JPS62125070U - - Google Patents

Info

Publication number
JPS62125070U
JPS62125070U JP1150986U JP1150986U JPS62125070U JP S62125070 U JPS62125070 U JP S62125070U JP 1150986 U JP1150986 U JP 1150986U JP 1150986 U JP1150986 U JP 1150986U JP S62125070 U JPS62125070 U JP S62125070U
Authority
JP
Japan
Prior art keywords
circuit
video signal
output
input video
delay circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1150986U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1150986U priority Critical patent/JPS62125070U/ja
Publication of JPS62125070U publication Critical patent/JPS62125070U/ja
Pending legal-status Critical Current

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Landscapes

  • Picture Signal Circuits (AREA)
  • Television Signal Processing For Recording (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は実施例の回路ブロツク図、第2図は波
形図、第3図は従来例の回路ブロツク図、第4図
は従来例の波形図である。 11…同期分離回路、12…遅延回路、17…
切換スイツチ、23…レベル可変回路。
FIG. 1 is a circuit block diagram of the embodiment, FIG. 2 is a waveform diagram, FIG. 3 is a circuit block diagram of the conventional example, and FIG. 4 is a waveform diagram of the conventional example. 11... Synchronization separation circuit, 12... Delay circuit, 17...
Changeover switch, 23...level variable circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力映像信号より同期信号を分離する同期分離
回路と、該同期分離回路出力を遅延して少なくと
も前記入力映像信号のバツクポーチ部分を含むパ
ルスを出力する遅延回路と、前記入力映像信号の
レベルを可変するレベル可変回路と、前記遅延回
路出力の前記レベル可変回路への印加を制御する
切換回路よりなる映像信号処理回路。
a sync separation circuit that separates a sync signal from an input video signal; a delay circuit that delays the output of the sync separation circuit to output a pulse containing at least a backpouch portion of the input video signal; and a delay circuit that varies the level of the input video signal. A video signal processing circuit comprising a level variable circuit and a switching circuit that controls application of the delay circuit output to the level variable circuit.
JP1150986U 1986-01-29 1986-01-29 Pending JPS62125070U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1150986U JPS62125070U (en) 1986-01-29 1986-01-29

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1150986U JPS62125070U (en) 1986-01-29 1986-01-29

Publications (1)

Publication Number Publication Date
JPS62125070U true JPS62125070U (en) 1987-08-08

Family

ID=30798790

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1150986U Pending JPS62125070U (en) 1986-01-29 1986-01-29

Country Status (1)

Country Link
JP (1) JPS62125070U (en)

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