JPS6381480U - - Google Patents
Info
- Publication number
- JPS6381480U JPS6381480U JP17440286U JP17440286U JPS6381480U JP S6381480 U JPS6381480 U JP S6381480U JP 17440286 U JP17440286 U JP 17440286U JP 17440286 U JP17440286 U JP 17440286U JP S6381480 U JPS6381480 U JP S6381480U
- Authority
- JP
- Japan
- Prior art keywords
- video signal
- horizontal synchronization
- predetermined amount
- delay
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003111 delayed effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Television Signal Processing For Recording (AREA)
Description
図面はいずれも本考案の実施例に係り、第1図
は回路ブロツク図、第2図は波形図、第3図は特
性図である。
20……第1遅延回路、21……第2遅延回路
。
The drawings all relate to embodiments of the present invention; FIG. 1 is a circuit block diagram, FIG. 2 is a waveform diagram, and FIG. 3 is a characteristic diagram. 20...first delay circuit, 21...second delay circuit.
Claims (1)
間が制御され、出力される第1遅延映像信号中の
水平同期信号と基準信号の位相差が所定量となる
よう動作する第1遅延回路と、この第1遅延映像
信号を入力として前記所定量に対応する固定遅延
量を有する第2遅延回路とよりなるスキユー補正
回路。 a first delay circuit whose delay time is controlled based on a horizontal synchronization signal in the reproduced video signal, and which operates so that the phase difference between the horizontal synchronization signal in the outputted first delayed video signal and the reference signal becomes a predetermined amount; A skew correction circuit comprising a second delay circuit receiving a first delayed video signal as an input and having a fixed delay amount corresponding to the predetermined amount.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17440286U JPS6381480U (en) | 1986-11-12 | 1986-11-12 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17440286U JPS6381480U (en) | 1986-11-12 | 1986-11-12 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6381480U true JPS6381480U (en) | 1988-05-28 |
Family
ID=31112751
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17440286U Pending JPS6381480U (en) | 1986-11-12 | 1986-11-12 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6381480U (en) |
-
1986
- 1986-11-12 JP JP17440286U patent/JPS6381480U/ja active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS6381480U (en) | ||
JPS60142859U (en) | Time base correction circuit | |
JPS59114664U (en) | synchronous circuit | |
JPS6293863U (en) | ||
JPS62168165U (en) | ||
JPS61109265U (en) | ||
JPH01153775U (en) | ||
JPS6455772U (en) | ||
JPS6448970U (en) | ||
JPH02116175U (en) | ||
JPS6314170U (en) | ||
JPS5850765U (en) | Vertical contour correction circuit | |
JPH01100583U (en) | ||
JPS63136475U (en) | ||
JPS58123393U (en) | electronic time switch | |
JPS6025240U (en) | frequency conversion circuit | |
JPS59114663U (en) | Vertical synchronization circuit | |
JPS60177539U (en) | Television receiver synchronization separation circuit | |
JPS6315684U (en) | ||
JPS63178920U (en) | ||
JPS6381565U (en) | ||
JPS63117183U (en) | ||
JPS6157751U (en) | ||
JPS60153060U (en) | Video signal synchronous conversion device | |
JPS6040164U (en) | Display clock generation circuit |