JPS62168165U - - Google Patents
Info
- Publication number
- JPS62168165U JPS62168165U JP5448686U JP5448686U JPS62168165U JP S62168165 U JPS62168165 U JP S62168165U JP 5448686 U JP5448686 U JP 5448686U JP 5448686 U JP5448686 U JP 5448686U JP S62168165 U JPS62168165 U JP S62168165U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- delay circuit
- video signal
- signal
- dropout
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims 1
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Television Signal Processing For Recording (AREA)
Description
第１図はこの考案の一実施例のブロツク図、第
２図及び第３図はこの考案の一実施例におけるク
ロツク発生回路の一例及び他の例を夫々示すブロ
ツク図、第４図はＴＢＣの一例のブロツク図であ
る。
図面における主要な符号の説明、１：再生ビデ
オ信号の入力端子、５，１３：スイツチ回路、７
：出力端子、８：ＣＣＤ遅延回路、１１：クロツ
ク発生回路、１２：基準発振器、１７：リターン
サブキヤリア信号の入力端子。
FIG. 1 is a block diagram of one embodiment of this invention, FIGS. 2 and 3 are block diagrams showing one example and another example of a clock generation circuit in one embodiment of this invention, and FIG. 4 is a block diagram of a TBC. FIG. 3 is a block diagram of an example. Explanation of main symbols in the drawings: 1: input terminal for playback video signal, 5, 13: switch circuit, 7
: Output terminal, 8: CCD delay circuit, 11: Clock generation circuit, 12: Reference oscillator, 17: Return subcarrier signal input terminal.
Claims (1)
路により遅延した信号をドロツプアウト検出信号
により制御されるスイツチ回路で切り替えるよう
にしたドロツプアウト補償回路において、 上記遅延回路を構成するＣＣＤ遅延回路と、上
記再生ビデオ信号と同期したＴＢＣからの基準信
号に基づいて上記ＣＣＤ遅延回路に対するクロツ
クパルスを発生する回路とを備えたドロツプアウ
ト補償回路。[Claims for Utility Model Registration] A dropout compensation circuit in which a playback video signal and a signal obtained by delaying the playback video signal by a delay circuit are switched by a switch circuit controlled by a dropout detection signal, a CCD constituting the delay circuit. A dropout compensation circuit comprising a delay circuit and a circuit for generating clock pulses for the CCD delay circuit based on a reference signal from a TBC synchronized with the reproduced video signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986054486U JPH0722769Y2 (en) | 1986-04-11 | 1986-04-11 | Dropout compensation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986054486U JPH0722769Y2 (en) | 1986-04-11 | 1986-04-11 | Dropout compensation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62168165U true JPS62168165U (en) | 1987-10-24 |
| JPH0722769Y2 JPH0722769Y2 (en) | 1995-05-24 |
Family
ID=30881524
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986054486U Expired - Lifetime JPH0722769Y2 (en) | 1986-04-11 | 1986-04-11 | Dropout compensation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0722769Y2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6094592A (en) * | 1983-10-28 | 1985-05-27 | Sony Corp | Dropout compensation circuit |
| JPS60251566A (en) * | 1984-05-26 | 1985-12-12 | Sony Corp | Reproduced signal correcting circuit |
-
1986
- 1986-04-11 JP JP1986054486U patent/JPH0722769Y2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6094592A (en) * | 1983-10-28 | 1985-05-27 | Sony Corp | Dropout compensation circuit |
| JPS60251566A (en) * | 1984-05-26 | 1985-12-12 | Sony Corp | Reproduced signal correcting circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0722769Y2 (en) | 1995-05-24 |
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