JPS63181037U - - Google Patents
Info
- Publication number
- JPS63181037U JPS63181037U JP7194787U JP7194787U JPS63181037U JP S63181037 U JPS63181037 U JP S63181037U JP 7194787 U JP7194787 U JP 7194787U JP 7194787 U JP7194787 U JP 7194787U JP S63181037 U JPS63181037 U JP S63181037U
- Authority
- JP
- Japan
- Prior art keywords
- input terminal
- controlled oscillator
- voltage controlled
- circuit
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000008929 regeneration Effects 0.000 claims description 3
- 238000011069 regeneration method Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図はこの考案の一実施例であるクロツク信
号再生回路のブロツク図、第２図は第１図の回路
の動作を説明するためのタイミング・チヤート、
第３図及び第４図は従来のクロツク信号再生回路
のブロツク図である。
FIG. 1 is a block diagram of a clock signal regeneration circuit which is an embodiment of this invention, and FIG. 2 is a timing chart for explaining the operation of the circuit of FIG.
FIGS. 3 and 4 are block diagrams of conventional clock signal regeneration circuits.
Claims (1)
端子が一方の入力端子に接続された位相比較回路
とから成るフエイズ・ロツク・ループと、 Ｂ 一方の入力端子が上記電圧制御発振器に接続
され、他方の入力端子がデジタル信号入力端子に
接続され、出力端子が上記位相比較回路の他方の
入力端子に接続された選択回路と、 Ｃ 上記デジタル信号入力端子から入力するデジ
タル信号に応じて上記選択回路から出力される信
号を決定する制御手段と、 を具備して成ることを特徴とするクロツク信号再
生回路。[Claims for Utility Model Registration] A. A phase lock loop consisting of a voltage controlled oscillator and a phase comparator circuit in which the output terminal of the voltage controlled oscillator is connected to one input terminal; B. a selection circuit connected to the voltage controlled oscillator, the other input terminal connected to the digital signal input terminal, and the output terminal connected to the other input terminal of the phase comparison circuit; A clock signal regeneration circuit comprising: control means for determining a signal output from the selection circuit according to the signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7194787U JPS63181037U (en) | 1987-05-14 | 1987-05-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7194787U JPS63181037U (en) | 1987-05-14 | 1987-05-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63181037U true JPS63181037U (en) | 1988-11-22 |
Family
ID=30914955
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7194787U Pending JPS63181037U (en) | 1987-05-14 | 1987-05-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63181037U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54111319A (en) * | 1978-02-21 | 1979-08-31 | Nec Corp | Phase synchronizing circuit |
-
1987
- 1987-05-14 JP JP7194787U patent/JPS63181037U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54111319A (en) * | 1978-02-21 | 1979-08-31 | Nec Corp | Phase synchronizing circuit |
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