JPH01140667U

JPH01140667U -

Info

Publication number: JPH01140667U
Application number: JP3583688U
Authority: JP
Priority date: 1988-03-18
Filing date: 1988-03-18
Publication date: 1989-09-26

Description

[Brief explanation of the drawing]

第１図は実施例のブロツク図、第２図は同実施
例のタイミングチヤート、第３図は従来例のブロ
ツク図、第４図は同従来例のタイミングチヤート
である。図中、１はデータ読み出し回路、３はサーボパ
ルス生成回路、５はＰＬＬ入力切替回路、７はＰ
ＬＬ回路、８はデータ復調回路、１０はリードク
ロツク、１１は第１のクロツク切替回路、２１は
分周器、２２はサーボクロツク、２３は固定発振
器、２４は第２のクロツク切替回路、２７は基準
クロツクである。なお、同一符号は同一又は相当
部分を示す。 FIG. 1 is a block diagram of an embodiment, FIG. 2 is a timing chart of the same embodiment, FIG. 3 is a block diagram of a conventional example, and FIG. 4 is a timing chart of the same conventional example. In the figure, 1 is a data readout circuit, 3 is a servo pulse generation circuit, 5 is a PLL input switching circuit, and 7 is a P
LL circuit, 8 is a data demodulation circuit, 10 is a read clock, 11 is a first clock switching circuit, 21 is a frequency divider, 22 is a servo clock, 23 is a fixed oscillator, 24 is a second clock switching circuit, 27 is a reference clock It is. Note that the same reference numerals indicate the same or equivalent parts.

Claims

[Scope of utility model registration request]

a data readout circuit, a servo pulse generation circuit, a PLL input switching circuit that outputs either the output of the data readout circuit or the output of the servo pulse generation circuit, and a PLL circuit that receives the output of the PLL input switching circuit. , a data demodulation circuit that receives the output of the data readout circuit and the output of the PLL circuit, a frequency divider that receives the output of the PLL circuit, and a read clock that is one of the outputs of the data demodulation circuit and the frequency divider. a first clock switching circuit that receives a servo clock as an output and outputs either one; and a first clock switching circuit that receives the output of the first clock switching circuit and a clock having the same frequency as the lead clock or the servo clock and outputs one of the clocks as a reference clock. a second clock switching circuit that controls the PLL input switching circuit; and a second clock switching circuit that controls the second clock switching circuit, causes the second clock switching circuit to normally output the output of the first clock switching circuit, and switches the PLL input switching circuit. A magnetic disk device characterized by comprising means for outputting a clock having the same frequency as the read clock or the servo clock for a certain period of time extending over an operating point.