JPH01151629U - - Google Patents
Info
- Publication number
- JPH01151629U JPH01151629U JP4685188U JP4685188U JPH01151629U JP H01151629 U JPH01151629 U JP H01151629U JP 4685188 U JP4685188 U JP 4685188U JP 4685188 U JP4685188 U JP 4685188U JP H01151629 U JPH01151629 U JP H01151629U
- Authority
- JP
- Japan
- Prior art keywords
- division ratio
- divider circuit
- circuit
- synchronous
- enlarged display
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Image Processing (AREA)
Description
第１図は本考案による水平拡大表示用のクロツ
ク分周回路の一実施例を示す回路構成図、第２図
は第１図の動作を示すタイミングチヤート、第３
図は従来の水平拡大表示用のクロツク分周回路を
例示する回路構成図、第４図は第３図の動作を示
すタイミングチヤートである。
ＣＯＵＮＴ……同期型カウンタ、Ｆ／Ｆ……同
期型遅延回路（フリツプフロツプ）、Ａ１，Ａ２
……アンドゲート、Ｎ１……ノツトゲート、ＮＡ
１……ノツトアンドゲート、ａ……原クロツク信
号入力端子、ｂ……並列データロード信号（同一
信号）入力端子、０〜３……拡大係数（分周
比）設定用入力端子、ｅ……分周出力。
FIG. 1 is a circuit configuration diagram showing an embodiment of a clock frequency dividing circuit for horizontal enlarged display according to the present invention, FIG. 2 is a timing chart showing the operation of FIG. 1, and FIG.
The figure is a circuit configuration diagram illustrating a conventional clock frequency divider circuit for horizontal enlarged display, and FIG. 4 is a timing chart showing the operation of FIG. 3. COUNT...Synchronous counter, F/F...Synchronous delay circuit (flip-flop), A1, A2
...and gate, N1...not gate, NA
1...Not and gate, a...Original clock signal input terminal, b...Parallel data load signal (same signal) input terminal, 0 to 3...Input terminal for setting expansion coefficient (frequency division ratio), e... Divide output.
Claims (1)
ク分周回路において、同期型遅延回路を設けるこ
とにより、分周出力が分周比にかかわりなく一定
の時点で立ち上るように構成したことを特徴とす
る水平拡大表示用のクロツク分周回路。 A clock divider circuit with a variable division ratio using a synchronous counter is characterized in that by providing a synchronous delay circuit, the divided output rises at a fixed point regardless of the division ratio. Clock frequency divider circuit for horizontally enlarged display.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4685188U JPH01151629U (en) | 1988-04-08 | 1988-04-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4685188U JPH01151629U (en) | 1988-04-08 | 1988-04-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01151629U true JPH01151629U (en) | 1989-10-19 |
Family
ID=31273097
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4685188U Pending JPH01151629U (en) | 1988-04-08 | 1988-04-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01151629U (en) |
-
1988
- 1988-04-08 JP JP4685188U patent/JPH01151629U/ja active Pending
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