JPS60586U - electronic watch body - Google Patents
electronic watch bodyInfo
- Publication number
- JPS60586U JPS60586U JP7114584U JP7114584U JPS60586U JP S60586 U JPS60586 U JP S60586U JP 7114584 U JP7114584 U JP 7114584U JP 7114584 U JP7114584 U JP 7114584U JP S60586 U JPS60586 U JP S60586U
- Authority
- JP
- Japan
- Prior art keywords
- frequency divider
- output
- input
- display counter
- flip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Measurement Of Unknown Time Intervals (AREA)
- Electric Clocks (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は一般の電子時計の構成を示す。第2図は最小時
間単位が0.1秒である電子時計を従来の技術で実現す
る例であって水晶振動子は40960Hzの固有振動数
である。第4図は従来の方法で二つの異なる最小時間単
位を持つ計数器系列で構成される時計体の実現方法の例
である。第4図は水晶振動子生産に伴なうでき上がりの
周波数のバラツキを示す。第5図は生産量に対するでき
上がり周波数のバラツキの変化を示す。第6図は本考案
による二つの異なる最小時間単位を持った計数器系列で
構成される時計体の実現例で12は可変分周器、13は
その制御ゲートである。第7図は本考案の他の実施例で
ある。第8図は第6図に示す実施例のタイミングチャー
トであり、第9図は上記タイミングの詳細図である。第
10図は第7図に示す実施例のタイミングチャートであ
る。
第11図は第6図に示す実施例のさらに具体的な回路図
であり、15は計数部(0,1秒単位)、16は可変分
周器、17はその制御ゲートを示す。第12図は第11
図に詳説する実施例のタイミングチャートであり、第1
3図はそのさらに詳細なタイミング図の一部である。FIG. 1 shows the configuration of a general electronic timepiece. FIG. 2 shows an example of realizing an electronic clock whose minimum time unit is 0.1 seconds using conventional technology, and the crystal resonator has a natural frequency of 40,960 Hz. FIG. 4 is an example of a conventional method for realizing a clock body composed of counter series having two different minimum time units. FIG. 4 shows the variation in frequency of finished crystals due to crystal resonator production. FIG. 5 shows the variation in finished frequency with respect to production volume. FIG. 6 shows an example of the realization of a clock body composed of a counter series having two different minimum time units according to the present invention, where 12 is a variable frequency divider and 13 is its control gate. FIG. 7 shows another embodiment of the present invention. FIG. 8 is a timing chart of the embodiment shown in FIG. 6, and FIG. 9 is a detailed diagram of the above timing. FIG. 10 is a timing chart of the embodiment shown in FIG. FIG. 11 is a more specific circuit diagram of the embodiment shown in FIG. 6, with reference numeral 15 indicating a counting section (in units of 0 and 1 seconds), 16 indicating a variable frequency divider, and 17 indicating its control gate. Figure 12 is the 11th
2 is a timing chart of the embodiment detailed in the figure;
Figure 3 is part of a more detailed timing diagram.
Claims (1)
能を有する電子式時計体において、水晶振動子と第1の
分周器を共用し、前記第1の分周器出力は第2の分周器
と第3の分周器に入力され、前記第2の分周器出力は時
刻表示用計数器に入力され、前記第3の分周器出力はク
ロノグラフ表示用計数器に入力され、前記第3の分周器
は可変分周器とゲート部より構成され、前記ゲート部は
R−Sフリップフロップを含み、前記ゲート回路は前記
可変分周器出力と前記クロノグラフ表示用計数器出力の
一部とを入力し、前記ゲート部を構成するR−Sフリッ
プフロップの出力を前記可変分周器を構成する複数のデ
ータ型フリップフロップのリセット入力とし、前記第3
の分周器は異なる分周比を交互に繰り返し、前記第1の
分周器出力はlHzより高い周波数であり、前記第3の
分周器出力は107F?、H2(mは正の整数)の信号
′を出力することを特徴とする電子式時計体。In an electronic watch body having at least multiple display functions of time display and chronograph display, the crystal oscillator and the first frequency divider are shared, and the output of the first frequency divider is shared with the second frequency divider. The second frequency divider output is input to a time display counter, the third frequency divider output is input to a chronograph display counter, and the third frequency divider output is input to a chronograph display counter. The frequency divider is composed of a variable frequency divider and a gate section, the gate section includes an R-S flip-flop, and the gate circuit outputs a part of the output of the variable frequency divider and the output of the chronograph display counter. and the output of the R-S flip-flop constituting the gate section is used as a reset input of a plurality of data type flip-flops constituting the variable frequency divider, and the third
The frequency divider alternates between different frequency division ratios, the first frequency divider output is at a frequency higher than 1Hz, and the third frequency divider output is 107F? , H2 (m is a positive integer).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7114584U JPS60586U (en) | 1984-05-16 | 1984-05-16 | electronic watch body |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7114584U JPS60586U (en) | 1984-05-16 | 1984-05-16 | electronic watch body |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60586U true JPS60586U (en) | 1985-01-05 |
JPS614871Y2 JPS614871Y2 (en) | 1986-02-14 |
Family
ID=30201294
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7114584U Granted JPS60586U (en) | 1984-05-16 | 1984-05-16 | electronic watch body |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60586U (en) |
-
1984
- 1984-05-16 JP JP7114584U patent/JPS60586U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS614871Y2 (en) | 1986-02-14 |
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