JPS60586U - electronic watch body - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

FIG. 1 shows the configuration of a general electronic timepiece. FIG. 2 shows an example of realizing an electronic clock whose minimum time unit is 0.1 seconds using conventional technology, and the crystal resonator has a natural frequency of 40,960 Hz. FIG. 4 is an example of a conventional method for realizing a clock body composed of counter series having two different minimum time units. FIG. 4 shows the variation in frequency of finished crystals due to crystal resonator production. FIG. 5 shows the variation in finished frequency with respect to production volume. FIG. 6 shows an example of the realization of a clock body composed of a counter series having two different minimum time units according to the present invention, where 12 is a variable frequency divider and 13 is its control gate. FIG. 7 shows another embodiment of the present invention. FIG. 8 is a timing chart of the embodiment shown in FIG. 6, and FIG. 9 is a detailed diagram of the above timing. FIG. 10 is a timing chart of the embodiment shown in FIG. FIG. 11 is a more specific circuit diagram of the embodiment shown in FIG. 6, with reference numeral 15 indicating a counting section (in units of 0 and 1 seconds), 16 indicating a variable frequency divider, and 17 indicating its control gate. Figure 12 is the 11th
2 is a timing chart of the embodiment detailed in the figure;
Figure 3 is part of a more detailed timing diagram.

Claims (1)

[Scope of utility model registration request] In an electronic watch body having at least multiple display functions of time display and chronograph display, the crystal oscillator and the first frequency divider are shared, and the output of the first frequency divider is shared with the second frequency divider. The second frequency divider output is input to a time display counter, the third frequency divider output is input to a chronograph display counter, and the third frequency divider output is input to a chronograph display counter. The frequency divider is composed of a variable frequency divider and a gate section, the gate section includes an R-S flip-flop, and the gate circuit outputs a part of the output of the variable frequency divider and the output of the chronograph display counter. and the output of the R-S flip-flop constituting the gate section is used as a reset input of a plurality of data type flip-flops constituting the variable frequency divider, and the third
The frequency divider alternates between different frequency division ratios, the first frequency divider output is at a frequency higher than 1Hz, and the third frequency divider output is 107F? , H2 (m is a positive integer).