JPS6093988U - digital clock - Google Patents
digital clockInfo
- Publication number
- JPS6093988U JPS6093988U JP18705883U JP18705883U JPS6093988U JP S6093988 U JPS6093988 U JP S6093988U JP 18705883 U JP18705883 U JP 18705883U JP 18705883 U JP18705883 U JP 18705883U JP S6093988 U JPS6093988 U JP S6093988U
- Authority
- JP
- Japan
- Prior art keywords
- minute
- display
- hour
- digital clock
- clock signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electric Clocks (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のデジタル時計の構成図、第２図は本考案
の一実施例によるデジタル時計の構成図である。
図において、１はタイムベース、１２は時、分信号作成
手段（マイクロコンピュータ）、１４は表示手段（７セ
グメントＬＥＤ ）である。なお、図中同一符号は同−
又は相当部分を示す。FIG. 1 is a block diagram of a conventional digital watch, and FIG. 2 is a block diagram of a digital watch according to an embodiment of the present invention. In the figure, 1 is a time base, 12 is an hour and minute signal generating means (microcomputer), and 14 is a display means (7 segment LED). In addition, the same symbols in the figures are the same.
or a corresponding portion.
Claims (1)
ースと、時又は分の上位桁と下位桁の各々を０から９の
数字で表示するための２つの表示部を有する表示手段と
、上記タイムベースからのクロック信号をカウントして
時、分を示す時、分信号を作成し時と分を所定時間毎に
又は１秒毎に交互に表示する交互表示を１秒周期又は２
秒周期で行なうよう上記両信号を交互に上記表示手段に
出力する時、分信号作成出力手段とを備えたことを特徴
とするデジタル時計。a time base that outputs a clock signal that is the basis of time display; a display means having two display sections for displaying each of the upper and lower digits of the hour or minute as numbers from 0 to 9; and the time base. The hour and minute signals are created by counting the clock signal from
A digital timepiece characterized by comprising: minute signal generation/output means for alternately outputting both of the above signals to the display means so as to be performed at a second cycle.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18705883U JPS6093988U (en) | 1983-12-01 | 1983-12-01 | digital clock |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18705883U JPS6093988U (en) | 1983-12-01 | 1983-12-01 | digital clock |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6093988U true JPS6093988U (en) | 1985-06-26 |
Family
ID=30403877
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18705883U Pending JPS6093988U (en) | 1983-12-01 | 1983-12-01 | digital clock |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6093988U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4933678A (en) * | 1972-07-24 | 1974-03-28 |
-
1983
- 1983-12-01 JP JP18705883U patent/JPS6093988U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4933678A (en) * | 1972-07-24 | 1974-03-28 |
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