JPH02120933U - - Google Patents

Info

Publication number
JPH02120933U
JPH02120933U JP3052689U JP3052689U JPH02120933U JP H02120933 U JPH02120933 U JP H02120933U JP 3052689 U JP3052689 U JP 3052689U JP 3052689 U JP3052689 U JP 3052689U JP H02120933 U JPH02120933 U JP H02120933U
Authority
JP
Japan
Prior art keywords
stage
flop
type flip
output
supplied
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3052689U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3052689U priority Critical patent/JPH02120933U/ja
Publication of JPH02120933U publication Critical patent/JPH02120933U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案による分周回路の実施例を示す
ブロツク図、第2図は第1図において遅延素子の
デイレイ量を原クロツク周期の4倍として11分
周を行なつた時の各部の波形を示すタイミング図
、第3図は第1図において遅延素子のデイレイ量
を変化させた時の分周されたクロツク信号を示す
タイミング図、第4図は従来技術による分周回路
の一例(11分周)を示すブロツク図である。 11,12,21〜26……D形フリツプフロ
ツプ、13……AND回路、14……遅延素子、
101〜107……信号線。
Fig. 1 is a block diagram showing an embodiment of the frequency divider circuit according to the present invention, and Fig. 2 shows the components of Fig. 1 when the delay amount of the delay element is set to 4 times the original clock period and the frequency is divided by 11. FIG. 3 is a timing diagram showing the frequency-divided clock signal when the delay amount of the delay element is changed in FIG. FIG. 2 is a block diagram showing frequency division. 11, 12, 21-26...D flip-flop, 13...AND circuit, 14...delay element,
101-107...Signal lines.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 前段D形フリツプフロツプの一方の入力段にク
ロツク信号を供給し、前記前段D形フリツプフロ
ツプの反転出力と前記前段D形フリツプフロツ
プの出力側に接続した後段D形フリツプフロツプ
の出力との論理積をとつた信号を遅延素子を介
して前記前段フリツプフロツプの他方の入力側に
供給したことを特徴とする分周回路。
A clock signal is supplied to one input stage of a front-stage D-type flip-flop, and a signal is obtained by performing the logical product of the inverted output of the front-stage D-type flip-flop and the output of a rear-stage D-type flip-flop connected to the output side of the front-stage D-type flip-flop. is supplied to the other input side of the front-stage flip-flop via a delay element.
JP3052689U 1989-03-16 1989-03-16 Pending JPH02120933U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3052689U JPH02120933U (en) 1989-03-16 1989-03-16

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3052689U JPH02120933U (en) 1989-03-16 1989-03-16

Publications (1)

Publication Number Publication Date
JPH02120933U true JPH02120933U (en) 1990-10-01

Family

ID=31255657

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3052689U Pending JPH02120933U (en) 1989-03-16 1989-03-16

Country Status (1)

Country Link
JP (1) JPH02120933U (en)

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