JPS62129841U - - Google Patents
Info
- Publication number
- JPS62129841U JPS62129841U JP1804486U JP1804486U JPS62129841U JP S62129841 U JPS62129841 U JP S62129841U JP 1804486 U JP1804486 U JP 1804486U JP 1804486 U JP1804486 U JP 1804486U JP S62129841 U JPS62129841 U JP S62129841U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- shift register
- circuit
- frequency
- division ratio
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図は本考案の同期式分周回路の一実施例を
示す回路図、第２図は第１図に示す回路において
信号Ｓ１が０、信号Ｓ２が０の場合の回路動作を
示すタイムチヤート、第３図は同回路において信
号Ｓ１が１、信号Ｓ２が０の場合の回路動作を示
すタイムチヤート、第４図は同回路において信号
Ｓ１が０、信号Ｓ２が１の場合の回路動作を示す
タイムチヤート、第５図は同回路において信号Ｓ
１が１、信号Ｓ２が１の場合の回路動作を示すタ
イムチヤートである。
１〜３……シフトレジスタ、４……排他的論理
和回路、５，６……論理積回路、７……反転回路
。
Fig. 1 is a circuit diagram showing an embodiment of the synchronous frequency divider circuit of the present invention, and Fig. 2 is a time chart showing the circuit operation when the signal S1 is 0 and the signal S2 is 0 in the circuit shown in Fig. 1. , Fig. 3 is a time chart showing the circuit operation when the signal S1 is 1 and the signal S2 is 0 in the same circuit, and Fig. 4 is a time chart showing the circuit operation when the signal S1 is 0 and the signal S2 is 1 in the same circuit. Time chart, Figure 5 shows the signal S in the same circuit.
This is a time chart showing the circuit operation when 1 is 1 and signal S2 is 1. 1 to 3...shift register, 4...exclusive OR circuit, 5, 6...AND circuit, 7...inverting circuit.
Claims (1)
段のシフトレジスタを備え、前記Ｎ段シフトレジ
スタのうちの第Ｎ番目のシフトレジスタの出力信
号を反転回路に加え、この反転回路の出力信号を
前記Ｎ段シフトレジスタのうちの第１番目のシフ
トレジスタに入力し、分周比設定信号に応じた分
周比で前記クロツク信号を分周して出力する同期
式分周回路において、前記Ｎ段シフトレジスタの
うちの第１番目から第（Ｎ―１）番目をリセツト
端子を備えたシフトレジスタとし、これら（Ｎ―
１）個のリセツト端子付シフトレジスタに各々対
応する（Ｎ―１）個の論理積回路を備え、前記リ
セツト端子は対応する前記論理積回路の出力端に
各々接続し、前記論理積回路の第１の入力端は前
記Ｎ番目のシフトレジスタの出力に接続し、前記
分周比設定信号は（Ｎ―１）個の前記論理積回路
の第２の入力端に加えられる論理信号であること
を特徴とする同期式分周回路。 N to shift the input signal according to the clock signal
The output signal of the N-th shift register of the N-stage shift registers is applied to an inverting circuit, and the output signal of the inverting circuit is applied to the first shift register of the N-stage shift registers. In a synchronous frequency divider circuit that divides the frequency of the clock signal by a frequency division ratio according to a frequency division ratio setting signal input to a register and outputs the frequency, the first to (N- 1) The shift register is equipped with a reset terminal, and these (N-
1) (N-1) logical product circuits each corresponding to a shift register with a reset terminal, each of the reset terminals being connected to an output terminal of the corresponding logical product circuit, 1 is connected to the output of the N-th shift register, and the division ratio setting signal is a logic signal applied to the second input terminals of the (N-1) AND circuits. Features a synchronous frequency divider circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1804486U JPS62129841U (en) | 1986-02-10 | 1986-02-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1804486U JPS62129841U (en) | 1986-02-10 | 1986-02-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62129841U true JPS62129841U (en) | 1987-08-17 |
Family
ID=30811360
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1804486U Pending JPS62129841U (en) | 1986-02-10 | 1986-02-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62129841U (en) |
-
1986
- 1986-02-10 JP JP1804486U patent/JPS62129841U/ja active Pending
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