JPH0230643U - - Google Patents
Info
- Publication number
- JPH0230643U JPH0230643U JP10830388U JP10830388U JPH0230643U JP H0230643 U JPH0230643 U JP H0230643U JP 10830388 U JP10830388 U JP 10830388U JP 10830388 U JP10830388 U JP 10830388U JP H0230643 U JPH0230643 U JP H0230643U
- Authority
- JP
- Japan
- Prior art keywords
- preset
- counter
- input
- output
- bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010363 phase shift Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図は本考案第１の実施例の構成を示す回路
図、第２図は本考案第１実施例の各種信号の発生
タイミングを示すタイミングチヤート、第３図は
本考案第２実施例の構成を示す回路図、第４図は
本考案第２実施例の各種信号の発生タイミングを
示すタイミングチヤート、第５図は従来例の構成
を示す回路図、第６図は従来例の各種信号の発生
タイミングを示すタイミングチヤートである。
１〜６…フリツプフロツプ、７〜１０…イクス
クルーシブオア（ＯＲ）回路、ＰＲ…プリセツト
入力（信号）、…カウント入力（信号）、Ｑ
Ａ〜ＱＤ…カウンタのビツト出力（信号）。
FIG. 1 is a circuit diagram showing the configuration of the first embodiment of the present invention, FIG. 2 is a timing chart showing the generation timing of various signals in the first embodiment of the present invention, and FIG. 3 is a circuit diagram of the second embodiment of the present invention. FIG. 4 is a timing chart showing the generation timing of various signals in the second embodiment of the present invention, FIG. 5 is a circuit diagram showing the configuration of the conventional example, and FIG. 6 is a timing chart showing the generation timing of various signals in the conventional example. This is a timing chart showing the timing of occurrence. 1 to 6...Flip-flop, 7 to 10...Exclusive OR (OR) circuit, PR...Preset input (signal),...Count input (signal), Q
A to QD...Counter bit output (signal).
Claims (1)
リセツト信号に応じて所定値にプリセツトされる
複数のビツト構成のカウンタ回路と、 所望のプリセツト値と前記所定値との差分に相
当するビツトだけ、前記カウンタ回路の出力を移
相して出力する移相回路とを具えたことを特徴と
するプリセツトカウンタ。 (2) 請求項１に記載のプリセツトカウンタにお
いて、前記移相回路は、前記カウンタ回路の出力
の各々のビツトが一方の入力に入力され、この入
力を前記所望のプリセツト値となるように他方の
入力の状態に応じてレベル反転して出力する論理
回転を具えたことを特徴とするプリセツトカウン
タ。[Claims for Utility Model Registration] (1) A counter circuit having a flip-flop for each bit and having a plurality of bits that is preset to a predetermined value in response to a preset signal, and a difference between a desired preset value and the predetermined value. 1. A preset counter comprising: a phase shift circuit that shifts the phase of the output of the counter circuit by a bit corresponding to . (2) In the preset counter according to claim 1, the phase shift circuit is configured such that each bit of the output of the counter circuit is inputted to one input, and this input is inputted to the other input so that each bit of the output of the counter circuit becomes the desired preset value. 1. A preset counter comprising a logical rotation that inverts the level and outputs the output according to the state of the input.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10830388U JPH0230643U (en) | 1988-08-19 | 1988-08-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10830388U JPH0230643U (en) | 1988-08-19 | 1988-08-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0230643U true JPH0230643U (en) | 1990-02-27 |
Family
ID=31343505
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10830388U Pending JPH0230643U (en) | 1988-08-19 | 1988-08-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0230643U (en) |
-
1988
- 1988-08-19 JP JP10830388U patent/JPH0230643U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0230643U (en) | ||
| JPS61140221A (en) | Timing generating circuit | |
| JPH03120127U (en) | ||
| JPS6347625U (en) | ||
| JPS62129841U (en) | ||
| JPH01143527U (en) | ||
| JPS5995500U (en) | Storage device | |
| JPS59129249U (en) | Phase continuous FS modulation circuit | |
| JPH0286247U (en) | ||
| JPH0298527U (en) | ||
| JPH01100534U (en) | ||
| JPS62109522U (en) | ||
| JPS58124895U (en) | Alarm signal holding circuit | |
| JPS6435425U (en) | ||
| JPS6181223U (en) | ||
| JPS5986742U (en) | Programmable timing generation circuit | |
| JPH0386456U (en) | ||
| JPS61160556U (en) | ||
| JPH01133828U (en) | ||
| JPS58172881U (en) | frequency detection circuit | |
| JPH0226823U (en) | ||
| JPS6198272U (en) | ||
| JPS6331404U (en) | ||
| JPS63108233U (en) | ||
| JPS6157751U (en) |