JPS61140221A - Timing generating circuit - Google Patents

Abstract

PURPOSE:To keep phase relation of divided frequency output signals to a prescribed phase relation by providing a counter that resets the flip-flop of each frequency divider for each original clock of the least common multiple of dividing ratio of each frequency divider. CONSTITUTION:Each frequency divider 3 and a counter for resetting 5 are operated by clock from an original clock oscillating circuit 4. A counter 5 sends a reset pulse to each frequency divider 3 when original clock of the least common multiple of frequency dividing ratio of each frequency divider is counted, and resets each frequency divider. Each frequency divider is made to start dividing from reset, that is, the state in which initial output is at low level. As resetting is made for each clock number of original clock signals of least common multiple of each frequency dividing ratio, when once resetting is made, resetting is made at a time when all flip-flop output of each dividing circuit 3 is at low level in the state of stable operation free from noise etc., and consequently, no influence is given to output from the dividing circuit 3 by by reset pulse.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a circuit that generates signals of a plurality of frequencies from a single clock source using a plurality of frequency dividers. Each of these relates to a timing generation circuit having a certain timing pattern.

[Conventional technology]

Generally, in an asynchronous frequency divider, a flip-flop or the like is used to divide the frequency of a clock signal. Therefore, when a single original clock is divided by multiple frequency dividers to generate synchronized signals of multiple frequencies, the timing pattern (phase relationship) of the synchronization at each frequency is different from that at power-on. It is determined by the state (initial state) of the output of each 7-lip 70-g of each frequency divider.

[Problem that the invention seeks to solve]

In other words, when the power is turned on, the initial state of the 7-channel and 7-channel outputs of each frequency divider is not constant, so the phase relationship between the frequencies generated from the timing circuit may change each time the power source is switched. comes out. For example 1
74 The timing circuit that generates two types of division frequencies, 1/6 frequency division and 1/6 frequency division, divides the original clock into 1/4 frequency division circuit and 17
The frequency is divided by a 6 frequency divider circuit, as shown in Figure 4.
Two phase relationships, 1 and 2, are possible depending on the initial states of the 1/4 frequency divider circuit and the 176 frequency divider circuit. Which of these two phase relationships will be determined depends on the initial state of the 7 lip-flops of the 1/4 and 1/6 frequency dividers when the power is turned on.

Furthermore, even during the operation of the timing circuit, if synchronization is once lost due to the influence of noise or the like and then synchronized again, there is a possibility that the phase relationship before the loss of synchronization and the phase relationship after resynchronization may change.

In general, when the above-mentioned development occurs, the 7 lip-flops of each frequency dividing circuit are reset to the initial state when the power is turned on. By this reset, the initial state of the 7 lip-flops in each frequency divider circuit becomes the same level, so the phase relationship of the divided frequency signals from each frequency divider is always fixed at 1.
It settles into two phase relationships.

However, such a reset to the initial state cannot solve the case where synchronization is lost during operation.

[Failure to solve the problem]

The timing generation circuit according to the present invention includes a plurality of frequency dividers that divide the original clock, an output means for obtaining a plurality of outputs with different division ratios from the plurality of frequency dividers, and a common multiple of each division ratio of the plurality of outputs. and means for resetting all the frequency dividers every time the frequency is divided.

In other words, each frequency divider is reset for each division that is a common multiple of each division ratio of multiple outputs, so even if each frequency divider loses synchronization due to noise, the phase relationship of each output can be quickly and automatically corrected. It can be restored.

〔Example〕

Next, the present invention will be explained in more detail with reference to the drawings.

FIG. 1 shows a schematic block diagram according to an embodiment of the present invention, and FIG. 2 shows a specific example of a configuration including a 1/4 frequency divider and a 1/6 frequency divider. 3 is a frequency divider with a different frequency division ratio, 4 is an original clock oscillation circuit, 5 is a counter that counts the original clock by the least common multiple of the division ratio, 6 is a reset line for resetting the frequency divider, and 7 is an original clock. This is the clock line.

Each frequency divider 3 and reset circuit 5 operate according to the clock from the original clock oscillation circuit 4. Kara/ri5
sends a reset pulse to each frequency divider 3 to reset each frequency divider 3 at the time when the original clock of the least common multiple of the frequency division ratio of each frequency divider 3 is counted.

In each frequency divider 3, division is started from a reset, that is, from a state in which the initial output state is at a low level.

Since the reset is performed every clock number of the original clock signal that is the least common multiple of each division ratio, once the reset is applied, in a stable operating state without noise etc., all 7 lip-flop outputs of each frequency divider circuit 3 will be at a low level. A reset is applied at this point, and as a result, the output from the frequency divider circuit 3 is not affected by the reset pulse.

Further, even if the phase relationship changes during operation, the seven lip-flops of each frequency divider 3 are always reset for each original clock of the least common multiple of each division ratio, so that the phase relationship always returns to the specified one at this point.

FIG. 3 shows, as an example, a timing generation circuit composed of two types of frequency dividers, a 174 frequency divider and a 1/6 frequency divider. 8 is a 1/4 frequency division frequency output terminal, 9 is a 1/6 frequency division frequency output terminal, 10 is a 174 frequency divider flip-flop,
11 is a slip 70 tube that constitutes a 1/6 frequency divider, 11
' is a NOR gate in the 1/6 frequency divider. Also,
Reference numeral 12 indicates 7 lips and 70 tubes for counting/counting, and in this example, the 7 lips and 70 tubes in the 1/6 frequency dividing circuit are also used for counting. 13 is an original clock oscillation circuit, 14 is an original clock line, 15 to 17 are count signal lines from the counter, and 18 is a reset line to the 1/4 frequency divider.

The original clock from the original clock circuit 13 is divided into 1/4 and 1
/6 and output from each output terminal 9. At this time, the flip-flop 11 in the 1/6 frequency divider circuit and the flip-flop 12 receiving its output function as a counter and count the original clock by 12 and output a reset signal.

In other words, the output signal lines 15 to 17 and 9 from each 7-rip 70 tube 11 and 12 are all at a low level every 12 original clocks, and the OR gate 19 outputs the reset signal /18 of the 1/4 frequency divider. A low level reset signal is output. This count number 12 is the least common multiple of the frequency division ratios 4 and 6. From now on, a reset is required every 12 original clocks, but the time it takes for the reset is the period during which all the outputs of the 1/4 frequency divider's 7 rip 70 tug 10 are at a low level, so the result is The reset signal is 1
/4 frequency divider. This situation is shown in Figure 4. In the above explanation, each 7-lip 70-tub is reset when a low level is input to the reset terminal, and for the clock φ input, the data latched at the D input terminal is output from the Q output at the falling edge. 9.

〔Effect of the invention〕

In a timing circuit that generates multiple types of divided frequencies from a single source using multiple types of frequency dividers, the present invention provides a timing circuit that generates multiple types of divided frequencies using multiple types of frequency dividers. By providing a counter that resets the 7 and 70 loops of the receiver, the phase relationship of each branch frequency output signal can be maintained at a certain prescribed phase relationship.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a specific circuit diagram of an embodiment of the invention, and FIG. 3 is a timing chart of an embodiment of the invention. FIG. 4 is an output timing diagram of a conventional timing generation circuit. 1...First phase relationship between the 1/4 frequency division frequency and the 1/6 frequency division frequency, 2...The first phase relationship between the 1/4 frequency division frequency and the 1/6 frequency division frequency Second phase relationship, 3...
Frequency dividers with different mutual frequency division ratios, 4...Original clock oscillation circuit, 5...Counter, 6...Reset signal 2/, 7...・Original clock line,
8...1/4 frequency division frequency output terminal, 9...
-1/ 6 frequency division frequency output terminal, 10...1/
7 lip-flops of 4 frequency divider, 11...1/6
7 lip flops of frequency divider, 12...7 lip flops of counter, 13...original clock oscillation circuit, 14...original clock line, 15...
... Signal twin from the counter, 16... Signal fin from the counter, 17... Signal line from the counter, 18... Reset signal line, 19... ...OR gate.

Claims (1)

[Claims] a plurality of frequency dividers for frequency dividing a single original clock signal; means for obtaining output signals of a plurality of types of frequencies from the plurality of frequency dividers; and counting a common multiple of frequency division ratios of the plurality of types of output signals. and means for resetting the frequency divider each time the frequency divider is reset.