JPS61255125A - Reference phase generating circuit - Google Patents

Abstract

PURPOSE:To avoid an output signal from being disturbed at the switching of a reference phase signal by providing a detection means detecting the number of changing points of an output of a frequency divider and a gate means applying an output of the detection means as a control signal for plural frequency dividers synchronously with the selection control of a selection means. CONSTITUTION:A frequency divider 3 inputting an f01 clock (a) is a 1/(n+1) frequency division counter circuit having addresses 0-n as shown in figure (b) and an output of the frequency divider 3 being a reference phase input to a phase synchronous oscillation circuit 6 is outputted to the location of the address 0 as shown in figure (c). A frequency divider 4 inputting an f02 clock acts similarly. The output of differentiation devices 9,10 is inputted to the selection section, which gives an output to the frequency divider 4 when a selector 8 selects the output of the frequency divider 3 and gives an output to the frequency divider 3 conversely when the output of the frequency divider 4 is selected. On the other hand, suppose that the frequency division is restarted from the address 0 in each frequency divider according to the output of the selection section, it is controlled that while one reference phase output is selected, the output phase of the other frequency divider is matched always with the output phase of the frequency divider in operation.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a reference phase generation circuit for a phase synchronized oscillation circuit in a digital dependent synchronization network, and more particularly to a reference phase generation circuit for input clock signals of a plurality of different frequencies.

11 and 1 Conventionally, this type of circuit has a ff
The clock inputs having two different frequencies are divided by frequency dividers 1 and 2, respectively, and the outputs of these frequency dividers are selected by the switching means 7 as the reference phase signal to the phase synchronized oscillation circuit 5. Ta.

However, in the conventional circuit described above, the switching means is manually operated using a switch or the like, and there is a drawback that the output of the phase synchronized oscillation circuit is disturbed at the time of switching due to the phase difference between the reference phase signals of the outputs of each frequency divider.

11. Summary of the Invention The present invention has been made to eliminate the drawbacks of the conventional circuits as described above, and an object of the present invention is to provide a reference phase generation circuit that does not cause disturbances in the output signal when switching the reference phase signal.

11. The reference phase generation circuit according to the present invention includes a plurality of frequency dividers provided corresponding to a plurality of clock inputs having different frequencies, and selects one of the outputs of these frequency dividers to generate a phase synchronized oscillator. A selection means as an input, a detection means for detecting a change point of the output of the frequency divider, and a gate means for supplying the output of the detection means as a control signal for a plurality of frequency dividers in synchronization with the selection control of the selection means. It is characterized by having the following.

1 pho 1 Next, the present invention will be explained with reference to the drawings.

Reference numeral 1511 is a block diagram showing an embodiment of the present invention, and FIG. 2 shows its timing diagram. Note that the clock input has two frequencies f 1 and f 2 .

Now, the frequency divider 3 which receives the '01 clock (FIG. 2(a)) is assumed to be an (n+1) division counter circuit with addresses 0 to n, as shown in FIG. 2(b). It is also assumed that the output of the frequency divider 3, which serves as the reference phase input of the phase synchronized oscillation circuit 6, is output to the address O as shown in FIG. 2(C).

On the other hand, the frequency divider 4 which receives f02 as an input performs the same operation, and its output is selected by the selector 8 as a reference phase signal having the same frequency as that of the frequency divider 3, and is inputted to the phase synchronized oscillation circuit 6.

In addition, the reference phase signal, which is the output of the frequency divider 3.4, is output by detecting the rising and changing points of the signal (Fig. 2 (b)).
is input to a differentiator 9.10. This differentiator 9.10
The output of Nant gate 11, 12 and inverter 13
The input is input to a selection section consisting of a selector 8.
When selects the output of frequency divider 3, it is output to frequency divider 4, and conversely, when it selects the output of frequency divider 4, it outputs to frequency divider 3.
It operates to output for.

On the other hand, each frequency divider follows the output of this selection section and restarts the division operation from 0. When one reference phase output is selected, the other frequency divider always divides its output phase into the active division. It will be controlled to match the frequency output phase. As a result, the phase difference between the outputs of each frequency divider can be suppressed to within one pit of the input clock signal.

As explained above, the present invention enables the phase difference to be within 1 pit of the input clock by feeding back the output phase during operation to another frequency divider, so that the input clock is equal to the reference phase. If the signal is sufficiently fast, even if this reference phase signal is switched, the phase synchronized oscillator will be hardly affected by it and the output signal will not be disturbed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an operation timing diagram thereof, and FIG. 3 is a block diagram showing a conventional example. Explanation of symbols of main parts 1.2.3.4... Frequency divider 5.6 -... Phase synchronized oscillator 8... Selector 9.10...・Differentiator

Claims (1)

[Claims] a plurality of frequency dividers provided corresponding to a plurality of clock inputs having different frequencies; a selection means for selecting one of the outputs of the frequency dividers as an input to a phase synchronized oscillator; A reference phase generator comprising: a detection means for detecting a change point; and a gate means for supplying the output of the detection means as a control signal for the plurality of frequency dividers in synchronization with the selection control of the selection means. circuit.