JPH01177216A - Signal generation system - Google Patents

Abstract

PURPOSE:To reduce bad influences of the distortion and delays of clocks following the reduction in the number of transmission lines when the clocks are distributed to other circuits from a clock generating circuit by distributing two kinds of clocks, system clocks and reference clocks, only. CONSTITUTION:A base plate 1 is provided with a system clock generating circuit 1a which generates clocks (system clocks) of the highest frequency to be used in this system and a reference clock generating circuit 1b which generates clocks (reference clocks) obtained by frequency-dividing the system clocks by the least common multiple of the clocks used in this system. By causing the clock generating circuits 1a and 1b to generate the two kinds of clocks and distribute the clocks to other circuits, (n) kinds of clocks to be used can be generated from the two kinds of clocks only at a receiving-side circuit. Namely, the clock to be transmitted at a high speed become the clocks of the highest frequency of the system only. Therefore, bad influences of delay and distortion of clocks on transmission lines can be reduced.

Description

[Detailed description of the invention] [Industrial application field].

The present invention relates to a signal generation system in a digital signal processing system, and more particularly to a signal generation system suitable for a system configured to distribute various types of high-speed clocks from a clock generation circuit to other circuits.

[Prior Art] - Fig. 3 is a block diagram showing the state of clock distribution in a conventional digital signal processing system. In the figure, 31 is a board having a clock generation circuit 31a;
5 is a board having digital signal processing circuits 32a to 35a. The clock generation circuit 31a generates all clocks having n types of frequencies necessary for this digital signal processing circuit, and locks are distributed as necessary to the digital signal processing circuits 32a to 35a in each board 32 to 35.

[Problems to be Solved by the Invention] The clock distribution method in the digital signal processing system in the conventional device as described above involves a large number of clock transmission paths. When a clock is distributed to a large number of circuits, clock delays and distortions may occur due to imperfections in the transmission path, and when high-speed clock transmission paths are placed adjacent to each other.

There has been a problem in that electromagnetic coupling and capacitive coupling between transmission lines adversely affect each other.

Therefore, these measures must be taken for all clock transmission paths, and it is difficult to accurately distribute all the clocks generated by the clock generation circuit to other circuits.

This invention was made in order to solve this problem, and aims to reduce distortion, delay, and negative effects between each transmission line by transmitting the minimum necessary types of clocks. The purpose is to provide a generation system.

[Means for Solving the Problems] In order to achieve the above object, the signal generation system of the present invention generates a clock of the highest frequency of the system from a clock generation circuit, and a clock of n types (n types) having different frequencies from each other. is an integer greater than or equal to 2), and the system clock frequency is divided by the least common multiple of the frequency of the system clock. It is.

[Operation] According to the configuration of the present invention, the clock generation circuit generates two types of clocks and distributes them to other circuits, so that the receiving circuit uses only the two types of clocks. It can be generated from In other words, high-speed lock transmission is performed using only one type of clock with the highest frequency in the system, which is better than conventional methods by preventing clock delays and distortions that were problems in the past in the transmission path. These negative effects can be reduced.

[Example] Hereinafter, the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing a clock distribution configuration of a digital signal processing system according to an embodiment of the present invention.

In the figure, l is a system clock generation circuit 1a that generates the highest frequency clock (system clock) used in the digital signal processing system in this embodiment.
and a reference clock generation circuit 1b that generates a clock (reference clock) obtained by dividing the system clock by the least common multiple of the clock used in this digital signal processing system. 2 is a board having a digital signal processing circuit 2b whose clock frequencies are 48 MH2, 24 MH2, 6 MH2, and 3 MH2, and a counter circuit 2a which generates each of the clocks from the system clock and reference clock from the board 1. . 3 uses clock frequencies of 24MHz and 16MHz.

This board has digital signal processing circuits 3b of 4 MHz, 2 MHz, and I MHz, and a counter circuit 3a that generates each of the clocks from the system clock and reference clock from the board 1. n is the frequency of the clock used: 48 MHz, 24 MHz, 6
This board has a digital processing circuit nb of MHz, and a counter circuit na that generates each of the clocks from the system clock and reference clock from the board 1.

Next, in the above configuration, in the system clock generation counter circuit 1a of the board 1, the highest frequency of the clock used in this system is 48M11. generates a clock. The source oscillation is TTL () - transistor by Vco.
transistor logic circuit) level. The reference clock generation circuit 1b generates a lMHz clock obtained by dividing the frequency of 48 MH2 by the least common multiple of the clock used in this digital signal processing system. The two types of clocks were transmitted to the boards 2 to n at the ECL (emitter-coupled logic circuit) level, and the transmission path was a two-wire system (twisted pair wire) with a common bus configuration.

The counter circuit 2a on the board 2 receives a 48 MHZ clock and an IMIZ clock synchronized therewith from the board 1, and uses the counter IC as a digital signal processing circuit 2b.
Hz.

A clock with a frequency of 3M1f□ is generated.

Similarly, the counter circuit 3a on the board 3 is used in the digital signal processing circuit 3b.
.

A clock with a frequency of IMH□ is generated, and the circuit na on the board n is used as a digital signal processing circuit nb.
MHz, 24 MH□, and 6 MH frequencies are generated, respectively.

The timing of these clocks is shown in FIG. FIG. 2 is a timing chart showing each clock and standard clock of the digital signal processing system in this embodiment.

In the above embodiment, the required locking frequencies of the system are 48 MHz, 24 MHz, 16 MHz.
z.

12 Heron H2, 6 Heron H2, 4 Heron H2, 3 Heron H2, 2 Heron H2
, I MHz, while the frequency of the clock transmitted from the clock generation circuit is 48 MH, and I MH, ! There are two types, and it is only necessary to take countermeasures against the clock distortion and delay that conventionally occur in this transmission path, thereby making it possible to distribute clocks more stably than in the past.

[Effects of the Invention] As explained above, the present invention reduces the number of transmission paths by distributing only two types of clocks, the system clock and the reference clock, when distributing clocks from the clock generation circuit to other circuits. It is possible to reduce clock distortion, clock delay, and adverse effects between transmission lines due to a reduction in the number of clocks.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a clock distribution configuration of a digital signal processing system according to an embodiment of the present invention, and FIG.
The figure is a timing chart showing each clock and standard clock of the digital signal processing system in this embodiment, and FIG. 3 is a block diagram showing the state of clock distribution in the conventional digital signal processing system. In the figure. 1.2,3,4. ......n: Board 1a system clock generation circuit lb=reference clock generation circuit 2a, 3a...na: Circuit consisting of a counter that generates a clock 2b, 3b-----・n b: Digital signal processing circuit agent Patent attorney 1) Haru Kitatake

Claims (1)

[Claims] A clock with the highest frequency of the system is generated from a clock generation circuit, and a clock with a frequency obtained by dividing this clock by the least common multiple of the frequencies of n types of system clocks having mutually different frequencies (n is an integer of 2 or more). A signal generation system characterized in that the receiving side circuit generates n types of clocks to be used from the two types of clocks.