JP2003115538A - Semiconductor device and adjustment method for clock delay of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To distribute a clock signal without differential delays with reference to a synchronous element inside each block when hierarchy is designed in a large-scale high-speed LSI. SOLUTION: Frequency information on the clock signal to be input to a clock encoder 1 in the outermost hierarchy of the hierarchy-designed LSI and delay information on a part up to each block are transmitted to a clock decoder 3 installed in each block, and the clock signal is distributed without difference delays to all synchronous elements inside each block.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of distributing a clock signal to each synchronous element without delay difference in order to operate a large-scale synchronous circuit at high speed in a semiconductor device.

[0002]

2. Description of the Related Art In recent years, the miniaturization of semiconductor processes has advanced,
The scale of circuits mounted in semiconductor devices is increasing,
When logic synthesis and automatic placement and routing are performed on all circuits in a semiconductor device, it becomes difficult to process all circuit information at once by a computer. Also, in the fine process, the capacitance value and resistance value of the wiring change greatly depending on the length of the wiring connecting each transistor, and the influence on the operating speed of the transistor becomes large. Is difficult to do. Due to these reasons, in the design of a semiconductor device, a circuit is divided into blocks for each function, and the blocks are connected to each other to form a semiconductor device as one chip.

Most of the large-scale semiconductor devices at present are designed on the basis of a synchronous design, and a clock signal is received from the outside in order to synchronize the inside of the semiconductor device, and an internal synchronizing element is synchronized with the clock signal. It has a method of operating. For this purpose, the clock signal received from the outside must be wired so as to reach all the synchronous elements inside at almost the same time. In the development of a semiconductor device, if the difference in the delay value until the clock signal reaches each synchronous element is large, the semiconductor device is adversely affected such as immobility or malfunction. Therefore, in order to eliminate this adverse effect, a method called "clock tree method" is widely and generally used.

As a method of designing a "clock tree system" synchronous circuit, for example, as a design method for synchronizing the inside of a block, there is a known example "Exact Zero Skew" (Proceeding IEE International Conference on Computer). Aided Design: Proc. IEEE Int. Conference onComp
uter-Aided Design, pp336-339, 1991).

However, the clock tree method is an effective means when it is used inside individual blocks, but if it is attempted to use the clock tree method from the highest hierarchy connecting the individual blocks, it will be used for the clock tree. Since the arrangement position of the clock buffer to be used is largely restricted by each block, a sufficient effect cannot be obtained.

[0006]

Therefore, according to the above-mentioned conventional technique, after the layout design is once performed for the inside of each block using the clock tree method, the individual blocks are arranged in the highest hierarchy. Connect the clock,
Again, inside the individual blocks, while adjusting the clock delay while replacing the cells on the clock path and adjusting the wiring length, the clock is synchronized to the synchronous elements of the entire chip without any delay difference. Was trying to spread. This method takes a very long time to adjust the delay of one chip.

The present invention solves the above-mentioned conventional problems. In a large-scale synchronous circuit in a semiconductor device, when a hierarchical design is performed, each block from the highest hierarchy is
An object of the present invention is to provide a method of supplying a clock without a delay difference without using the clock tree method.

[0008]

In order to achieve this object, a clock distribution method of the present invention comprises a clock encoder at the highest hierarchy and a clock decoder for each block, and a clock signal inputted from the outside. Is converted into frequency information by an encoder of the highest hierarchy and transmitted to each block, and in each block, the received frequency information is reproduced into a clock signal by a decoder and used as a clock signal in the block.

However, if this is left as it is, the wiring length from the decoder to the encoder differs for each block, and clocks cannot be supplied to each block at the same time. Therefore, a step of calculating the delay amount for each clock is provided.

Further, the encoder and the decoder each have a frequency sufficiently higher than the clock supplied from the outside,
Since a clock signal synchronized between the encoder and the decoder is required, each encoder and decoder has a step of synchronizing the oscillation circuit with the oscillation circuit.

[0011]

DETAILED DESCRIPTION OF THE INVENTION Embodiments will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, 1 is a clock encoder,
2 is a transmission line, 3 is a clock decoder, and CK is a clock signal.

FIG. 2 is a flow chart showing the clock transmission method of the present invention. Reference numeral 10 is a decoder clock checking step in each block, 11 is a clock information transmitting step, 12 is a clock decoder internal clock generating step,
13 is a delay value calculation step, and 14 is a synchronous clock generation step.

First, the decoder clock checking step 10 of each block in FIG. 2 will be described with reference to FIG.

A new clock having 100 cycles as one cycle is generated by an oscillator (not shown) in the clock encoder 1 and sent to the transmission line 2. Next, the clock that reaches the clock decoder 3 from the transmission line 2 is
Calculates and holds the number of cycles with the internal oscillator.

Next, the clock information transmitting step 11 of FIG. 2 will be described with reference to FIG.

External clock signal CK input from the outside
Is received by the clock encoder 1, the number of cycles of one cycle of the external clock signal CK is set by the oscillator inside the clock encoder 1, and the counted value is sent to the transmission line 2.

Next, the clock decoder internal clock generation step 12 of FIG. 2 will be described with reference to FIG.

The clock decoder 3 uses the value obtained from the transmission line 2 to check the decoder clock for each block in FIG.
A value obtained by multiplying the value calculated by 0 by 100 is calculated, and the clock generated by this value is generated inside the clock decoder 3 using an internal oscillator (not shown).

Next, the delay value calculation step 13 of FIG. 2 will be described with reference to FIG.

The clock decoder 3 sends a reply request signal to the transmission line 2. Transmission line 2 to clock encoder 1
When the reply request signal arrives at, the clock encoder 1 immediately sends the reply signal to the transmission line 2. The clock decoder 3 holds a half value of the number of clocks generated by the oscillator in the clock decoder 3 after outputting the reply request signal until receiving the reply signal as a delay due to the transmission line 2.

Next, the synchronous clock generating step 14 of FIG. 2 will be described with reference to FIG.

The clock decoder 3 uses the delay value calculation step 1 shown in FIG. 2 for the clock generated internally for the clock decoder 3 in the clock decoder internal clock generation step 12 shown in FIG.
The clock advanced by the value calculated in 3 is generated inside the block as the block internal clock.

These steps 10 to 10 are carried out during the operation of the semiconductor device.
Even if a generally unstable oscillator that can be configured in the semiconductor device is used in the clock encoder 1 and the clock decoder 3 by repeating step 14 in sequence, sufficient synchronization can be achieved.

[0025]

As described above, according to the present invention, when a semiconductor device has a clock encoder and a clock decoder and a process of synchronizing them is used, a large-scale high-speed synchronous circuit of the semiconductor device is hierarchically designed. In addition, the external clock can be transmitted to all the synchronous elements without delay difference.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a flowchart showing a flow of clock information transmission according to the embodiment of the present invention.

[Explanation of symbols]

1 clock encoder 2 transmission lines 3 clock decoder 10 Decoder clock check process for each block 11 Clock information transmission process 12 Clock decoder Internal clock generation process 13 Delay value calculation process 14 Synchronous clock generation process

Claims (2)

[Claims] 1. A semiconductor device having a clock encoder and a transmission path at a top level and a clock decoder in a child block, whereby the frequency of a clock can be signaled and transmitted to the child block. 2. In the above semiconductor device, a step of synchronizing a clock used inside the clock encoder of the top level and a clock decoder of the child block, and a delay value from the clock encoder of the top level to the clock decoder of the child block are calculated. A method for adjusting a clock delay including the step of: