JP2007193658A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can supply a more stable clock signal by not affecting output of an external output clock by power fluctuation by operation of an internal block. <P>SOLUTION: A semiconductor device 100 which performs giving and receiving of data between an external circuit 118 using a clock output from an oscillation source 102 as a standard is characterized by comprising; a clock distribution means 112 to distribute a clock output from an oscillation source to an internal circuit 114 provided in the semiconductor device; a clock supply means 104 which supplies a clock to an external circuit; a phase difference detection means 106 which detects a phase difference between the clock supplied to the external circuit and the clock at an end of the clock distribution means; and a clock delay adjustment means 110 to adjust the clock delay output from the clock supply means based on data of phase difference detected by the phase difference detection means. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a function of adjusting a delay value of a clock.

  Semiconductor devices such as LSIs (large scale integrated) have been miniaturized, and accordingly, a system that has been configured with a plurality of LSIs in the past has been configured by putting the functions of the plurality of LSIs together into a single LSI. It has come to be. Further, with the miniaturization of LSIs, the operation speed at which LSIs can be processed has been improved, and higher speed operations have been required in order to increase the processing functions of LSIs as compared with the prior art.

  At the LSI design stage, an external oscillator or an internal or external PLL (Phase Locked Loop) output is basically used because of the ease of design as an LSI and the ease of verification such as adjustment of clock skew. Synchronous circuit design using a clock tree as a clock has become the mainstream. When executing this circuit design, it is necessary to synchronize clocks in order to exchange information between the internal block and the external block. As a method of synchronizing the clocks, a method of handling the clock supplied to the external block as one of the clock trees (hereinafter referred to as the first method), or a feedback of the clock at the end of the clock tree, the internal block There is a method (hereinafter referred to as a second method) for matching the clock of the above to the external output clock.

  However, since LSIs have been increased in scale and high-speed operation has been required, the transfer of information with external blocks has also been speeded up, so that the setup time and hold time for the clock generated during information transfer can be secured. It has become difficult.

  Also, for example, instead of using a clock provided by an external block as in DDR (Double Data Rate), the external block has a PLL or DLL (Delay-Locked Loop) and operates based on this function. Some are doing it. When the supplied clock has jitter, the reference clock serving as a reference signal is not stable in terms of PLL and DLL, which may cause malfunction of the external block. Even when malfunction does not occur, a clock having jitter adversely affects AC (Alternating Current) timing such as setup and hold time in information exchange between each other.

  On the other hand, with regard to the clock of the supply source to the external block, the arrival time from the start point of the clock tree to the internal flip-flop is equal to the oscillation source frequency or the oscillation frequency because the LSI has been increased in scale and speed. The situation has exceeded.

  As a semiconductor device that automatically adjusts the supply of the clock signal to the optimum timing, the system clock SC is delayed by a buffer row BR composed of a plurality of buffers, and several buffer outputs are connected to a selector composed of a flip-flop or the like. A clock delay adjustment method for forming clock paths having different delay amounts is disclosed in Patent Document 1. The configuration and operation of the synchronization circuit for adjusting the clock delay of the semiconductor device disclosed in Patent Document 1 will be described below with reference to the drawings.

  FIG. 5 is a schematic diagram for briefly explaining the configuration of the synchronization circuit 10 for adjusting the clock delay of the semiconductor device disclosed in Patent Document 1, and FIG. 6 shows the clock delay in the synchronization circuit shown in FIG. It is a timing chart for demonstrating operation | movement. 5 and 6, the number of buffers constituting the synchronization circuit will be described in a seven-stage configuration, but this is an example for simplifying the description of the operation of the synchronization circuit. In the following description, the clock absolute delay value and the clock cycle are the same, but this is also an example for simplification. For example, when the absolute delay value is larger than the clock period, it may affect the next clock.

  As shown in FIG. 5, the synchronizing circuit 10 is configured to have the same frequency as the frequency of the transmission source with a seven-stage buffer. The synchronization circuit 10 functions as a memory area that is temporarily used for data processing, so that seven buffers 11 to 17 are inserted to satisfy clock simultaneity from the configuration of the synchronization circuit 10. It is configured to be connected to a flip-flop (hereinafter abbreviated as F / F) 18 which is one model of an operation module in the LSI. FIG. 6 shows a timing chart under this assumption. The “start point” in FIG. 6 corresponds to the clock waveform of the transmission source, and the waveforms corresponding to the outputs of the buffers 11 to 17 shown in FIG. 5 correspond to “delay 1” to “end point” shown in FIG. .

  The clock CK1S generated at the “start point” shown in FIG. 6 reaches the “end point” clock CK1E shown in FIG. 6 with delay while passing through the buffers 11-17. The clock CK1E that has reached the “end point” drives each F / F 18 shown in FIG. Such driving gives fluctuations to the power supply. This variation varies in magnitude and time depending on the number of elements driven at that time, variations in clock arrival time at each “end point”, and ringing depending on the power source impedance. A model of the difference between the magnitudes of the fluctuations and the time is indicated by a period T60 in FIG.

  In the period T60 shown in FIG. 6, the buffers 11, 12, and 13 (delay 1, delay 2, and delay 3 shown in FIG. 6) are switching, the transistor is in the operating point region, and the power supply You will be subject to fluctuations. The clock subjected to the power supply fluctuation is with respect to the clock generated in the clock CK2S shown in FIG. 6, and the influence of the fluctuation appears in the form of jitter 61 in the clock CK2E shown in FIG. In the worst case, variations in the clock arrival time to each element that becomes a hazard and the impedance of the power supply are fixed by design and are commonly given to all clocks. Will be different. Due to this jitter 61, the frequency sensed by the F / F 18 in FIG. 5 is 1 / (T ± j) (Hz, where T (s) is the generation period of the clock source and j (s) is the magnitude of the jitter. )

  According to the first conventional method, this clock is supplied to the external block, and the required operating frequency for the external block is 1 / (T−j) (Hz), which is a stricter requirement standard. Further, when the operation is performed using the PLL or DLL based on the clock supplied to the external block, the clock may be out of the lock range and cause a malfunction. Even when the clock is within the lock range and no malfunction occurs, it becomes a factor of reducing AC timing margins such as setup time and hold time in information exchange between the internal block and the external block.

In addition, the speed has been increased and the number of parts has been reduced. In addition, the interface for differential signals has increased as in DDR, so the clock used as a reference for internal and external blocks can also be generated by PLL. The number of built-in cases has increased. In this case, when the clock at the end of the clock tree is used for feedback to the PLL to reduce the circuit scale, the feedback signal surely has jitter due to external noise as described with reference to FIGS. As a result, the system is not stable, and jitter exceeding the inherent capability of the PLL is added to the output clock. Therefore, feedback to the PLL of the oscillation source is created from the output of the PLL, and it is necessary to make a PLL or DLL separately at the subsequent stage. This is the second conventional method.
JP 2000-235517 A

  According to the second conventional method described above, if the output of the oscillation source is used as it is for output to the external block, the output clock to the outside can be reduced only to the jitter of the oscillation source. However, when the PLL or DLL is separately provided, the jitter to the internal clock is generated in the feedback signal as described with reference to FIGS. 5 and 6. Therefore, the system is not stable, and the jitter exceeding the original ability is generated. Will have.

  In the second conventional method, the semiconductor device measures a delay value in a steady state using a DLL, and uses the delay value as a fixed value. The jitter that occurs is eliminated. However, in consideration of the clock of the oscillation source and the clock at the end of the clock tree input to the DLL, in FIG. 6, the clock that becomes the reference of the oscillation source corresponds to the “start point”, and the clock at the end of the clock tree is “end point”. Become. For example, when the reference clock is “CK3S” shown in FIG. 6, the clock at the end of the clock tree fed back as a comparison reference is “CK2E”. As shown in FIG. 6, “CK2E” corresponds to “CK2S” in terms of a reference clock. That is, since the oscillation source itself has a jitter component, a delay value including the jitter of the oscillation source is measured. In other words, the output of the external output clock is affected by fluctuations in the power supply due to the operation of the internal block, and a clock including jitter is output, resulting in variations in the characteristics of the manufacturing process of the semiconductor device.

  Therefore, the present invention has been made in view of the above-mentioned problems of conventional semiconductor devices, and the object of the present invention is not to affect the output of the external output clock even if the power supply fluctuates due to the operation of the internal block. Thus, a new and improved semiconductor device capable of supplying a more stable clock signal is provided.

  In order to solve the above-described problem, according to an embodiment of the present invention, in a semiconductor device that performs data exchange with an external circuit based on a clock output from an oscillation source, the clock output from the oscillation source is Clock distribution means for distributing to an internal circuit provided in a semiconductor device, clock supply means for supplying a clock to an external circuit, and a phase difference for detecting a phase difference between the clock supplied to the external circuit and the clock at the end of the clock distribution means There is provided a semiconductor device comprising: a detecting unit; and a clock delay adjusting unit that adjusts a delay of a clock output from the clock supply unit based on phase difference data detected by the phase difference detecting unit. The

  With such a configuration, the output clock to the external circuit such as the external function block is separated from the power supply fluctuation due to the operation of the internal circuit such as the internal block, so that it is possible to output with reduced jitter. Therefore, by outputting a jitter-reduced clock, the transmission / reception margin with the external function block can be expanded to reduce the required specifications for the external function block, and the AC timing characteristics for transmission / reception with the external function block can also be reduced. It can be mitigated.

  Further, by making the delay values of the two clocks whose phases are compared the same, the inherent jitter of the oscillation source can be canceled out and accurate phase alignment can be achieved, so that variations in manufacturing process characteristics can be absorbed. That is, the clock delay adjusting means executes a setting sequence for adjusting the delay of the clock based on the phase difference data by the phase difference detecting means, so that the difference in process characteristics generated at the route between the output clock and the clock tree placement and routing And delay values caused by power supply differences are absorbed.

  At this time, in the above embodiment, the internal circuit includes a flip-flop that interfaces with the external circuit, and the input node from the terminal of the clock distribution means to the phase difference detection means inputs the input point of the clock of the flip-flop. It may be a node.

  With this configuration, for example, when a logical operation is performed between the output of one flip-flop and the input of another flip-flop that receives the output of the flip-flop, and a delay value is added. The clock to other flip-flops may have such a delay value as compared to the clock of one flip-flop. For this reason, when generating the clock distribution means, the condition that the input node is the clock input point of the flip-flop that interfaces with the external circuit of the internal circuit from the terminal of the clock distribution means to the phase difference detection means. When the above is established, the generation of the clock distribution means is completed. In other words, since the time is not the same at all the ends of the clock distribution means, the above-described clock delay adjustment can be executed more accurately.

  Further, at this time, in the above embodiment, when adjusting the clock delay by the clock delay adjusting means, the portions corresponding to the data input terminal and output terminal of the flip-flop provided in the internal circuit are static. Also good.

  By adopting such a configuration, the setting sequence at the initial stage is executed in a state close to the non-operating state, so that the delay clock does not affect the internal block, and the configuration of the delay setting is simplified. Design becomes possible.

  As described above, according to the present invention, since it is possible to separate the clock supplied to the outside and the power supply voltage of the internal block, there is little jitter without being affected by the fluctuation of the power supply voltage by the internal block. A clock can be supplied, and it is possible to accurately set the delay of the clock to be transmitted to the outside as to the jitter of the oscillation source. In addition, by adjusting the delay, it is possible to absorb the difference in delay caused by the process due to the difference in the placement and routing route. In terms of design, the design specifications can be relaxed, and in terms of production, the yield can be improved. It becomes.

  Exemplary embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In the present specification and drawings, components having substantially the same functional configuration are denoted by the same reference numerals, and redundant description is omitted.

  First, the configuration of the semiconductor device according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit block diagram showing an outline of a basic configuration of a semiconductor device according to the present embodiment.

  As shown in FIG. 1, the semiconductor device 100 in this embodiment includes an oscillation source 102, an output terminal 104, a phase difference detection unit 106, a control unit 108, a delay adjustment unit 110, a clock tree 112, an internal block 114, and an input block. An output terminal 116 is provided.

  The oscillation source 102 is a clock generation means for generating a basic clock for transferring data between the semiconductor device 100 of the present embodiment and the external function block 118 which is an external circuit such as a memory. As the oscillation source 102, for example, a crystal oscillator, a ceramic oscillator, or a PLL circuit is used. Here, as for the PLL circuit, it may be either built in the semiconductor device 100 or external.

  The output terminal 104 is a clock supply unit that supplies a clock generated by the oscillation source 102 to the external function block 118. External function block 118 and semiconductor device 100 of the present embodiment are assumed to exchange data with reference to this clock. Further, as a method for supplying the clock from the output terminal 104, only a normal phase clock, only a reverse phase clock, or a differential supply that supplies a pair of a normal phase and a reverse phase may be used. The peak value of the clock may be either a full swing or not a full swing.

  The phase difference detection unit 106 is a clock phase difference detection unit that detects a clock phase difference between a clock supplied to the outside and a terminal (corresponding to an “end point” shown in FIG. 5) of a clock tree 112 described later. The detection value by the detection unit 106 may be composed of a plurality of bits such as a counter, or may be composed of 1 bit such as “early / late”. . The clock from the clock tree 112 and the clock from the oscillation source 102 input to the phase difference detection unit 106 may be divided as necessary. The frequency dividing stage itself may be provided in the phase difference detection unit 106 or may be arranged outside the phase difference detecting unit 106.

  The control unit 108 controls the delay adjustment unit 110 described later based on the data detected from the phase difference detection unit 106. The control unit 108 may be a control that is executed in hardware by providing a dedicated control device, or may be a control that is executed in software via the CPU. The control unit 108 includes at least a function for setting a delay value in a delay adjustment unit 110 described later and a function for invalidating a feedback function from the phase difference detection unit 106.

  The delay adjustment unit 110 is a clock delay adjustment unit that determines a delay value of the clock output from the oscillation source 102 in accordance with the control of the control unit 108, and is configured by, for example, a DLL delay element group. Yes. It is assumed that the power source of the blocks constituting the delay adjustment unit 110 is different from the internal block 114 described later at least inside the semiconductor device 100 and sufficiently measures for noise are taken.

  The clock tree 112 is a clock distribution unit that distributes a basic clock for operating the internal block 114 of the semiconductor device 100 of the present embodiment from the oscillation source 102 to the internal block 114 described later. In the clock tree 112, the layout and the number of stages of the latches provided in the clock tree 112 are adjusted at the time of layout so as to satisfy clock simultaneity. One of the outputs from the end of the clock tree 112 is an input to the phase difference detection unit 106. At this time, the input node preferably has a clock input point of a flip-flop (not shown) that interfaces with the external function block 118 of the internal block 114 as an input node, thereby enabling more accurate delay adjustment. It becomes.

  When the clock tree 112 is thus extended, a logical operation is performed between the output of one flip-flop and the input of another flip-flop that receives the output of the flip-flop, and a delay value t is obtained. At this time, it is actually necessary to secure a setup / hold margin, but the clock to the other flip-flop may have a delay value of absolute time t as compared with the clock of one flip-flop. There will be no. For this reason, when generating the clock tree 112, the clock input point of the flip-flop that interfaces with the external function block 118 of the internal block 114 is input to the node that is input from the end of the clock tree 112 to the phase difference detection unit 106. The generation of the clock tree 112 is completed when a condition (setting / holding margin is ensured) that establishes a node is established. That is, since it is not the same time at all the ends of the clock tree 112, it is desirable to detect the phase difference with the clock of the flip-flop that actually takes the interface.

  The internal block 114 is an internal circuit that realizes the function of the semiconductor device 100 according to the present embodiment, and has at least one functional block to which a clock is supplied from the clock tree 112. Such functional blocks include, for example, a CPU, a memory, and logic for a specific application.

  The input / output terminal 116 is an input / output (I / O) buffer for transferring data between the semiconductor device 100 of the present embodiment and an external function block 118 described later. The input / output terminal 116 is, for example, a data bus or an address line, and there is one or more information exchange ports.

  The external function block 118 is an external circuit such as a memory that exchanges information through the input / output terminal 116 with reference to the clock supplied from the semiconductor device 100 and the output terminal 104 of the present embodiment.

  Next, the operation of the semiconductor device 100 having the above-described configuration and the control sequence for setting the clock delay value for adjusting the clock delay by the delay adjusting unit 110 will be described.

  First, assuming that the delay adjustment value in the phase adjustment unit 110 is 0 in the initial state, the clock output by the clock tree 112 has a delay, so that the phase difference detection unit 106 is connected from the output terminal 104 to the external function block 118. It is determined that there is a phase difference between an external clock including the above and the internal clock supplied to the internal block 114.

  The control unit 108 acquires information such as data detected from the phase difference detection unit 106 directly by hardware, or acquires information such as data indirectly by software, so that the delay adjustment unit 110 Change the delay setting value in the direction of further delay. In this embodiment, since the initial delay value is set to 0, only the direction in which the delay is added can be changed. At this time, the delay value delayed by one setting may be one delay element or a plurality of delay values, and the phase difference detection unit 106 has means for detecting an absolute value. If it is a detector, it may be the value of the detected absolute value.

  In the determination of the phase difference detection unit 106 described above, the sign of the phase difference between both the clock input to the outside input to the phase difference detection unit 106 and the clock output from the terminal of the clock tree 112 is reversed. The point is a delay setting value in which two input clocks are in phase. Here, although the initial delay value in the phase difference detection unit 106 is set to 0, a method of reducing the delay value when setting the clock delay value with the initial delay value as the maximum delay value may be used. Shall. For example, when the phase of the output clock supplied to the outside and the phase of the internal clock are to be the same, the control unit 108 uses the detection value obtained by reversing the “advance / delay” that can be read from the phase difference detection unit 106 to control the delay adjustment unit 108. A clock delay value is set to 110. Further, when it is desired to shift the phase of the output clock and the internal clock, the clock adjustment may be performed by the delay adjustment unit 110 based on a set value obtained by adding a certain value. It is assumed that the second “advance / delay” is detected, and the clock adjustment setting of the delay adjustment unit 110 may be determined from the calculation result.

  The setting sequence for determining the clock adjustment setting value of the delay adjustment unit 110 is performed once in the setting sequence at the initial stage such as when the power is turned on. Suppose that the setting value of the delay adjustment unit 110 is not updated. By executing such a design sequence in the initial stage, it is possible to absorb a delay value generated due to a difference in process characteristics or a difference in power supply generated between the output clock and the clock tree placement and routing route.

  In other words, when the phase of the output clock and the end of the clock tree are matched without executing such a setting sequence as in the prior art, only the case of a specific voltage under a specific process condition matches, and the delay stage is used. The output clock and the clock tree inevitably differ in the number of buffer stages due to the structure. For this reason, when the setting sequence is not executed, a difference occurs in the delay value between the output clock and the clock tree due to a difference in process or voltage. On the other hand, in the present embodiment, by executing the above setting sequence, it is possible to absorb a delay value generated due to a difference in process characteristics or a difference in power supply generated between the output clock and the route of the placement and routing of the clock tree.

  Further, in the above sequence, the internal block 114 preferably has static portions corresponding to the data terminal and output terminal of the flip-flop. As described above, since the delay clock does not affect the internal block by performing the initial setting sequence in a state close to the non-operating state, the delay setting can be designed with a simplified configuration.

  Next, in the semiconductor device 100 of the present embodiment, the clock supply operation timing will be described with reference to the drawings while comparing with the clock supply operation timing in the first conventional method described above. FIG. 2A shows a timing chart of clock supply by the above-described conventional first method, and FIG. 2B shows a timing chart of clock supply by the semiconductor device 100 according to the first embodiment of the present invention. Both figures show a timing chart of the external clock, return data, and internal clock in order from the top. In both figures, the jitter component due to factors other than those described in FIGS. 5 and 6 (for example, the jitter of the PLL itself due to the dead zone of the Phase Detector that the PLL has) is the first method and Since this applies to both methods of clock supply according to this embodiment, it is ignored here.

  The “external clock” shown in FIG. 2A is a clock that is output with the same delay value as the end of the clock tree by the first conventional method. Is output with jitter. The “return data” shown in FIG. 2A is generated using the “external clock” or “external clock” from the external function block 118 shown in FIG. 1 toward the LSI that is the semiconductor device 100 of the present embodiment. For example, in the case of the external function block 118, it corresponds to memory read data or the like. In the first method shown in FIG. 2A, since the “external clock” has jitter, the “return data” generated based on the external clock also has jitter. The “internal clock” is the same as the internal clock of the semiconductor device 100 of the present embodiment. In FIG. 2A, the “internal clock” is the source of the “external clock”, and is also a clock that receives “return data”.

  The “external clock” shown in FIG. 2B is a clock that is output so as not to be affected by the supply of the clock in the semiconductor device 100 of the present embodiment in consideration of the influence from the internal block 114. Therefore, the output is performed without jitter due to the internal operation of the semiconductor device 100. The “return data” shown in FIG. 2B is a clock generated using the “external clock” or “external clock” from the external function block 118 shown in FIG. 1 toward the semiconductor device 100 of the present embodiment. For example, the external function block 118 corresponds to the read data of the memory. In FIG. 2B, in the sense that the “external clock” depends on the operation of the internal block 114, it does not have jitter. Therefore, the “return data” generated based on the external clock does not have jitter. . The “internal clock” shown in FIG. 2B is an internal clock of the semiconductor device 100 of the present embodiment, and is also a clock that receives “return data”. Such an “internal clock” is affected by the operation of the internal block 114 and has jitter as in the first conventional method.

  In FIG. 2A and FIG. 2B, the codes Tcks1 and Tcks2 correspond to the setup time at the time of reception, and the codes Tckh1 and Tckh2 correspond to the hold time at the time of reception. As described with reference to FIGS. 5 and 6, in FIG. 2, jitter affects the operation of the internal clock CKI (n−1) in the external clock CKO (n) and the internal clock CKI (n). Therefore, the period of each clock edge depends on the amount of jitter. In the reception of “return data”, the data generated by the external clock CKO (n−1) is received by the internal clock CKI (n). According to the semiconductor device 100 of the embodiment, the reception margin can be increased by removing the jitter from the external clock and taking the interface. In comparison between FIG. 2 (a) and FIG. 2 (b), the setup times Tcks1 and Tcks2 at the time of reception are larger in the setup time at the time of reception in the present embodiment. That is, a relationship of Tcks2> Tcks1 is established.

  In the description of the operation shown in FIG. 2, all the operation triggers are set to the rising edge of the clock. However, the same effect can be obtained even if the operation trigger is set to the falling edge of the clock. In FIG. 2, the case where the semiconductor device 100 of the present embodiment receives data or the like has been described. However, transmission information includes jitter as in the conventional case, but transmission clock jitter also occurs during transmission. The AC timing margin for this jitter can be expanded. Further, in the setting of the delay value in the phase difference detection unit 106 shown in FIG. 1, the external output clock and the internal clock have been adjusted so as to have the same phase. Also, it may be adjusted to an intermediate position. In addition, the sign of the result of the phase comparison is used for the determination of the delay value adjustment, but in the determination of the delay value adjustment, an offset value is added, or it is executed by adjusting to a fixed value experimentally examined. It may be acceptable.

  Next, in the semiconductor device 100 of the present embodiment, the clock supply operation timing will be described with reference to the drawings while comparing with the clock supply operation timing in the second conventional method described above. FIG. 3 shows a timing chart of clock supply by the above-described second conventional method, and FIG. 4 shows a timing chart of clock supply by the semiconductor device 100 according to the first embodiment of the present invention. 3 shows a timing chart of the oscillation source clock, the output clock, the DLL output clock, and the end clock of the clock tree in order from the top. FIG. 4 shows the oscillation source clock, the output clock, and the clock in order from the top. The timing chart of the end clock of a tree is shown.

  As described above, according to the second conventional method, the clock generated from the oscillation source is output as it is and becomes an output clock to the outside. The clock generated by the oscillation source is further supplied to the clock tree via another PLL or DLL, and then distributed to the internal block. The input of the PLL or DLL becomes the output clock and the end clock of the clock tree. At this time, if the sequence control similar to the present invention is performed only when the DLL is used, it is possible to eliminate the jitter factor from the internal block generated through the power supply. However, in the description of the conventional first method, the jitter component of the oscillation source is ignored, but in the conventional second method, the oscillation source itself has jitter. Therefore, the influence of the jitter of the oscillation source 102 according to the second conventional method and the first embodiment of the present invention will be described below.

  In the second conventional method, the DLL connected to the subsequent stage of the oscillation source operates so as to detect the phase of the end clock of the clock tree and the oscillation source clock. When the phases are matched, as shown in FIG. 3, since the delay occurs in the clock tree, the end clock of the clock tree is delayed by one cycle or more, and the clock edge exists at the position of the cycle unit. FIG. 3 shows an example in which the phase of the DLL connected to the latter stage of the oscillation source is adjusted so that the phases are matched in one cycle.

  On the other hand, the clock of the oscillation source is directly output as the output clock to the outside. For this reason, the DLL connected in the subsequent stage detects the phase difference between the two clocks of the output clock and the end clock of the clock tree. At this time, when these two clocks compared by the DLL are numbered to the clocks at the oscillation source, the end clock of the clock tree is the clock CKE (n−1) with respect to the output clock CKO (n). ) Will be compared. In other words, the clock CKS (n) and the clock CKS (n−1) are compared with the oscillation source clock. Jitter also exists in the clock of the oscillation source, and the jitter values of the clock CKS (n) and the clock CKS (n−1) are not equal. Therefore, when the clock adjustment is performed by the second conventional method, an error depending on the jitter of the oscillation source occurs. In addition, since there is a high possibility that the control unit that changes the delay setting also uses the clock of the clock tree, it is necessary to separately provide a means for controlling the delay unit so as not to cause a hazard in the clock, and the LSI is complicated. It will become a structure.

  On the other hand, in the clock supply by the semiconductor device 100 of the present embodiment, the clock of the oscillation source 102 is output with jitter and is supplied to each flip-flop included in the internal block 114 after being delayed by the clock tree 112. The On the other hand, the output clock to the external function block 118 passes through the delay adjustment unit 110 and is set to have the same delay value as the end of the clock tree 112. The phase difference detection unit 106 detects the phase difference between these two clocks. The temporal relationship between the two input clocks detected by the phase difference detection unit 106 is that the clock tree termination clock CKC (n) corresponds to the output clock CKO (n) to the outside, and is converted to the clock of the oscillation source 102. Then, both are clocks CKS (n). Therefore, according to the method of this embodiment, the jitter of the oscillation source 102 is canceled out, and the phase difference between the output clock to the outside and the termination clock of the clock tree 112 can be accurately measured. Become.

  In addition, since the clock form of the oscillation source 102 is transmitted to the internal block 114 as it is after being delayed by the clock tree 112, changing the delay setting of the delay adjusting unit 110 has no effect. For the external function block 118, it is possible to avoid a malfunction by performing a reset operation, for example, considering that a setting sequence is initially performed even if a hazard occurs. Therefore, it is not necessary to make the change timing of the delay set value complicated. Of course, it is possible to make the change timing of the delay set value complex and prevent the occurrence of a hazard.

  As described above, according to the semiconductor device 100 of the present invention, the output clock from the oscillation source 102 to the external output block 118 is separated from the power supply fluctuation due to the operation of the internal block 114, and thus supplied to the external function block 118. The jitter of the output clock can be reduced. Further, by reducing the jitter, the transmission / reception margin with the external function block 118 is expanded, and the clock used to supply the jitter of the oscillation source 102 to the external function block 118 and the clock used in the internal block 114 are synchronized. Also, the transmission / reception margin can be expanded, the required specifications for the external function block 118 can be reduced, and the AC timing characteristics for transmission / reception with the external function block 118 can also be reduced. In addition, by adjusting the delay value of the delay adjustment unit 110, the delay value of the two clocks to be compared in phase can be made the same so that the inherent jitter of the oscillation source 102 can be canceled, and accurate phase alignment becomes possible. Variations in characteristics in the manufacturing process of semiconductor devices can be absorbed.

  As mentioned above, although preferred embodiment of this invention was described referring an accompanying drawing, it cannot be overemphasized that this invention is not limited to the example which concerns. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present invention. Understood.

  The present invention is a digital circuit designed using a clock tree, and can be applied to a semiconductor device that supplies a clock to the outside and exchanges information with an external function block based on the clock. The present invention can be applied to a configuration method and an adjustment method of a clock supplied to the device.

1 is a circuit block diagram showing an outline of a basic configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 3 is a timing chart for explaining operation timing of clock supply in the semiconductor device according to the first embodiment of the present invention, as compared with the conventional example, and (a) is a timing chart of clock supply by the conventional first method. (B) shows a timing chart of clock supply by the semiconductor device of the embodiment. It is a timing chart of clock supply by the conventional 2nd method. 3 is a timing chart of clock supply by the semiconductor device according to the first embodiment of the present invention. It is the schematic for demonstrating briefly the structure of the synchronizing circuit which adjusts the clock delay of the conventional semiconductor device. 6 is a timing chart for explaining an operation of clock delay in the synchronization circuit shown in FIG. 5.

Explanation of symbols

100 Semiconductor device 102 Oscillation source 104 Clock supply means (output terminal)
106 Phase difference detection means (phase difference detection unit)
108 Control Unit 110 Clock Delay Adjustment Unit (Delay Adjustment Unit)
112 Clock distribution means (clock tree)
114 Internal circuit (internal block)
116 Input / output terminal 118 External circuit (external function block)

Claims (3)

In a semiconductor device that executes data transfer with an external circuit based on a clock output from an oscillation source,
Clock distribution means for distributing a clock output from the oscillation source to an internal circuit included in the semiconductor device;
Clock supply means for supplying the clock to the external circuit;
Phase difference detection means for detecting a phase difference between a clock supplied to the external circuit and a clock at the end of the clock distribution means;
A clock delay adjusting means for adjusting a delay of a clock output from the clock supply means based on the data of the phase difference detected by the phase difference detecting means;
A semiconductor device comprising: The internal circuit includes a flip-flop that interfaces with the external circuit,
2. The semiconductor device according to claim 1, wherein the input node from the terminal of the clock distribution unit to the phase difference detection unit uses the input point of the clock of the flip-flop as an input node. 3. A portion corresponding to a data input terminal and an output terminal of the flip-flop provided in the internal circuit is static when adjusting the delay of the clock by the clock delay adjusting means. A semiconductor device according to 1.

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