JP5417688B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention generally relates to semiconductor integrated circuits, and more particularly to a semiconductor integrated circuit including a plurality of circuit blocks that are variably controlled in power supply voltage and operate at different power supply voltages.

  In recent years, systems for reproducing audio and moving images on portable devices have become widespread. In such a portable device, it is necessary to reduce the power consumption of the mounted semiconductor circuit in order to extend the life of the battery. In general, the power consumption of a semiconductor circuit is proportional to the operating frequency and proportional to the square of the power supply voltage. Therefore, set the clock to the minimum operating frequency required to execute the amount of processing required for applications such as audio and video playback, and the minimum power source required to achieve the required operating frequency. There is a method of supplying a voltage to each circuit block. This method is referred to as dynamic voltage and frequency scaling (hereinafter DVFS).

  Taking an application processor used in a mobile phone as an example, the highest frequency clock and highest voltage power are supplied to the processor core during video playback, and the processor core clock frequency and power supply voltage are reduced during audio playback. Reduce power. In addition to the processor core, the application processor chip is also equipped with a circuit for signal input / output with the outside of the chip, but the power supply voltage supplied to the input / output circuit is often fixed. In this case, two types of circuits, that is, a processor core whose power supply voltage is variably controlled and an input / output circuit whose power supply voltage is fixed, are mounted on one application processor chip.

  Hereinafter, data transfer between circuits in a chip on which a circuit operating with two different types of power supply voltages is mounted will be described. FIG. 12A is a diagram illustrating a chip on which circuits that operate with two different types of power supply voltages are mounted.

  The integrated circuit chip 10 includes a circuit block 11 and a circuit block 12. The circuit blocks 11 and 12 correspond to the two power domains PD1 and PD2 to which different power is supplied. The power domain means a group of circuits to which the same power is supplied. Here, the power supply voltage is variably controlled for the circuit block 11 of the domain PD1. The power supply voltage is fixed for the circuit block 12 of the domain PD2. The input clock of the flip-flop 15 in the circuit block 11 of the PD 1 is supplied from the PLL circuit 13 mounted on the integrated circuit chip 10. Specifically, the clock signal CK0 output from the PLL circuit 13 is frequency-divided by the 1 / m frequency divider 14 in the voltage-fixed PD2, and supplied to the flip-flop 15 in the PD1 domain as the clock signal CK1. The propagation time in this case is assumed to be tCK1. In many cases, m is an integer of 1 or more.

  Similarly, the input clock of the flip-flop 17 in the circuit block 12 of the PD 2 is also supplied from the PLL circuit 13. Specifically, the clock signal CK0 output from the PLL circuit 13 is frequency-divided by the 1 / n frequency divider 16 in the voltage-fixed PD2, and supplied to the flip-flop 17 in the PD2 domain as the clock signal CK2. The propagation time in this case is tCK2.

  For example, the circuit block 11 can be considered as a processor core and the circuit block 12 as a peripheral circuit. Since the clock frequency of the circuit block 12 is low, a 1 / n frequency divider 16 is provided as shown in FIG. 12A.

  FIG. 12B is a diagram illustrating changes in clock frequency, power supply voltage, and clock propagation time. When the division ratio m is switched between 1 and 4, and the division ratio n is fixed to 2, (a) clock frequency, (b) power supply voltage, and (c) clock propagation time are shown.

  Until time t1, since the processor core (circuit block 11) requires high processing capability, the clock of PD1 is operated at a high frequency with m = 1. Since a high frequency is not required for the clock of the peripheral circuit (circuit block 12), n = 2. During this period, the clock propagation time tCK1 (from the PLL circuit 13 to the flip-flop 15 of the PD1) and tCK2 (PLL) with the PD1 and PD2 set to predetermined power supply voltages (may be the same power supply voltage). It is assumed that the circuit 13 to the flip-flop 17 of the PD2 are designed to be equal. After time t1, the amount of processing required for the circuit block 11 is reduced, and the desired processing can be performed sufficiently even if the frequency of CK1 is low. At this time, since the clock cycle in the PD1 becomes long, it is possible to operate normally even if the power supply voltage of the PD1 is lowered. Therefore, the voltage of PD1 is lowered at time t2. Then, tCK1 increases and becomes longer than tCK2. When it is necessary to restore the frequency of CK1 at time t4, the power supply voltage of PD1 is restored to the original voltage at the previous time t3, and then m = 1 and the frequency of CK1 is restored. Thus, in the period from time t2 to time t3, tCK1 may be longer than tCK2.

  FIG. 13 is a diagram showing a system including a plurality of integrated circuit chips and a power supply IC chip. In FIG. 13, the same components as those in FIG. 12A are referred to by the same numerals, and a description thereof will be omitted. The system shown in FIG. 13 includes an integrated circuit chip 10 including a processor core and an input / output circuit, an integrated circuit chip 20 including a user interface circuit, and a power supply IC chip 30 that controls a power supply voltage.

  The integrated circuit chip 20 includes a circuit block 21. The circuit block 21 corresponds to one power domain PD9. The input clock of the flip-flop 25 in the circuit block 21 of the PD 9 is supplied from the PLL circuit 23 mounted on the integrated circuit chip 20. Specifically, the clock signal output from the PLL circuit 23 is divided by the 1 / n frequency divider 24 and supplied to the flip-flops 25 and 26 as the clock CK9. The propagation time in this case is assumed to be tCK9.

  The voltages VD1, VD2, and VD9 of the power domains PD1, PD2, and PD9 are supplied from the power IC chip 30, respectively. The power supply IC chip 30 is supplied with a voltage VD (for example, 4.5 V) from a battery or the like. The voltage of VD1 is controlled between 0.6V and 1.2V, for example, according to the value of the control signal vdd_set output from the voltage frequency control circuit 18 provided in the circuit block 12 of the integrated circuit chip 10. VD2 is fixed at 1.0V. The voltage frequency control circuit 18 calculates VD1 from the clock frequency required by the circuit of PD1 and sends it as vdd_set to the power supply IC chip 30 and controls the value of the frequency division ratio m of the 1 / m frequency divider 14.

  The integrated circuit chip 10 and the integrated circuit chip 20 receive the same clock signal CKIN as an input from the outside, control the phase using the respective PLL circuits 13 and 23, and then supply the clock to the flip-flops in the respective chips. . The phase control of the PLL circuit 13 and the PLL circuit 23 is performed, for example, so as to match the timing of the rising edge of the clock input to the flip-flop with the timing of the rising edge of CKIN input from the outside. The clock CK0 output from the PLL circuit 13 of the integrated circuit chip 10 is distributed to the flip-flops 15 and 28 of the processor core and the flip-flops 17 and 27 of the input / output circuit. As for the clock input to the flip-flop 15 of the processor core, CK0 is divided by 1 / m by the 1 / m divider 14, enters the PD2 domain, and reaches the flip-flops 15 and 28 as CK1. As for the clock input to the flip-flop 17 of the input / output circuit, CK0 is frequency-divided to 1 / n by the 1 / n frequency divider 16, and reaches the flip-flops 17 and 27 as CK2 only through the PD2 domain. The clock output from the PLL circuit 23 of the integrated circuit chip 20 is divided into 1 / n by the 1 / n divider 24 and input to the flip-flops 25 and 26 as CK9.

  The flow of data when the data after the processor core processing of the integrated circuit chip 10 is transferred to the integrated circuit chip 20 is as follows. Data is transmitted from the flip-flop 15 of the PD1 at the rising edge of the CK1, the flip-flop 17 of the PD2 receives the data at the rising edge of the CK2, and simultaneously transmits the data to the integrated circuit chip 20, and the buffer of the PD9 at the rising edge of the CK9. 25 receives the data. Conversely, when transferring the data of the integrated circuit chip 20 to the processor core, the data is output from the flip-flop 26 of the PD 9 at the rising edge of CK 9 and the flip-flop 27 of the PD 2 receives the data at the rising edge of CK 2. Data is output, and the flip-flop 28 of PD1 receives the data at the rising edge of CK1.

  FIG. 14A and FIG. 14B are diagrams for explaining a problem when VDFS is performed. During a period when tCK1 and tCK2 are equal (until time t1 in FIG. 12B or after time t4), the data transmitted from the flip-flop 15 at the rising edge of CK1 is transmitted by the flip-flop 17 at the next rising edge of CK2. Can receive. This is illustrated in FIG. 14A. The data receiving circuit of PD2 expects to receive data at the rising edge of CK2. However, when VD1 is lower than VD2 (period from time t2 to time t3 in FIG. 12B), tCK1 becomes longer than tCK2, so that the rising edge of CK1 on the transmission side is delayed, and the data receiving circuit of PD2 is expected. The data cannot be received at the rising edge of CK2. This is illustrated in FIG. 14B.

  Thus, it is necessary to prevent the phenomenon that data cannot be received at the expected edge. Therefore, a technique has been proposed in which a variable delay circuit capable of adjusting the delay is inserted in the middle of the clock wiring of CK1, and the delay is controlled by the output of the phase comparator that detects the phase difference between the rising edges of CK1 and CK2. Patent Document 1).

  FIG. 15 is a diagram showing an integrated circuit chip provided with a variable delay circuit for delay control. In FIG. 15, the same components as those of FIG. 12A are referred to by the same numerals, and a description thereof will be omitted. The integrated circuit chip 10A of FIG. 15 includes a phase comparison circuit 31, a variable delay circuit 32, and a fixed delay circuit 33 in addition to the components shown in FIG. 12A.

  The phase comparison circuit 31 constantly compares the phase of CK1 and the phase of CK2 so that tCK1 and tCK2 are the same, and the delay amount of the variable delay circuit 32 inserted into CK1 is controlled according to the comparison result. For example, consider the case where the voltage of PD1 decreases. As the voltage of PD1 decreases, the delay of tCK1 increases. Then, the phase difference between CK1 and CK2 shifts toward the slower CK1. The phase comparison circuit 31 measures the phase relationship and the amount of deviation thereof, and generates a control signal that shortens the delay of the variable delay circuit 32. Based on this control signal, the variable delay circuit 32 shortens the delay. By repeating this operation, tCK1 and tCK2 can be made the same length, and data transfer can be performed correctly. Here, it is necessary to insert a fixed delay circuit 33 that delays the delay in the middle of CK2 so that tCK1 and tCK2 become the same when the voltage of PD1 is the lowest (when tCK1 becomes the longest).

  As a method for clock phase alignment between chips, for example, there is a method using PLL or DLL for clock phase alignment between a memory controller and a memory chip. In these methods, the voltage setting is fixed, but due to fluctuations in the actual voltage caused by disturbances, fluctuations in propagation delay caused by differences in connection status between chips, temperature changes during use, and process variations It is possible to adjust the phase with respect to the timing variation without any problem. However, it cannot cope with a situation in which the clock time changes during operation by more than three times due to an intentional power supply voltage change, such as DVFS.

  When the technique of Non-Patent Document 1 described above is used, the fixed delay circuit 33 inserted into tCK2 always generates a fixed delay. Therefore, even when PD1 is the highest voltage and the delay of CK1 is the shortest, this fixed delay circuit 33 A clock delay including a delay occurs. For example, assume that the delay time of the clock propagation path of PD1 and PD2 is 1 ns when the power supply voltage is 1.2V. Further, when the power supply voltage of PD1 is the lowest voltage value 0.6V, the delay of the clock propagation path of PD1 is 6 ns. In such a case, it is necessary to set the total delay of the clock propagation path of the PD 2 and the fixed delay circuit 33 to 6 ns in accordance with the latest delay time. As a result, tCK2 on the PD2 side is always 6 ns, and even if the power supply voltage changes on the PD1 side, tCK1 is always set to 6 ns. That is, for example, tCK1 when the power supply voltage of PD1 is 1.2 V becomes 6 ns in total by providing a long delay with the variable delay circuit 32 even though the delay of the clock propagation path itself is only 1 ns.

When the clock delay increases, the clock jitter accompanying the power fluctuation increases, or the clock delay variation (clock skew) due to the process variation increases. For example, when a clock jitter of 10% of the clock delay occurs, a jitter of 600 ps occurs with a clock delay of 6 ns. When there was no DVFS, the jitter was only 100 ps, which is 10% of the clock delay of 1 ns, but the provision of DVFS increases the jitter to 600 ps. As a result, it is necessary to use a clock signal having a longer period with a margin, which causes the operation speed to be limited. In particular, even when it is desired to operate at the highest speed with the power supply voltage of PD1 set to the maximum voltage, there is a problem that the clock frequency cannot be increased because of the large jitter.
Toshihide Fujiyoshi, et al., "An H.264 / MPEG-4 Audio / Visual Coded LSI with Module-Wise Dynamic Voltage / Frequency Scaling," ISSCC (IEEE International Solid-State Circuits Conference) Digest of technical paper, pp.132-133 , 2005

  In view of the above, according to the present invention, in a plurality of circuit blocks operating with a plurality of different power supply voltages, the power supply voltage is variably controlled, and the clock delay time between the plurality of blocks can be aligned while shortening the clock delay as much as possible. An object of the present invention is to provide a simple integrated circuit chip.

The semiconductor integrated circuit includes a first flip-flop that operates based on a first clock, a first circuit block that operates with a first power supply voltage whose voltage value is variably controlled, and a second clock. A second circuit block including a second flip-flop that operates and operating at a second power supply voltage; a phase of the first clock supplied to the first flip-flop; and a second flip-flop A phase comparison circuit for outputting a value corresponding to a phase difference from the phase of the second clock to be supplied, and the second flip-flop supplied to the second flip-flop according to an output value of the phase comparison circuit A first variable delay circuit for delaying a phase of the clock, the first power supply voltage being variably controlled , and substantially the same as a delay of a path for supplying the first clock to the first flip-flop; With the delay of And a second simulated delay path having substantially the same delay as a path of supplying the second clock to the second flip-flop, and the phase comparison circuit includes: It is configured to output a value corresponding to a comparison between the phase of the signal propagating through the first simulated delay path and the phase of the signal propagating through the second simulated delay path .

  According to at least one embodiment of the present invention, the clock is supplied to the second circuit block instead of the first clock supply path that supplies the clock to the first circuit block whose power supply voltage is variably controlled. By controlling the delay of the variable delay circuit provided in the middle of the second clock supply path, it is configured to follow the delay amount change of the first clock supply path accompanying the change of the power supply voltage of the first circuit block. Has been. That is, in the prior art, when the power supply voltage rises and the clock delay of the clock supply path decreases, the delay amount of the variable delay circuit provided in the clock supply path is increased so that the entire delay amount becomes constant. Is controlling. On the other hand, in the present invention, when the power supply voltage decreases and the clock delay of the clock supply path increases, the delay amount of the variable delay circuit provided in the counterpart clock supply path is increased to reduce the delay amount of the counterpart side. I try to make it follow. Therefore, in the prior art, when the power supply voltage is set to the maximum voltage and it is desired to operate at the highest speed, there is a problem that a large jitter exists and the clock frequency cannot be increased. However, in the present invention, the power supply voltage is increased. Accordingly, the total delay amount of the clock supply path is shortened accordingly, and the jitter is also reduced. Therefore, the problem that the operation speed is limited by jitter is reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1A is a diagram showing a first embodiment of an integrated circuit chip according to the present invention. An integrated circuit chip 40 shown in FIG. 1A includes a circuit block 41 and a circuit block 42. The circuit blocks 41 and 42 correspond to two power supply domains PD1 and PD2 to which different power supplies are supplied. Here, the power supply voltage is variably controlled for the circuit block 41 of the domain PD1. The power supply voltage is fixed for the circuit block 42 of the domain PD2. The circuit block 41 is a circuit block including a processor core, and the circuit block 42 is a circuit block including its input / output circuit.

  The input clock of the flip-flop 45 in the circuit block 41 of PD1 is supplied from the PLL circuit 43 mounted on the integrated circuit chip 40. Specifically, the clock signal CK0 output from the PLL circuit 43 is delayed and divided by the variable delay circuit 48 and the 1 / m frequency divider 44 in the voltage-fixed PD2, and the PD1 domain flip-flop as the clock signal CK1. Is supplied to the controller 45. In this case, the total propagation time of the clock signal is tCK1. The clock signal immediately after the output of the 1 / m frequency divider 44 is assumed to be CK01.

  Similarly, the input clock of the flip-flop 47 in the circuit block 42 of PD2 is also supplied from the PLL circuit 43. Specifically, the clock signal CK0 output from the PLL circuit 43 is delayed and divided by the variable delay circuit 49 and the 1 / n frequency divider 46 in the voltage-fixed PD2, and the PD2 domain flip-flop is obtained as the clock signal CK2. Is supplied to the head 47. In this case, the total propagation time of the clock signal is tCK2. The clock signal immediately after the output of the 1 / n divider 46 is CK02.

  The clock CK1 reaching the flip-flop 45 of PD1 and the clock CK2 reaching the flip-flop 47 of PD2 are input to the phase comparison circuit 50. The phase comparison circuit 50 outputs phase difference signals SCK1 and SCK2 according to the comparison result between the phase of the clock CK1 and the phase of the clock CK2. Based on the phase difference signals SCK1 and SCK2, the control circuit 51 outputs control signals CNT1 and CNT2. The control signal CNT1 is supplied to the variable delay circuit 48 inserted in the clock supply path to CK1. The control signal CNT2 is supplied to the variable delay circuit 49 inserted in the clock supply path to CK2.

  As described above, the integrated circuit chip 40 according to the present invention shown in FIG. 1A includes the circuit block 41 including the flip-flop 45 and operating at the first power supply voltage, and the circuit block 42 including the flip-flop 47 and operating at the second power supply voltage. A first clock supply path connected to the clock input terminal of the flip-flop 45 and supplying the clock CK1, a second clock supply path connected to the clock input terminal of the flip-flop 47 and supplying the clock CK2, and a flip-flop The phase comparison circuit 50 outputs a value corresponding to the phase difference between the phase of the clock CK1 at the clock input terminal 45 and the phase of the clock CK2 at the clock input terminal of the flip-flop 47, and the output value of the phase comparison circuit 50 Variable delay provided in the middle of the second clock supply path whose delay time changes Including the road 49. In this configuration, the first power supply voltage is variably controlled.

  FIG. 1B is a diagram illustrating changes in power supply voltage and clock propagation time. For the case where the power supply voltage of PD1 is switched, (a) power supply voltage, (b) clock propagation time tCK1, and (c) clock propagation time tCK2 are shown.

  Until time t1, the processor core (circuit block 41) requires high processing capability, so the PD1 clock is operated at a high frequency. During this period, PD1 and PD2 are set to predetermined power supply voltages (may be the same power supply voltage), and clock propagation time tCK1 (from PLL circuit 43 to flip-flop 45 of PD1) and tCK2 (PLL Assume that the circuit 43 to the flip-flop 47 of PD2 are designed to be equal. After time t1, the amount of processing required for the circuit block 41 has decreased, so the frequency of CK1 is lowered. As a result, normal operation can be achieved even if the power supply voltage of PD1 is lowered, so the voltage of PD1 is lowered at time t2. As a result, as shown in FIG. 1B (b), the delay of the clock supply path portion in PD1 increases, and the total propagation time tCK1 increases accordingly. Since the phase of the clock CK1 changes, the delay of the variable delay circuit 49 increases as shown in FIG. 1B (c) according to the output of the phase comparison circuit 50 that detects the phase difference between CK1 and CK2. The increase in the delay of the variable delay circuit 49 follows the increase in the delay of the clock supply path portion in the PD 1 by feedback control. Therefore, as shown in (b) and (c), tCK1 and tCK2 are always adjusted to have the same length.

  Unlike the configuration of the prior art shown in FIG. 15, the variable is provided in the middle of the second clock supply path for supplying the clock to the circuit block 42 instead of the first clock supply path for supplying the clock to the circuit block 41. By controlling the delay of the delay circuit 49, the delay amount of the first clock supply path following the change of the power supply voltage of the circuit block 41 is followed. That is, in the prior art, when the power supply voltage rises and the clock delay of the clock supply path decreases, the delay amount of the variable delay circuit provided in the clock supply path is increased so that the entire delay amount becomes constant. Is controlling. On the other hand, in the present invention, when the power supply voltage decreases and the clock delay of the clock supply path increases, the delay amount of the variable delay circuit provided in the counterpart clock supply path is increased to reduce the delay amount of the counterpart side. I try to make it follow. Therefore, in the prior art, when the power supply voltage of PD1 is set to the maximum voltage and it is desired to operate at the highest speed, there is a problem that a large jitter exists and the clock frequency cannot be increased. Accordingly, the total delay amount of the clock supply path is shortened accordingly, and the jitter is also reduced. Therefore, there is no problem that the operation speed is limited by jitter.

  In order to reduce the jitter as much as possible, the delay amount of the variable delay circuit 49 is set to the minimum value of the variable range when the power supply voltage of the PD 1 is set to the maximum voltage of the variable range. Is desirable. By setting in this way, the amount of jitter can be minimized when operating at maximum speed using the maximum voltage and maximum frequency.

  As described above, when only the circuit block 41 in the integrated circuit chip 40 is subject to variable power supply voltage control, the provision of the variable delay circuit 49 has the purpose of adjusting tCK1 and tCK2 to the same length. Can be achieved. However, as described above, in order to reduce the jitter as much as possible, it is desirable to set the delay amount of the variable delay circuit 49 to the minimum value of the variable range when the power supply voltage of the PD 1 is set to the maximum voltage of the variable range. . However, the delay of the clock supply path when the power supply voltage is set to the maximum voltage may vary due to process variations, temperature fluctuations, etc., and the variable range of the power supply voltage may vary depending on the operating environment. Therefore, if the circuit is designed so that the delay amount of the variable delay circuit 49 becomes the minimum value when the power supply voltage of the PD 1 is set to the maximum voltage, the circuit operates normally when the circuit is actually operated. There is a possibility that it will not. Therefore, this problem can be solved by inserting the variable delay circuit 48 in the clock supply path on the PD1 side whose power supply voltage is variably controlled. This will be described below.

  FIG. 2A is a diagram for explaining the operation of the phase comparison circuit 50. After the integrated circuit chip 40 is released from reset and enters the normal use mode, the phase comparison circuit 50 compares the phase of CK1 with the phase of CK2 (step S1). If the phase difference is equal to or smaller than the predetermined value α, SCK1 = 0 and SCK2 = 0 are output (step S2). α is set, for example, as a delay value measured in units of time such as 50 ps, or as a phase angle with respect to the clock cycle such as 5 degrees. In step S3, the magnitudes of the phases are compared. If CK1 is later than CK2 by a phase difference α or more, SCK1 = 1 and SCK2 = 0 are output (step S4). Conversely, when CK2 is later than CK1 by a phase difference α or more, SCK1 = 0 and SCK2 = 1 are output (step S5).

  FIG. 2B is a diagram for explaining the control operation of the control circuit 51. Immediately after the reset of the integrated circuit chip 40 is released, the output of the control circuit 51 is set to CNT1 = 000 and CNT2 = 000 (step S1). The values of CNT1 and CNT2 correspond to the delay amounts of the variable delay circuit 48 and the variable delay circuit 49, respectively. If CNT1 = 000 and CNT2 = 000, the delays of the variable delay circuit 48 and the variable delay circuit 49 are set to the minimum.

  Next, when SCK1 = 1 is detected (when the phase of CK1 is later than that of CK2: yes in step S2), if CNT1 is 000 (that is, if the delay of the variable delay circuit 48 cannot be made smaller than the current value). : Yes in step S3), the value of CNT2 is increased by 1 (step S4). As a result, the delay amount of the variable delay circuit 49 is increased. If the value of CNT1 is not 000 (that is, if the delay of the variable delay circuit 48 can be made smaller than the current value: no in step S3), the value of CNT1 is decreased by 1 (step S5). As a result, the delay of the variable delay circuit 48 is reduced.

  When SCK2 = 1 is detected (when the phase of CK2 is later than CK1: yes in step S6), if CNT2 is 000 (that is, if the delay of the variable delay circuit 49 cannot be made smaller than the current value: in step S7) yes), the value of CNT1 is incremented by 1 (step S8). As a result, the delay of the variable delay circuit 48 increases. If CNT2 is not 000 (that is, if the delay of the variable delay circuit 49 can be made smaller than the current value: no in step S7), CNT2 is decreased by 1 (step S9). As a result, the delay of the variable delay circuit 49 is reduced.

  In this way, the delay of either the variable delay circuit 48 or the variable delay circuit 49 is preferentially reduced, and the other delay is increased only when the delay cannot be reduced below the current value. To adjust the phases of CK1 and CK2. Such adjustment makes it possible to always set the delay amounts of the variable delay circuits 48 and 49 to the minimum necessary state. That is, even when the delay of the clock supply path when the power supply voltage of PD1 is set to the maximum voltage in the variable range varies due to various factors, the delay amount of the variable delay circuit 49 is set to the minimum value in the variable range. It is possible to set and operate normally.

  FIG. 3 is a time chart for explaining the operation of the integrated circuit chip 40 of FIG. 1A. Before time t1 and after time t4, the power supply voltage of PD1 is higher than the power supply voltage of PD2, and the power supply voltage of PD1 is lower between times t1 and t4. In addition, the waveforms in the case of the frequency division ratio m = 2 and n = 2 are shown.

  Until time t1, the delay from CK0 (output of the PLL circuit 43) to CK1 (input of the flip-flop 45 in the PD1 domain) and the clock delay from CK0 to CK2 (input of the flip-flop 47 in the PD2 domain) are the same. . Therefore, the phases of CK1 and CK2 are equal, and SCK1 = 0 and SCK2 = 0.

  After the time t1, the power supply voltage of PD1 decreases and the delay from CK01 (output of 1 / m frequency divider 44) to CK1 increases. As a result, the phase of CK1 is delayed from CK2, and SCK1 = 1 and SCK2 = 0. At this time, if CNT1 indicates the shortest 000, CNT2 changes from 000 to 001. As a result, the delay from CK0 to CK02 (output of the 1 / n frequency divider 46) increases, and the phases of CK2 and CK1 coincide. If the phases match, SCK1 = 0 and SCK2 = 0 are returned, and CNT2 becomes constant at 001.

  After time t4, the power supply voltage of PD1 becomes high again, and the delay from CK01 to CK1 becomes short. Therefore, since the phase of CK1 is earlier than that of CK2, SCK = 0 and SCK2 = 1. At this time, since CNT2 is 001, CNT2 is set to 000 to reduce the delay amount of the variable delay circuit 49. As a result, the phases of CK1 and CK2 coincide again.

  FIG. 4A is a diagram showing a second embodiment of an integrated circuit chip according to the present invention. In FIG. 4A, the same components as those in FIG. 1A are referred to by the same numerals, and a description thereof will be omitted.

  An integrated circuit chip 40A shown in FIG. 4A includes a circuit block 41, a circuit block 42A, and a circuit block 42B. The circuit blocks 41, 42A, and 42B correspond to the three power domains PD1, PD0, and PD2 to which different power is supplied. Here, the power supply voltage is variably controlled for the circuit block 41 of the domain PD1 and the circuit block 42B of the domain PD2. The power supply voltage is fixed for the circuit block 42A of the domain PD0. The circuit block 41 is a circuit block including a processor core, and the circuit block 42B is a circuit block including the input / output circuit.

  In the configuration shown in FIG. 4A, since the variable delay circuit is included in both clock paths for data transmission and reception, the power supply voltage is variably controlled independently for the circuit block 41 of the domain PD1 and the circuit block 42B of the domain PD2. Even in this case, the data can be normally transferred with the clock phases aligned on the transmission side and the reception side. The control of the delay amount based on the phase detection in this case may be the same as the control shown in FIGS. 2A and 2B.

  FIG. 4B is a diagram illustrating changes in the power supply voltage and the clock propagation time. For the case where the power supply voltages of PD1 and PD2 are switched, (a) power supply voltage, (b) clock propagation time tCK1, and (c) clock propagation time tCK2 are shown.

  Until time t1, both the variable delay circuit 48 and the variable delay circuit 49 are set to the shortest delay. Since the power supply voltage of PD2 drops at time t1, the delay of the variable delay circuit 48 increases and the phase of CK1 and the phase of CK2 are matched. When the time t2 is exceeded, the power supply voltage of the PD1 decreases, so that the phase of the CK1 is delayed (the delay in the PD1 increases). At this time, since the delay of the variable delay circuit 48 is not the shortest, the delay value of the variable delay circuit 48 decreases, and the phase of CK1 and the phase of CK2 are matched. Next, after the time t3, the power supply voltage of the PD2 is increased, so that the phase of the CK2 is advanced, that is, the phase of the CK1 is relatively delayed. Since the variable delay circuit 48 is already the shortest, the delay of the variable delay circuit 49 increases and the phases of CK1 and CK2 are matched. After time t4, since the power supply voltage of PD1 becomes high, the phase of CK1 becomes early, that is, the phase of CK2 becomes late. At this time, since the delay of the variable delay circuit 49 is not the shortest, the delay is reduced and the phases of CK1 and CK2 are matched.

  4A, the phase comparison circuit 50, the control circuit 51, the variable delay circuits 48 and 49, the 1 / m frequency divider 44, the 1 / n frequency divider 46, and the PLL circuit 43 are arranged in the fixed voltage domain of PD0. However, it may be arranged in a variable voltage domain. However, by arranging in the fixed voltage domain, the circuit can be operated more stably. For example, there is an advantage that the delay amount per step of the variable delay circuits 48 and 49 can be fixed, and the jitter generated in each circuit can be reduced.

  FIG. 5 is a diagram showing a third embodiment of an integrated circuit chip according to the present invention. In FIG. 5, the same components as those in FIG. 1A are referred to by the same numerals, and a description thereof will be omitted.

  An integrated circuit chip 40B shown in FIG. 5 includes a circuit block 41 and a circuit block 42C. The circuit blocks 41 and 42C correspond to the two power domains PD1 and PD2 to which different power is supplied. Here, the power supply voltage is variably controlled for the circuit block 41 of the domain PD1. The power supply voltage is fixed for the circuit block 42C of the domain PD2. The circuit block 41 is a circuit block including a processor core, and the circuit block 42C is a circuit block including the input / output circuit.

  The integrated circuit chip 40B shown in FIG. 5 differs from the integrated circuit chip 40 shown in FIG. 1A in that the variable delay circuit 48 is not provided. Accordingly, a control circuit 51B that outputs one control signal CNT1 is provided instead of the control circuit 51 that outputs two control signals CNT1 and CNT2. The operation of the phase comparison circuit 50 may be the same as that shown in FIG. 2A.

  FIG. 6 is a diagram for explaining the control operation of the control circuit 51B. Immediately after the reset of the integrated circuit chip 40 is released, the output of the control circuit 51 is set to CNT2 = 000 (step S1). The value of CNT2 corresponds to the delay amount of the variable delay circuit 49. If CNT2 = 000, the delay of the variable delay circuit 49 is set to the minimum.

  Next, when SCK1 = 1 is detected (when the phase of CK1 is later than that of CK2: yes in step S2), the value of CNT2 is incremented by 1 (step S3). As a result, the delay amount of the variable delay circuit 49 is increased. When SCK2 = 1 is detected (when the phase of CK2 is later than CK1: yes in step S4), CNT2 is decreased by 1 (step S5). As a result, the delay of the variable delay circuit 49 is reduced.

  FIG. 7 is a diagram showing a fourth embodiment of an integrated circuit chip according to the present invention. In FIG. 7, the same components as those in FIG. 1A are referred to by the same numerals, and a description thereof will be omitted.

  The integrated circuit chip 40C in FIG. 7 includes a circuit block 41C and a circuit block 42D. The circuit blocks 41C and 42D coincide with two power domains PD1 and PD2 to which different power is supplied. Here, the power supply voltage is variably controlled for the circuit block 41C of the domain PD1. The power supply voltage is fixed for the circuit block 42D of the domain PD2. The circuit block 41C is a circuit block including a processor core, and the circuit block 42D is a circuit block including the input / output circuit.

  The integrated circuit chip 40C of FIG. 7 has a first simulated delay having substantially the same delay as the delay of the clock supply path from the variable delay circuit 48 to the flip-flop 45, as compared with the integrated circuit chip 40 of FIG. 1A. The difference is that the path 61 further includes a second simulated delay path 62 having substantially the same delay as the delay of the clock supply path from the variable delay circuit 49 to the flip-flop 47. The phase comparison circuit 50 compares the phase of the signal propagating through the first simulated delay path 61 with the phase of the signal propagating through the second simulated delay path 62, so as to respond to the phase difference between CK1 and CK2. Configured to output a value.

  The frequency of the voltage variable domain clock is variably controlled by DVFS or the like. Therefore, for example, the phase comparison circuit 50 shown in FIG. 1A needs to be able to perform phase comparison between clock signals having different frequencies, instead of simply comparing the timing of each rising edge between clock signals having the same frequency. That is, an operation for comparing the timings of the rising edges while thinning out the edge of one of the clock signals is required.

  In the configuration shown in FIG. 7, a clock signal having a constant frequency before being input to the 1 / m frequency divider 44 and the 1 / n frequency divider 46 is used for phase comparison so that the phase comparison can be easily performed. Specifically, the first simulated delay path 61 and the second simulated clock signal have the same delay in the same voltage domain as the clock signal supplied to the flip-flops 45 and 47. A delay path 62 is provided.

  For CK1, the clock before being divided to 1 / m immediately after the variable delay circuit 48 is branched, and a buffer is provided so as to have the same delay as the clock delay distributed to the flip-flop 45 in the PD1 domain. The signal is input to the phase comparison circuit 50 via the first simulated delay path 61 inserted in a plurality of stages. On the other hand, for CK2, the clock before being divided by 1 / n immediately after the variable delay circuit 49 is branched so that the clock delay is the same as the clock delay distributed to the flip-flop 47 in the PD2 domain. The signal is input to the phase comparator 50 via the second simulated delay path 62 in which a plurality of buffers are inserted. In this way, even if the value of m is changed by DVFS, or the frequency ratio of the processor core and the input / output circuit is changed by the clock mode and the value of n is changed, the simulation delay paths 61 and 62 are simply changed. Therefore, the phase comparison circuit 50 can be realized with a relatively simple circuit.

  FIG. 8 is a diagram showing a fifth embodiment of the integrated circuit chip according to the present invention. In FIG. 8, the same components as those of FIGS. 1A, 5 and 7 are referred to by the same numerals, and a description thereof will be omitted.

  An integrated circuit chip 40D shown in FIG. 8 includes a circuit block 41C and a circuit block 42E. The integrated circuit chip 40D shown in FIG. 8 differs from the integrated circuit chip 40C shown in FIG. 7 in that the variable delay circuit 48 is not provided. Accordingly, a control circuit 51B that outputs one control signal CNT1 is provided instead of the control circuit 51 that outputs two control signals CNT1 and CNT2. The operation of the phase comparison circuit 50 is the same as that shown in FIG. 2A. The operation of the control circuit 51B is the same as that shown in FIG. Similar to the configuration shown in FIG. 7, the phase comparison circuit 50 can be realized by a relatively simple circuit because the simulation delay paths 61 and 62 are simply compared for each edge.

  FIG. 9 is a diagram showing a sixth embodiment of an integrated circuit chip according to the present invention. In FIG. 9, the same components as those in FIG. 1A are referred to by the same numerals, and a description thereof will be omitted.

  FIG. 9 shows a case where the data transferred from the processor core circuit of the circuit block 41 to the input / output circuit of the circuit block 42F in the integrated circuit chip 40E is further transferred to the user interface control circuit of another integrated circuit chip 70. ing. The integrated circuit chip 70 includes a PLL circuit 71 that generates an internal clock signal based on the same clock signal as the clock signal CKIN input to the PLL circuit 43 of the integrated circuit chip 40E, and a clock generated by the PLL circuit 71. 1 / n frequency divider 72 and a flip-flop 73 that receives the divided clock signal CK9.

  This configuration is characterized in that the output clock CK02 of the variable delay circuit 49 is fed back to the PLL circuit 43 via the feedback path 65. When data is transferred from the processor core to the input / output circuit, the delay value of the variable delay circuit 49 is variably controlled, so that the rising edge of CK2 varies relative to the rising edge of the output clock CK0 of the PLL circuit 43. . In the configuration of FIG. 9, since CK02 is fed back to the PLL circuit 43 via the feedback path 65, the phase between CKIN and CK02 is always kept constant. Therefore, the phase between CKIN and CK2 is also kept constant. Thereby, data can be sent to the user interface control circuit (flip-flop 73) of the integrated circuit chip 70 in synchronization with the rising edge of the external CKIN.

  In this example, the example of data transfer from the processor core to the user interface is shown. However, it is obvious that the data transfer from the user interface circuit to the processor core is also possible.

  FIG. 10 is a diagram showing a seventh embodiment of an integrated circuit chip according to the present invention. 10, the same components as those in FIG. 1A are referred to by the same numerals, and a description thereof will be omitted.

  An integrated circuit chip 40F illustrated in FIG. 10 includes a circuit block 41, a circuit block 42G, and a circuit block 85. The circuit block 41, the circuit block 42G, and the circuit block 85 correspond to the power domains PD1, PD2, and PD3, respectively. PD1 and PD3 are variably controlled in power supply voltage, and PD2 is a fixed power supply voltage.

  The input clock of the flip-flop 86 in the circuit block 85 of PD3 is supplied from the PLL circuit 43 mounted on the integrated circuit chip 40F. Specifically, the clock signal CK0 output from the PLL circuit 43 is delayed and divided by the variable delay circuit 82 and the 1 / k frequency divider 81 in the voltage-fixed PD2, and the PD3 domain flip-flop as the clock signal CK3. Supplied to 86.

  In order to synchronize data transfer among the three power domains PD1, PD2, and PD3, the phases of the three clocks CK1, CK2, and CK3 must be matched. Therefore, a phase comparison circuit 50 that detects the phase difference between CK1 and CK2 and a phase comparison circuit 80 that detects the phase difference between CK3 and CK2 are provided. A control circuit 83 that generates control signals CNT1 and CNT2 based on the phase difference signals SCK11 and SCK12 that are outputs of the phase comparison circuit 50 and the phase difference signals SCK22 and SCK23 that are outputs of the phase comparison circuit 80 is provided.

  FIG. 11 is a diagram illustrating the operation of the control circuit 83. FIG. 11 shows in tabular form how the values of the control signals CNT1 and CNT2 are changed based on the phase difference signals SCK11, SCK12, SCK22, and SCK23.

  For example, when the phase of CK2 is slower than the phase of CK1 (SCK11 = 0, SCK12 = 1), and the phase of CK2 is later than the phase of CK3 (SCK22 = 1, SCK23 = 0) (column indicated by B in FIG. 11). Think. First, the variable control circuits 49 and 82 are controlled so that the phase of CK2 and the phase of CK3 are matched. Specifically, when CNT2 is not 000, CNT2 is decreased by 1. When CNT2 is 000, CNT3 is increased by 1. By repeating this, the phase of CK2 coincides with the phase of CK3. That is, both SCK2 and SCK3 are zero. At this time, if the phase of CK2 is still slower than the phase of CK1, the condition of the column indicated by A in FIG. 11 is satisfied, and the phase of CK1 is adjusted while changing CK2 and CK3 together. Specifically, if both CNT2 and CNT3 are not 000, both CNT2 and CNT3 decrease by one. If either CNT2 or CNT3 is 000, CNT3 is incremented by one. By repeating this, the phases are aligned for all of CK1, CK2, and CK3. In FIG. 11, “*” indicates don't care.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

1 is a diagram showing a first embodiment of an integrated circuit chip according to the present invention. It is a figure which shows the change of a power supply voltage and clock propagation time. It is a figure for demonstrating operation | movement of a phase comparison circuit. It is a figure for demonstrating control operation of a control circuit. It is a time chart for demonstrating operation | movement of the integrated circuit chip of FIG. 1A. It is a figure which shows the 2nd Example of the integrated circuit chip by this invention. It is a figure which shows the change of a power supply voltage and clock propagation time. It is a figure which shows the 3rd Example of the integrated circuit chip by this invention. It is a figure for demonstrating control operation of a control circuit. It is a figure which shows the 4th Example of the integrated circuit chip by this invention. FIG. 7 is a diagram showing a fifth embodiment of an integrated circuit chip according to the present invention. It is a figure which shows the 6th Example of the integrated circuit chip by this invention. It is a figure which shows the 7th Example of the integrated circuit chip by this invention. It is a figure which shows operation | movement of a control circuit. It is a figure which shows the chip | tip in which the circuit which operate | moves with two different types of power supply voltages is mounted. It is a figure which shows the change of a clock frequency, a power supply voltage, and a clock propagation time. It is a figure which shows the system which consists of a some integrated circuit chip and a power supply IC chip. It is a figure for demonstrating the problem in the case of implementing VDFS. It is a figure for demonstrating the problem in the case of implementing VDFS. It is a figure which shows the integrated circuit chip which provided the variable delay circuit for delay control.

Explanation of symbols

40 integrated circuit chip 41 circuit block 42 circuit block 43 PLL circuit 44 1 / m frequency divider 45 flip-flop 46 1 / n frequency divider 47 flip-flop 48 variable delay circuit 49 variable delay circuit 50 phase comparison circuit 51 control circuit

Claims (4)

A first circuit block including a first flip-flop that operates based on a first clock and that operates with a first power supply voltage whose voltage value is variably controlled;
A second circuit block including a second flip-flop operating with a second clock and operating with a second power supply voltage;
A phase comparison circuit that outputs a value corresponding to a phase difference between the phase of the first clock supplied to the first flip-flop and the phase of the second clock supplied to the second flip-flop When,
A first variable delay circuit for delaying a phase of the second clock supplied to the second flip-flop according to an output value of the phase comparison circuit, wherein the first power supply voltage is variably controlled; ,
A first simulated delay path having a delay that is substantially the same as a delay of a path for supplying the first clock to the first flip-flop;
And a second simulated delay path having substantially the same delay as the path of supplying the second clock to the second flip-flop, wherein the phase comparison circuit includes the first simulated delay. A semiconductor integrated circuit characterized by outputting a value corresponding to a comparison between a phase of a signal propagating through a path and a phase of a signal propagating through the second simulated delay path.   2. The semiconductor integrated circuit according to claim 1, wherein when the first power supply voltage is set to a maximum voltage in a variable range, a delay amount of the first variable delay circuit is set to a minimum value in the variable range. circuit. It further includes a second variable delay circuit provided in the middle of a path for supplying the first clock to the first flip-flop, and having a delay time that changes in accordance with the output value of the phase comparison circuit. the semiconductor integrated circuit according to claim 2 Symbol mounting to. When the second power supply voltage is variably controlled in addition to the first power supply voltage and the second power supply voltage is set to the maximum voltage in the variable range, the delay amount of the second variable delay circuit is 4. The semiconductor integrated circuit according to claim 3, wherein the semiconductor integrated circuit is set to a minimum value of a variable range.

Images