JP5481871B2 - Multi-power supply system, semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a multiple power supply system and a semiconductor integrated circuit that dynamically change a power supply voltage supplied to a plurality of circuit blocks.

  In recent years, electronic devices such as cellular phones equipped with semiconductor integrated circuits have been reduced in size and power consumption. It is also demanded to reduce power consumption for semiconductor integrated circuits. For the purpose of reducing power consumption, a different power supply voltage may be supplied for each circuit block.

  A multi-power supply system 100 shown in FIG. 1 includes a semiconductor integrated circuit 200 to which a different power supply voltage is supplied for each circuit block, and a power supply control circuit 300. In the semiconductor integrated circuit 200, the first circuit block 20 using the first power supply voltage (PD1) and the second circuit block 30 using the second power supply voltage (PD2) are mixed. Here, the first power supply voltage (PD1) is a variable setting, and the second power supply voltage (PD2) is a fixed setting. The power supply control circuit 300 controls the first power supply voltage (PD1).

  The first circuit block 20 operating at the first power supply voltage (PD1) includes a processor core 40. The processor core 40 is a core part of the CPU that performs arithmetic processing, and includes a buffer 50 and a flip-flop circuit 60.

  The second circuit block 30 operating at the second power supply voltage (PD2) includes a PLL circuit 80, a function circuit 70, a phase comparison circuit 5, and a control circuit 85. The functional circuit 70 includes a buffer 55 and a flip-flop circuit 65.

  The phase comparison circuit 5 receives the first clock signal (CK1) input to the flip-flop circuit 60 and the second clock signal (CK2) input to the flip-flop circuit 65. The flip-flop circuit 60 operates in synchronization with the first clock signal (CK1), and the flip-flop circuit 65 operates in synchronization with the second clock signal (CK2). The phase comparison circuit 5 compares the phase difference between both input signals and outputs comparison result signals (CKA1) and (CKA2). The control circuit 85 adjusts the phase difference between the first clock signal (CK1) and the second clock signal (CK2) in accordance with the comparison result signals (CKA1) and (CKA2).

  The reason why the control circuit 85 adjusts the phase difference is that when the data (DATA) is transferred from the flip-flop circuit 60 to the flip-flop circuit 65, the first clock signal (CK1) and the second clock signal (CK2) This is because if there is a phase difference, timing may be shifted at the time of data (DATA) delivery, and there is a possibility that the data cannot be delivered.

JP2008-227397

  Consider a case where the processing load of the processor core 40 changes and the first power supply voltage (PD1) changes. When the first power supply voltage (PD1) varies, a phase difference between the first clock signal (CK1) and the second clock signal (CK2) occurs. This phase difference is proportional to the voltage fluctuation in unit time. Depending on the degree of phase difference, data (DATA) may not be transferred from the flip-flop circuit 60 to which the first power supply voltage (PD1) is supplied to the flip-flop circuit 65 to which the second power supply voltage (PD2) is supplied. Sex occurs.

  The phase comparison circuit 5 detects the phase difference between the first clock signal (CK1) and the second clock signal (CK2), and the control circuit 85 adjusts the first clock signal (CK1) and the second clock signal ( The phase difference from CK2) becomes small.

  In order for the control circuit 85 to reduce the phase difference between the first clock signal (CK1) and the second clock signal (CK2), a finite time is required. This finite time is proportional to the phase difference and proportional to the fluctuation of the first power supply voltage (PD1) in unit time.

  The flip-flop to which the first power supply voltage (PD1) is supplied when the first power supply voltage (PD1) fluctuates in unit time and a phase difference occurs between the first clock signal (CK1) and the second clock signal (CK2). There is a possibility that data (DATA) may not be transferred from the flip-flop circuit 60 to the flip-flop circuit (65) to which the second power supply voltage (PD2) is supplied.

The present invention has been proposed in view of the above-described problems, and a multiple power supply that enables a synchronous operation between circuit blocks by adjusting a power supply voltage change sequence even when a power supply voltage is dynamically changed. and purpose thereof is to provide a system and a semiconductor integrated circuit.

The multi-power supply system disclosed in the present application includes a plurality of circuit blocks to which different power supply voltages are supplied, and a power supply control circuit that supplies different power supply voltages to the plurality of circuit blocks and controls the power supply voltages of the different power supply voltages. And a phase comparison circuit that compares the phases of the clock signals supplied to each of the plurality of circuit blocks, and a voltage that controls the change of the power supply voltage according to the detection result of the phase difference between the clock signals by the phase comparison circuit A voltage change circuit that outputs a change signal to the power supply control circuit, wherein the power supply control circuit changes the voltage value of one of the power supply voltages from the first voltage value to the second voltage value. the first power supply voltage according to a voltage change signal that varies based on the clock signal that varies in response to changes in the first power supply voltage stepwise changed to the second voltage value from the first voltage value, electric While the control circuit gradually changes the first power supply voltage from the first voltage value to the second voltage value, the voltage change circuit detects that the phase difference between the clock signals is greater than or equal to a predetermined value. In this case, the voltage difference signal for stopping the change of the first power supply voltage is output, and the phase difference between the clock signals is predetermined after the elapse of a predetermined period after the voltage change signal for stopping the change of the first power supply voltage is output. When the phase comparison circuit detects that the value is smaller than the value, a voltage change signal for restarting the change of the first power supply voltage is output .

  When changing the power supply voltage, the power supply control circuit changes the voltage value step by step. This change is performed according to a voltage change signal output from the voltage change circuit. The voltage change circuit outputs a voltage change signal for controlling the change of the power supply voltage to the power supply control circuit according to the detection result of the phase difference between the clock signals by the phase comparison circuit. The phase is detected by phase comparison by a phase comparison circuit.

A semiconductor integrated circuit disclosed in the present application includes a plurality of circuit blocks to which different power supply voltages are supplied, and a power supply control circuit that supplies different power supply voltages to the plurality of circuit blocks and controls the power supply voltages of the different power supply voltages. And a phase comparison circuit that compares the phases of the clock signals supplied to each of the plurality of circuit blocks, and a voltage that controls the change of the power supply voltage according to the detection result of the phase difference between the clock signals by the phase comparison circuit A voltage change circuit that outputs a change signal to the power supply control circuit, wherein the power supply control circuit changes the voltage value of one of the power supply voltages from the first voltage value to the second voltage value. the first power supply voltage according to a voltage change signal that varies based on the clock signal that varies in response to changes in the first power supply voltage stepwise changed to the second voltage value from the first voltage value, electric While the control circuit gradually changes the first power supply voltage from the first voltage value to the second voltage value, the voltage change circuit detects that the phase difference between the clock signals is greater than or equal to a predetermined value. In this case, the voltage difference signal for stopping the change of the first power supply voltage is output, and the phase difference between the clock signals is predetermined after the elapse of a predetermined period after the voltage change signal for stopping the change of the first power supply voltage is output. When the phase comparison circuit detects that the value is smaller than the value, a voltage change signal for restarting the change of the first power supply voltage is output .

  When the power supply voltage individually supplied to the circuit block is changed, the voltage change circuit changes the power supply voltage according to the detection result of the phase difference between the clock signals supplied to each of the plurality of circuit blocks. A voltage change signal to be controlled is output to the power supply control circuit. The output of the voltage change signal notifies that the change in the voltage value of the power supply voltage is acceptable. Here, the phase is detected by phase comparison by a phase comparison circuit.

  According to the present application, when there are a plurality of circuit blocks to which different power supply voltages are supplied, even when any of the power supply voltages is changed, the power supply voltage is changed step by step so that the circuit blocks having different power supply voltages can be changed. In this case, the phase shift is suppressed and the synchronous operation is enabled. Even when the power supply voltage is changed, a synchronous operation between circuit blocks operating at different power supply voltages can be ensured.

  If a synchronous operation between circuit blocks is ensured, data can be transferred between circuit blocks operating at different power supply voltages even when the power supply voltage is changed.

Block diagram of multi-power supply system of background art Block diagram of a multiple power supply system of the first embodiment Circuit diagram of voltage change permission circuit of first embodiment Block diagram of power supply control circuit Circuit diagram of counter clock generation circuit Circuit diagram of comparison circuit Circuit diagram of regulator circuit Waveform diagram of each signal in the power supply control circuit The flowchart which showed the effect | action of 1st Embodiment when fluctuating a 1st power supply voltage from 1.2V to 0.6V. Table showing correspondence between target voltage setting signal and first power supply voltage Table showing correspondence relationship between voltage switching signal, switching element, and first power supply voltage Circuit diagram of voltage change permission circuit of second embodiment

  The embodiment disclosed in the present application is suitable for application to Dynamic Voltage and Frequency Scaling (hereinafter referred to as DVFS). DVFS is to variably control the power supply voltage supplied to the processor core or the like and the frequency of the clock signal. An object of the present invention is to suppress unnecessary power supply and reduce power consumption by supplying an optimal power supply voltage and clock signal frequency according to the processing speed when the processor core performs arithmetic processing.

  In order to realize DVFS in a semiconductor integrated circuit having a processor core, a design having a plurality of power supply systems and capable of variably controlling at least one power supply voltage (hereinafter referred to as “multiple power supply design”) ).

  The configuration of the first embodiment will be described with reference to FIG. FIG. 2 is a block diagram of the first embodiment.

  A multi-power supply system 101 illustrated in FIG. 2 includes a semiconductor integrated circuit 201 and a power supply control circuit 301. The semiconductor integrated circuit 201 is a semiconductor integrated circuit designed for multiple power supplies. The first and second circuit blocks 20 and 31 in the semiconductor integrated circuit 201 are supplied with the first power supply voltage (PD1) and the second power supply voltage (PD2), respectively. Here, the first power supply voltage (PD1) is variable, and the second power supply voltage (PD2) is fixed.

  In FIG. 2, the first circuit block 20 indicates that a circuit in the block operates by being supplied with the first power supply voltage (PD1), and the second circuit block 31 indicates that the circuit in the block is the first circuit. It shows that it operates with power being supplied with two power supply voltages (PD2).

  The original clock signal (CK00) supplied from the outside of the semiconductor integrated circuit 201 is input to the PLL circuit 80 provided in the second circuit block 31. The PLL circuit 80 outputs a clock signal (CK0). The frequency of the clock signal (CK0) is synchronized with the original clock signal (CK00) by the PLL circuit 80. The clock signal (CK0) is input to the control circuit 85 provided in the second circuit block 31.

  The control circuit 85 outputs a first original clock signal (CK01) and a second original clock signal (CK02). The first original clock signal (CK01) is input to the buffer 50 in the processor core 40 provided in the first circuit block 20. The second original clock signal (CK02) is input to the buffer 55 in the functional circuit 70 provided in the second circuit block 31.

  The buffer 50 outputs the first clock signal (CK1). The buffer 55 outputs the second clock signal (CK2). The first clock signal (CK1) is input to the flip-flop circuit 60 in the processor core 40 and the phase comparison circuit 5 provided in the second circuit block 31. The second clock signal (CK2) is input to the flip-flop circuit 65, the voltage change permission circuit 1, and the phase comparison circuit 5 in the function circuit 70. The flip-flop circuit 60 transfers data (DATA) to the flip-flop circuit 65.

  The phase comparison circuit 5 compares the phase difference between the first clock signal (CK1) and the second clock signal (CK2), and outputs phase comparison result signals (CKA1) and (CKA2).

  When the phase of the first clock signal (CK1) is ahead of the phase of the second clock signal (CK2), the phase comparison circuit 5 sets the phase comparison result signal (CKA1) to the high level and the phase comparison result signal. (CKA2) is output at a low level.

  When the phase of the first clock signal (CK1) is delayed from the phase of the second clock signal (CK2), the phase comparison circuit 5 sets the phase comparison result signal (CKA1) to the low level and the phase comparison result signal. (CKA2) is output at a high level.

  When the phase of the first clock signal (CK1) and the phase of the second clock signal (CK2) substantially match, the phase comparison circuit 5 outputs the phase comparison result signals (CKA1) and (CKA2). Both output at low level.

  Here, substantially matching means that the phase difference between the phase of the first clock signal (CK1) and the phase of the second clock signal (CK2) is data (DATA) from the flip-flop circuit 60 to the flip-flop circuit 65. The phase difference is within a range that does not hinder the delivery of.

  The phase comparison result signals (CKA1) and (CKA2) are input to the control circuit 85 and the voltage change permission circuit 1. The control circuit 85 adjusts the phases of the first original clock signal (CK01) and the second original clock signal (CK02) according to the phase comparison result signals (CKA1) and (CKA2).

  Specifically, when the phase comparison result signal (CKA1) is input at a high level and the phase comparison result signal (CKA2) is input at a low level, the control circuit 85 determines the phase of the first original clock signal (CK01). Delay. When the phase comparison result signal (CKA1) is input at a low level and the phase comparison result signal (CKA2) is input at a high level, the control circuit 85 delays the phase of the second original clock signal (CK02). When the phase comparison result signals (CKA1) and (CKA2) are both input at a low level, the control circuit 85 sets the phase of the first original clock signal (CK01) and the phase of the second original clock signal (CK02). maintain.

  The clock (CK1) is synchronized with the original clock (CK01), and the clock (CK2) is synchronized with the original clock (CK02). The clock (CK1) and the original clock (CK01) are the output signal and input signal of the buffer 50, respectively, and the clock (CK2) and the original clock (CK02) are the output signal and input signal of the buffer 55, respectively. It is. Therefore, the phases of the clocks (CK1) and (CK2) are adjusted by adjusting the phases of the original clocks (CK01) and (CK02).

  The voltage change permission circuit 1 outputs a voltage change permission signal (PCEN). The voltage change permission signal (PCEN) is input to the power supply control circuit 301. Further, the power supply control circuit 301 receives an enable signal (EN), a switching signal (UPDN), a clock signal (CLK), and a target voltage setting signal (TG). The power supply control circuit 301 outputs a first power supply voltage (PD1) and a comparison result signal (CMP). The comparison result signal (CMP) is input to an external controller (not shown).

  The enable signal (EN), the switching signal (UPDN), and the target voltage setting signal (TG) are signals output from an external controller (not shown). The enable signal (EN) is a signal that permits voltage fluctuation of the first power supply voltage (PD1). When the enable signal (EN) is maintained at a high level, the first power supply voltage (PD1) can be varied.

  The switching signal (UPDN) is a signal for instructing whether to increase or decrease the first power supply voltage (PD1). The first power supply voltage (PD1) can be increased when the switching signal (UPDN) is maintained at a high level. When the switching signal (UPDN) is maintained at a low level, the first power supply voltage (PD1) can be lowered.

  The target voltage setting signal (TG) is a signal indicating the voltage value of the first power supply voltage (PD1) output from the power supply control circuit 301. Here, the target voltage setting signal (TG) is, for example, a 10-bit signal.

  The voltage change permission circuit 1 will be described with reference to FIG. FIG. 3 is an example of the voltage change permission circuit 1 as a whole.

  The phase comparison result signal (CKA1) is input to one terminal of the NOR circuit NOR. The phase comparison result signal (CKA2) is input to the other terminal of the NOR circuit NOR. The output terminal of the NOR circuit NOR is connected to the input terminal D1 of the D-type flip-flop circuit DFF1. The second clock signal (CK2) is input to the clock input terminal N1 of the D-type flip-flop circuit DFF1. The D-type flip-flop circuit DFF1 operates in synchronization with the second clock signal (CK2). A signal output from the output terminal Q1 of the D-type flip-flop circuit DFF1 is a voltage change permission signal (PCEN).

  When the phase comparison result signals (CKA1) and (CKA2) are both at a low level and the second clock signal (CK2) transitions from a low level to a high level, the high level signal output from the NOR circuit NOR is D. Type flip-flop circuit DFF1. As a result, a high level signal is output from the output terminal Q1 of the D-type flip-flop circuit DFF1. The voltage change enable signal (PCEN) becomes high level. When either of the phase comparison result signals (CKA1) and (CKA2) is at a high level and the second clock signal (CK2) transitions from a low level to a high level, the voltage change permission signal (PCEN) becomes a low level. One of the conditions that the first power supply voltage (PD1) varies is that the voltage change permission signal (PCEN) is maintained at a high level.

  The internal configuration of the power supply control circuit 301 will be described with reference to FIG. FIG. 4 is an example of the power supply control circuit 301 as a whole.

  The voltage change permission signal (PCEN) and the clock signal (CLK) are input to the counter clock generation circuit 6. The counter clock generation circuit 6 outputs a counter clock signal (CCK). The counter clock signal (CCK) is input to the voltage control circuit 7. The voltage control circuit 7 operates in synchronization with the counter clock signal (CCK). Further, the voltage control circuit 7 receives an enable signal (EN) and a switching signal (UPDN). One of the conditions for changing the logical value of the voltage switching signal (CV) is that the enable signal (EN) is maintained at a high level. One of the conditions for adding 1 to the voltage switching signal (CV) is that the switching signal (UPDN) is maintained at a high level. Maintaining the switching signal (UPDN) at a low level is one of the conditions for subtracting 1 from the voltage control voltage switching signal (CV).

  The voltage control circuit 7 outputs a voltage switching signal (CV). The voltage switching signal (CV) is a signal composed of the same bit string as the target voltage setting signal (TG) (here, 10 bits, for example). The voltage switching signal (CV) is input to the comparison circuit 8 and the regulator circuit 9. Further, the target voltage setting signal (TG) is input to the comparison circuit 8. The comparison circuit 8 compares the logical value of the voltage switching signal (CV) with the logical value of the target voltage setting signal (TG) and outputs a comparison result signal (CMP). A signal output from the regulator circuit 9 is the first power supply voltage (PD1).

  The internal configuration of the counter clock generation circuit 6 will be described with reference to FIG. FIG. 5 as a whole is an example of the counter clock generation circuit 6.

  A voltage change permission signal (PCEN) is input to the latch circuit LATCH. Further, a clock signal (CLK) is input to the latch circuit LATCH. The latch circuit LATCH operates in synchronization with the clock signal (CLK). The latch circuit LATCH holds the logic state of the voltage change permission signal (PCEN) when the clock signal (CLK) transits from a low level to a high level, for example. The held logic state signal is output. If the voltage change permission signal (PCEN) is maintained at a high level when the clock signal (CLK) transits from a low level to a high level, the latch circuit LATCH outputs a high level. On the contrary, when the voltage change permission signal (PCEN) is maintained at the low level, the latch circuit LATCH outputs the low level.

  Here, the latch circuit LATCH holds the logic state of the voltage change permission signal (PCEN) when the clock signal (CLK) transits from the low level to the high level. However, it is not limited to this. The logic state of the voltage change permission signal (PCEN) when the clock signal transitions from the high level to the low level may be held. The latch timing of the voltage change permission signal (PCEN) in the latch circuit LATCH may be determined by the clock signal (CLK).

The output terminal of the latch circuit LATCH is connected to one terminal of the AND circuit AND1. A clock signal (CLK) is input to the other terminal of the AND circuit AND1. A signal output from the output terminal of the AND circuit AND1 is a counter clock signal (CCK).

  The counter clock generation circuit 6 outputs a signal having the same phase as the clock signal (CLK) as the counter clock signal (CCK) only when the voltage change permission signal (PCEN) is maintained at a high level.

  The internal configuration of the comparison circuit 8 will be described with reference to FIG. FIG. 6 is an example of the comparison circuit 8 as a whole.

  Each bit (CV1 to CV10) of the voltage switching signal (CV) is input to one input terminal of a negative exclusive OR circuit (ENOR1 to ENOR10) corresponding to each bit (CV1 to CV10).

  Similarly, each bit (TG1 to TG10) of the target voltage setting signal (TG) is input to the other input terminal of the negative exclusive OR circuit (ENOR1 to ENOR10) corresponding to each bit (TG1 to TG10). The other exclusive input terminals of the negative exclusive OR circuits ENOR1 to ENOR10 corresponding to each bit (TG1 to TG10) are, for example, a negative exclusive logical sum circuit if the least significant bit (TG1) of the target voltage setting signal (TG). This is the other input terminal of ENOR1.

  Here, the least significant bit of the voltage switching signal (CV) is (CV1), the least significant bit from the least significant bit of the voltage switching signal (CV) is (CV2), and each time the higher order bit is sequentially moved thereafter. The most significant bit is expressed as (CV10) so as to be a large number. The same applies to the target voltage setting signal (TG). The numbers following CV and TG are shown to indicate the bit position from the least significant bit to the most significant bit.

  The output terminals of the negative exclusive OR circuits ENOR1 to ENOR10 are connected to the input terminals of the AND circuit AND2. A signal output from the output terminal of the AND circuit AND2 is a comparison result signal (CMP).

  The comparison circuit 8 outputs the comparison result signal (CMP) as a high level only when the logical value of the voltage switching signal (CV) and the logical value of the target voltage setting signal (TG) are the same. Here, the same logical value indicates that, for example, when the voltage switching signal (CV) is 0000000, the target voltage setting signal (TG) is also 0000000.

  The internal configuration of the regulator circuit 9 will be described with reference to FIG. 7 is an example of the regulator circuit 9 as a whole.

  A power supply voltage (VDD) is input to one terminal of the resistor element R1 and one terminal of the switch element SW1. The other terminal of the resistance element R1 is connected to one terminal of the resistance element R2. The other terminal of the resistance element R2 is connected to one terminal of the resistance element R3. Similarly, the state in which the other terminal of the resistor element Rn (n = 3 to 1024) is connected to one terminal of the resistor element R (n + 1) (n = 3 to 1024) continues to the resistor element R1024. The other terminal of the resistor element R1024 is grounded.

  One terminal of the resistor element R1 is connected to one terminal of the switch element SW1. One terminal of the resistor element R2 is connected to one terminal of the switch element SW2. Similarly, the state where one terminal of the resistance element Rn (n = 3 to 1024) is connected to one terminal of the switch element SWn (n = 3 to 1024) continues to the resistance element R1024.

  The other terminals of each of the switch elements SW1 to SW1024 are connected to each other. A voltage output to the connection point via any one of the switch elements SW1 to SW1024 is a reference voltage (VREF). This connection point is connected to the non-inverting input terminal of the amplifier AMP1, and the reference voltage (VREF) is input to the non-inverting input terminal of the amplifier AMP1.

  Here, the resistance values from the resistance element R1 to the resistance element R1023 are the same. The resistance value of the resistance element R1024 is a resistance value obtained by adding all the resistance values of the resistance elements from the resistance element R1 to the resistance element R1023. The connection relationship from the resistance element R1 to the resistance element R1024 is an example of a voltage dividing circuit. Thus, when the voltage value of the power supply voltage (VDD) is VDD, the voltage value output to one terminal of the resistance element Rn is VDD − (((VDD / 2) / 1023) × (n−1)). Become.

  A voltage switching signal (CV) is decoded and input to the control terminals from the switch element SW1 to the switch element SW1024. A logical value included in the voltage switching signal (CV) corresponds to conduction / non-conduction from the switch element SW1 to the switch element SW1024. That is, any one switch from the switch element SW1 to the switch element SW1024 is controlled to be in a conductive state by the signal 1024 obtained by decoding the voltage switching signal (CV).

  Specifically, the switch element SWm (m = 1 to 1024) having a numerical value obtained by converting the logical value of the voltage switching signal (CV) expressed in binary notation into decimal notation and adding 1 is turned on. . For example, when the logical value of the voltage switching signal (CV) is 0000000000000, only the switch element SW1 is turned on and all other switch elements are turned off.

  With the circuit connection of the regulator circuit 9 illustrated in FIG. 7, the voltage value of the reference voltage (VREF) is divided into 1024 stages from the voltage value of the power supply voltage (VDD) to the voltage value half of the power supply voltage (VDD). One of the voltage values.

  The reference voltage (VREF) is input to the non-inverting input terminal of the amplifier AMP1. The output terminal of the amplifier AMP1 is connected to the inverting input terminal of the amplifier AMP1, and the amplifier AMP1 functions as a voltage follower circuit. Therefore, the voltage value of the first power supply voltage (PD1) output from the output terminal of the amplifier AMP1 is the voltage value of the reference voltage (VREF).

  Based on the logical value included in the voltage switching signal (CV), the regulator circuit 9 applies any one of the voltage dividing points divided by the resistor element R1024 from the resistor element R1 to the non-inverting input terminal of the amplifier AMP1. Connect with. As a result, the first reference voltage (PD1) is varied and output.

  The operation of the first embodiment will be described with reference to FIGS.

  Here, for convenience of explanation, it is assumed that the voltage value of the power supply voltage (VDD) is 1.2V. However, the operation of the first embodiment is not limited to this. Further, for the sake of easy understanding, it is assumed that the voltage value of the first power supply voltage (PD1) fluctuates to a voltage value 0.6V which is half of 1.2V which is the voltage value of the power supply voltage (VDD).

  FIG. 8 is a waveform diagram showing each signal in the power supply control circuit 301 when the first power supply voltage (PD1) fluctuates. In FIG. 8, the logical value of the target voltage setting signal (TG) and the logical value of the voltage switching signal (CV) are expressed in decimal notation. FIG. 9 is a flowchart showing the operation of the first embodiment when the voltage value of the first power supply voltage (PD1) varies from 1.2V to 0.6V.

  In an initial state (T1 in FIG. 8) before changing the first power supply voltage (PD1), the first power supply voltage (PD1) is the same value as the power supply voltage (VDD). In this state, the logical value of the target voltage setting signal (TG) is 0000000000000, and the logical value of the voltage switching signal (CV) is also 0000000000000.

  The logical value of the target voltage setting signal (TG) and the logical value of the voltage switching signal (CV) are the same. Therefore, in each of the negative exclusive OR circuits ENOR1 to ENOR10 in the comparison circuit 8, the logic levels of the signals input to one input terminal and the other input terminal are the same. Each negative exclusive OR circuit ENOR1 to ENOR10 outputs a high level, and the comparison result signal (CMP) is maintained at a high level.

  An external controller (not shown) changes the logical value of the target voltage setting signal (TG) at the timing (T2 in FIG. 8) when the clock signal (CLK) transitions to the high level (S1 in FIG. 9). Here, the number is changed from 0000000000000 to 1111111111. This 1111111111 is a logical value for changing the first power supply voltage (PD1) to 0.6V.

  Here, the correspondence between the logical value of the target voltage setting signal (TG) and the first power supply voltage (PD1) is shown in FIG. The logical value 0000000000000 of the target voltage setting signal (TG) corresponds to 1.2V of the first power supply voltage (PD1). Every time 1 is added to the target voltage setting signal (TG) from the target voltage setting signal (TG) from 000000000000, the voltage value of the first power supply voltage (PD1) decreases from 1.2V to about 0.0006V.

  A target voltage setting signal (TG) changed by an external controller (not shown) is input to the power supply control circuit 301. The power supply control circuit 301 does not immediately change the voltage switching signal (CV) even if the target voltage setting signal (TG) is changed, and executes a voltage value changing sequence according to the processing of FIG. By changing the logical value of the target voltage setting signal (TG) (S1 in FIG. 9), a difference occurs between the logical value of the target voltage setting signal (TG) and the logical value of the voltage switching signal (CV). In each of the negative exclusive OR circuits ENOR1 to ENOR10 in the comparison circuit 8, a difference occurs in the logic level of the signal input to one input terminal and the other input terminal. When each of the exclusive exclusive OR circuits ENOR1 to ENOR10 outputs a low level, the comparison result signal (CMP) transitions to a low level.

  When the external controller detects the low level transition of the comparison result signal (CMP), the switching signal (UPDN) transitions to the low level at the timing (T3 in FIG. 8) when the clock signal (CLK) transitions to the high level. (S2 in FIG. 9). This low level signal is input to the power supply control circuit 301. Then, at the timing when the clock signal (CLK) transitions to the high level (T4 in FIG. 8), the enable signal (EN) transitions to the high level (S3 in FIG. 9). This high level signal is input to the power supply control circuit 301.

  While the operations from the processing (S1 in FIG. 9) to the processing (S3 in FIG. 9) are being performed, the phase comparison circuit 5 also includes the first clock signal (CK1) and the second clock signal (CK2). And the phase comparison result signals (CKA1) and (CKA2) are output. When the phase difference between the first clock signal (CK1) and the second clock signal (CK2) substantially matches, both the phase comparison result signals (CKA1) and (CKA2) are output as a low level. In this state, when the second clock signal (CK2) transits to a high level, the voltage change permission signal (PCEN) transits to a high level. In FIG. 8, the phase difference coincidence comparison between the first clock signal (CK1) and the second clock signal (CK2) is performed in an initial state (before T1 in FIG. 8) before the first power supply voltage (PD1) is changed. The voltage change permission signal (PCEN) is maintained at a high level.

  When the voltage change permission signal (PCEN) is maintained at a high level (S4: YES in FIG. 9), when the clock signal (CLK) transits to a high level, the latch circuit LATCH has a high level voltage change permission signal. (PCEN) is latched. The latch circuit LATCH outputs a high level signal. The high level output by the latch circuit LATCH continues until the voltage change permission signal (PCEN) transitions to the low level.

  When the latch circuit LATCH outputs a high level and the clock signal (CLK) is input to the OR circuit AND1, a 1-clock counter clock signal (CCK) is output (S5 in FIG. 9).

  1 is added to the voltage switching signal (CV) at the timing when the one-clock counter clock signal (CCK) transitions to the high level (T5 in FIG. 8) (S6 in FIG. 9). The addition of 1 means, for example, that the logical value of the voltage switching signal (CV) is changed from 0000000000000 to 0000000001.

  When 1 is added to the voltage switching signal (CV) (S6 in FIG. 9), the conduction / non-conduction state of each switch element SW1 to SW1024 is switched accordingly. For example, when the logical value of the voltage switching signal (CV) becomes from 000000000000 to 0000000001, the switch element SW2 is conductive and the switch element SW2 is conductive from the state where the switch element SW1 is conductive and the other switch elements SW2 to SW1024 are nonconductive. The other switch elements SW1 to SW1024 except for are in a non-conductive state.

  Thereby, the voltage value of the reference voltage (VREF) decreases. Further, since the voltage value of the reference voltage (VREF) and the voltage value of the first power supply voltage (PD1) are the same value, the voltage value of the first power supply voltage (PD1) also decreases. The decreasing voltage value is a voltage value obtained by dividing half of the voltage value of the power supply voltage (VDD) by 1023 (S7 in FIG. 9).

  The logical value of the target voltage setting signal (TG) and the logical value of the voltage switching signal (CV) are compared (S8 in FIG. 9), and if they do not match (S8: NO in FIG. 9), the processing (FIG. Returning to S4 in 9, the process is repeated until they match (S8 in FIG. 9: YES).

  In FIG. 11, a switch element (any one of SW1 to SW1024) and a switch element (any one of SW1 to SW1024) that conducts in accordance with the logical value of the voltage switching signal (CV). The relationship with the voltage value of the 1st power supply voltage (PD1) output by energizing is shown.

  The operations from the process (S5 in FIG. 9) to the process (S7 in FIG. 9) are performed within one cycle of the counter clock signal (CCK). Further, the operation from the process (S5 in FIG. 9) to the process (S7 in FIG. 9) is such that the voltage change permission signal (PCEN) is output at a low level (T6 in FIG. 8) (in FIG. 9). Repeat until S4: NO). If the phase difference between the first clock signal (CK1) and the second clock signal (CK2) does not substantially match, one of the phase comparison result signals (CKA1) and (CKA2) is output as a high level. . In this state, when the second clock signal (CK2) input to the D-type flip-flop circuit DFF transitions to a high level, the voltage change permission signal (PCEN) transitions to a low level (T6 in FIG. 8) (FIG. 8). S4 in 9: NO).

  If the voltage change permission signal (PCEN) is at a low level, the sequence for changing the voltage value of the first power supply voltage (PD1) is interrupted (S4 in FIG. 9: NO). In this case, it can be said that the phase difference between the first clock signal (CK1) and the second clock signal (CK2) does not substantially match. The sequence of changing the voltage value of the first power supply voltage (PD1) is stopped to prevent a situation where data (DATA) cannot be transferred from the flip-flop circuit 60 to the flip-flop circuit 65.

  When the voltage change enable signal (PCEN) is maintained at a low level, when the clock signal (CLK) transits to a high level, the low level voltage change enable signal (PCEN) is latched in the latch circuit LATCH. The latch circuit LATCH outputs a low level signal. The low level output by the latch circuit LATCH continues until the voltage change permission signal (PCEN) transits to the high level.

  When the latch circuit LATCH outputs a low level, the process (S5 in FIG. 9) to the process (S7 in FIG. 9) are not performed. This is because in a state where the latch circuit LATCH outputs a low level, the counter clock signal (CCK) is maintained at a low level regardless of the transition of the logic level of the clock signal (CLK). is there.

  When the voltage change enable signal (PCEN) transits to a high level and the counter clock signal (CCK) transits to a high level (T7 in FIG. 8) (S4: YES in FIG. 9), processing (in FIG. 9) The processing (S7 in FIG. 9) starts again from S5).

  From the process (S5 in FIG. 9) to the process (S7 in FIG. 9), on the condition that the voltage change permission signal (PCEN) is at a high level (S4: YES in FIG. 9), the target voltage setting signal It continues until the logical value of (TG) becomes the same as the logical value of the voltage switching signal (CV).

  When the logical value of the target voltage setting signal (TG) becomes the same as the logical value of the voltage switching signal (CV) (T8 in FIG. 8) (S8: YES in FIG. 9), the AND circuit AND2 outputs a comparison result signal. (CMP) is output at a high level. The external controller changes the enable signal (EN) to low level in response to the comparison result signal (CMP) changing to high level. When the enable signal (EN) becomes low level, the power supply control circuit 301 stops the voltage fluctuation of the first power supply voltage (PD1).

  The effect of the first embodiment will be described.

  When the first power supply voltage (PD1) of the multi-power supply system 101 having the first circuit block 20 and the second circuit block 31 fluctuates, the phase comparison circuit 5 generates the first clock signal (CK1) and the second clock signal. Compare the phase with (CK2). If the phase comparison circuit 5 determines that the phase of the first clock signal (CK1) and the phase of the second clock signal (CK2) match, the voltage change permission circuit 1 determines that the voltage change permission signal (PCEN) Is output at a high level. When the voltage change permission signal (PCEN) is maintained at a high level, the power supply control circuit 301 varies the first power supply voltage (PD1). The fluctuation sequence of the first power supply voltage (PD1) is performed in stages. This continues while the phase of the first clock signal (CK1) and the phase of the second clock signal (CK2) are considered to match by the comparison circuit 5.

  While the state in which the phase of the first clock signal (CK1) and the phase of the second clock signal (CK2) substantially match is maintained, the voltage value of the first power supply voltage (PD1) is changed stepwise. Done. Accordingly, the voltage value of the first power supply voltage (PD1) changes sharply and the phase difference between the first clock signal (CK1) and the second clock signal (CK2) increases, and the flip-flop circuit 60 and the flip-flop circuit 65 It is possible to prevent a situation in which data cannot be exchanged.

  The first clock signal (CK1) and the second clock signal (CK2) can operate in synchronization even during the change sequence in which the voltage value of the first power supply voltage (PD1) is dynamically changed. Even during fluctuations in the power supply voltage, data can be transferred between the flip-flop circuit 60 and the flip-flop circuit 65.

  If the phase comparison circuit 5 determines that the phase of the first clock signal (CK1) and the phase of the second clock signal (CK2) do not match, the voltage change permission circuit 1 determines that the voltage change permission signal (PCEN) To the low level. When the voltage change permission signal (PCEN) is maintained at the low level, the power supply control circuit 301 stops the fluctuation of the first power supply voltage (PD1). Then, the current voltage value of the first power supply voltage (PD1) is maintained until the voltage change permission signal (PCEN) transitions to a high level next time.

  When the voltage change permission signal (PCEN) is at a low level, the change sequence of the first power supply voltage (PD1) is interrupted. As a result, it is possible to prevent the voltage value of the first power supply voltage (PD1) from fluctuating rapidly and increase the phase difference between the first clock signal (CK1) and the second clock signal (CK2). it can. Since the transition to the low level of the voltage change enable signal (PCEN) is performed when the phase difference between the first clock signal (CK1) and the second clock signal (CK2) exceeds the allowable value, the first clock signal Variations in the first power supply voltage (PD1) such that the phase difference between (CK1) and the second clock signal (CK2) exceeds an allowable value can be suppressed.

  Even when the voltage fluctuation of the first power supply voltage (PD1) is interrupted, the phase difference between the first clock signal (CK1) and the second clock signal (CK2) is adjusted. If the phase difference comparison circuit 5 again determines that the phases of the first clock signal (CK1) and the second clock signal (CK2) match, the voltage change permission circuit 1 causes the voltage change permission signal to be (PCEN) transits to a high level. When the voltage change permission signal (PCEN) is maintained at a high level, the power supply control circuit 301 changes the first power supply voltage (PD1).

  When a phase difference occurs between the first clock signal (CK1) and the second clock signal (CK2), the fluctuation of the first power supply voltage (PD1) is interrupted. That is, a change sequence in which the voltage value of the first power supply voltage (PD1) fluctuates dynamically within an allowable range in which the phases of the first clock signal (CK1) and the second clock signal (CK2) substantially coincide with each other. To do. Even during the period in which the voltage value of the first power supply voltage (PD1) is dynamically changed, the phase difference between the first clock signal (CK1) and the second clock signal (CK2) is maintained within a certain range. .

  Here, the range of the phase difference maintained constant is a range in which data (DATA) between the flip-flop circuit 60 and the flip-flop circuit 65 can be transferred.

  A second embodiment will be described. The second embodiment includes a voltage change permission circuit 2 instead of the voltage change permission circuit 1 in the first embodiment. In the following description, the voltage change permission circuit 2 will be described.

  The voltage change permission circuit 2 will be described with reference to FIG. FIG. 12 is an example of the voltage change permission circuit 2 as a whole.

  The phase comparison result signal (CKA1) is input to one terminal of the NOR circuit NOR2. The phase comparison result signal (CKA2) is input to the other terminal of the NOR circuit NOR2. The output terminal of the NOR circuit NOR2 is connected to the input terminal D2 of the D-type flip-flop circuit DFF2.

  The second clock signal (CK2) is input to the clock input terminal N2 of the D-type flip-flop circuit DFF2. The D-type flip-flop circuit DFF2 operates in synchronization with the second clock signal (CK2). The output terminal Q2 of the D-type flip-flop circuit DFF2 is connected to the input terminal D3 of the D-type flip-flop circuit DFF3.

  The second clock signal (CK2) is input to the clock input terminal N3 of the D-type flip-flop circuit DFF3. The D-type flip-flop circuit DFF3 operates in synchronization with the second clock signal (CK2). The output terminal Q3 of the D-type flip-flop circuit DFF3 is connected to the input terminal D4 of the D-type flip-flop circuit DFF4.

  The second clock signal (CK2) is input to the clock input terminal N4 of the D-type flip-flop circuit DFF4. The D-type flip-flop circuit DFF4 operates in synchronization with the second clock signal (CK2).

  The output terminal Q2 of the D-type flip-flop circuit DFF2, the output terminal Q3 of the D-type flip-flop circuit DFF3, and the output terminal Q4 of the D-type flip-flop circuit DFF4 are connected to each input terminal of the AND circuit AND3. In the second embodiment, the signal output from the output terminal of the AND circuit AND3 is the voltage change permission signal (PCEN).

  The operation of the voltage change permission circuit 2 will be described.

  When the phase comparison result signals (CKA1) and (CKA2) are both at a low level and the second clock signal (CK2) transits from a low level to a high level, a high level signal output from the NOR circuit NOR2 is: The data is taken into the D-type flip-flop circuit DFF2. As a result, a high level signal is output from the output terminal Q2 of the D-type flip-flop circuit DFF2.

  When the second clock signal (CK2) transits from the low level to the high level again while the phase comparison result signals (CKA1) and (CKA2) are both kept at the low level, the output from the negative OR circuit NOR2 The high-level signal to be output is input to the D-type flip-flop circuit DFF2, and the high-level signal output from the output terminal Q2 of the D-type flip-flop circuit DFF2 is input to the D-type flip-flop circuit DFF3. Accordingly, a high level signal is output from the output terminal Q2 of the D-type flip-flop circuit DFF2 and the output terminal Q3 of the D-type flip-flop circuit DFF3.

  Further, when both the phase comparison result signals (CKA1) and (CKA2) continue to be in the low level state and the second clock signal (CK2) transits from the low level to the high level again, it is output from the negative OR circuit NOR2. The high level signal output from the output terminal Q2 of the D flip flop circuit DFF2 is output from the output terminal Q3 of the D flip flop circuit DFF3. The output high level signal is taken into the D-type flip-flop circuit DFF4. Accordingly, a high level signal is output from the output terminal Q2 of the D-type flip-flop circuit DFF2, the output terminal Q3 of the D-type flip-flop circuit DFF3, and the output terminal Q4 of the D-type flip-flop circuit DFF4.

  When a high level signal is output from the output terminal Q2 of the D-type flip-flop circuit DFF2, the output terminal Q3 of the D-type flip-flop circuit DFF3, and the output terminal Q4 of the D-type flip-flop circuit DFF4, the voltage change permission signal (PCEN) Is output at a high level. In other words, when the phase comparison result signals (CKA1) and (CKA2) are both in the low level state for 3 cycles of the second clock signal (CK2), the voltage change enable signal (PCEN) transits to the high level. To do.

  The effect of the voltage change permission circuit 2 will be described.

  When the phase comparison result signals (CKA1) and (CKA2) are both kept at the low level for the second clock signal (CK2) for 3 cycles, the voltage change permission signal (PCEN) transits to the high level. . That is, the state in which the phase difference between the first clock signal (CK1) and the second clock signal (CK2) substantially coincides with the second clock signal (CK2) being in a period of 3 cycles stably. Can be detected. During such a stable period, a high level signal can be output as the voltage change permission signal (PCEN), and the voltage value change sequence of the first power supply voltage (PD1) can be executed. The voltage value of the first power supply voltage (PD1) can be changed while ensuring the synchronization between the first clock signal (CK1) and the second clock signal (CK2).

  Here, the first power supply voltage (PD1) and the second power supply voltage (PD2) are examples of the power supply voltage in the claims. The power supply control circuit 301 is an example of a power supply control circuit in the claims. The voltage change permission signal (PCEN) is an example of a voltage change permission signal in the claims. The first clock signal (CK1) and the second clock signal (CK2) are examples of clock signals supplied to each of the claims. The phase comparison circuit 5 is an example of a phase comparison circuit in the claims. The voltage change permission circuits 1 and 2 are examples of the voltage change permission circuit in the claims. The multi-power supply system 101 is an example of a multi-power supply system in the claims. The D-type flip-flop circuits DFF2 to DFF4 are examples of a plurality of flip-flop circuits. The AND circuit AND3 is an example of a gate circuit in the claims. The semiconductor integrated circuit 201 is an example of a semiconductor integrated circuit and a multi-power supply operating device.

  The present invention is not limited to the above-described embodiment, and it goes without saying that various improvements and modifications can be made without departing from the spirit of the present invention. For example, in the operation of the first embodiment disclosed in the present application, only the case where the voltage value of the first power supply voltage (PD1) decreases has been described. However, the present application is not limited to this case. A similar effect can be obtained when the voltage value of the first power supply voltage (PD1) increases. When the first power supply voltage (PD1) increases, the voltage switching signal (UPDN) becomes high level. In addition, it goes without saying that the present invention can be similarly applied when the voltage value of the second power supply voltage (PD2) dynamically changes instead of or together with the first power supply voltage (PD1). Yes.

  According to the embodiment described above, a multi-power supply system and a semiconductor integrated circuit that enable a synchronous operation between circuit blocks by adjusting a power supply voltage change sequence even when a power supply voltage is dynamically changed. Can be provided.

DESCRIPTION OF SYMBOLS 1 Voltage change permission circuit of 1st Embodiment 2 Voltage change permission circuit of 2nd Embodiment 5 Phase comparison circuit 85 Control circuit 101 Multiple power supply system 201 Semiconductor integrated circuit 301 Power supply control circuit AND1, AND2, AND3 AND circuit DFF1, DFF2 , DFF3, DFF4 D-type flip-flop circuit (CK1) First clock signal (CK2) Second clock signal (PCEN) Voltage change enable signal (PD1) First power supply voltage (PD2) Second power supply voltage

Claims (5)

A plurality of circuit blocks to which different power supply voltages are supplied;
A power supply control circuit that supplies the different power supply voltages to the plurality of circuit blocks, respectively, and controls the power supply voltages of the different power supply voltages;
A phase comparison circuit for comparing phases of clock signals supplied to each of the plurality of circuit blocks;
A voltage change circuit that outputs a voltage change signal for controlling the change of the power supply voltage to the power supply control circuit according to a detection result of a phase difference between the clock signals by the phase comparison circuit;
The power supply control circuit changes in accordance with a change in the first power supply voltage when the voltage value of one of the power supply voltages is changed from a first voltage value to a second voltage value. In response to the voltage change signal that changes based on a clock signal, the first power supply voltage is changed stepwise from the first voltage value to the second voltage value ,
While the power supply control circuit changes the first power supply voltage stepwise from the first voltage value to the second voltage value, the voltage change circuit has a phase difference between the clock signals equal to or greater than a predetermined value. When the phase comparison circuit detects this, the voltage change signal for stopping the change of the first power supply voltage is output, and the predetermined value after the voltage change signal for stopping the change of the first power supply voltage is output. When the phase comparison circuit detects that the phase difference between the clock signals is smaller than the predetermined value after the period has elapsed, the voltage change signal for restarting the change of the first power supply voltage is output. Multi power supply system.   The power supply control circuit sets the first power supply voltage to the first voltage value and the second voltage according to the first level voltage change signal output when a phase difference between the clock signals is greater than or equal to a predetermined value. The multi-power supply system according to claim 1, wherein a voltage value between the voltage values is held.   The voltage change circuit outputs the voltage change signal at a second level different from the first level in response to a phase difference between the clock signals continuously matching for a predetermined period. Multi-power supply system as described in. The phase comparison circuit is
A clock signal output from a first buffer in the circuit block to which the first power supply voltage is supplied and a second buffer in the circuit block to which a power supply voltage different from the first power supply voltage is supplied. The multi-power supply system according to any one of claims 1 to 3, wherein a phase with a clock signal is compared. A plurality of circuit blocks to which different power supply voltages are supplied;
A power supply control circuit that supplies the different power supply voltages to the plurality of circuit blocks, respectively, and controls the power supply voltages of the different power supply voltages;
A phase comparison circuit for comparing phases of clock signals supplied to each of the plurality of circuit blocks;
A voltage change circuit that outputs a voltage change signal for controlling the change of the power supply voltage to the power supply control circuit according to a detection result of a phase difference between the clock signals by the phase comparison circuit;
The power supply control circuit changes in accordance with a change in the first power supply voltage when the voltage value of one of the power supply voltages is changed from a first voltage value to a second voltage value. In response to the voltage change signal that changes based on a clock signal, the first power supply voltage is changed stepwise from the first voltage value to the second voltage value ,
While the power supply control circuit changes the first power supply voltage stepwise from the first voltage value to the second voltage value, the voltage change circuit has a phase difference between the clock signals equal to or greater than a predetermined value. When the phase comparison circuit detects this, the voltage change signal for stopping the change of the first power supply voltage is output, and the predetermined value after the voltage change signal for stopping the change of the first power supply voltage is output. When the phase comparison circuit detects that the phase difference between the clock signals is smaller than the predetermined value after the period has elapsed, the voltage change signal for restarting the change of the first power supply voltage is output. A semiconductor integrated circuit.

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