KR20020008449A - Phase locked loop for improving jitter characteristics - Google Patents

Abstract

PURPOSE: A phase locked loop is provided to improve a jitter property and to reduce static current consumption, by optimizing a delay time according to an operating state of a switch. CONSTITUTION: A phase frequency detector(101) outputs an error signal by comparing the phase and frequency of an input signal with the phase and frequency of an input signal of an output signal of a voltage controlled oscillator. A charge pump(102) charges or discharges a capacitor of a loop filter according to the error signal. The voltage controlled oscillator(108) is oscillated by a voltage generated through charging/discharging of the capacitor and outputs a signal having a frequency. The phase frequency detector(101) includes the first and second D flip-flops(103, 104), an AND gate(106), a switch operation detector(202), and a variable delay portion(201). The first D flip-flop(103) receives an input signal via a clock terminal(CLK1) and a power supply voltage via a data input terminal(D1). The second D flip-flop(104) receives an output signal of the oscillator(108) via a clock terminal(CLK2) and the power supply voltage via a data input terminal(D2). The AND gate(106) compares phases of output signals of the flip-flops(103, 104). The switch operation detector(202) senses an operating state of a switch in th charge pump and detects a pulse width where the switch is normally operated. The variable delay portion(201) adjusts a delay value according to an output of the AND gate and the pulse width detected by the detector(202) and supplies the adjusted delay value to reset terminals(RESET) of the flip-flops(103, 104).

Description

PHASE LOCKED LOOP FOR IMPROVING JITTER CHARACTERISTICS}

The present invention is directed to characterizing the jitter characteristics of a phase locked loop, and more particularly, to a phase locked loop having improved jitter characteristics to reduce power consumption and improve jitter characteristics in a phase locked state. will be.

1 is a diagram illustrating an example of a conventional phase locked loop. As shown therein, a phase frequency detector 101 for comparing a phase and a frequency of an input signal and an output signal of a voltage controlled oscillator and outputting an error signal according thereto; In accordance with the error signal output from the phase frequency detector 101, a charge pump 102 for supplying the necessary current by performing a pull-up or pull-down operation, and in the charge pump 102 The loop filter 107 is charged and discharged by the output current to generate a voltage, and the control oscillator 108 is oscillated according to the voltage generated by the loop filter 107 to output a signal having a constant frequency.

The phase frequency detector 101 receives the input signal through the clock terminal CLK1 and outputs a power supply voltage to the data input terminal D1 according to the clock through the output terminal Q1. 103 and an output signal of the voltage controlled oscillator 108 to the second clock terminal CLK2 and outputs a power supply voltage to the data input terminal D2 according to the clock through the output terminal Q2. Outputs a high signal when the phases of the two deflip flops 104 and the first and second deflip flops 103 and 104 are the same, and outputs a low signal when the phases of the two signals are different. A delay unit for delaying the AND gate 106 and the signal output from the AND gate 106 by a predetermined time, and providing the AND gate 106 to the reset terminal RESET of the first and second dip-flops 103 and 104. It consists of 105.

Looking at the conventional technology configured as described above is as follows.

When the input signal and the output signal from the voltage controlled oscillator 108 are input to the phase frequency detector 101, respectively, the phase and frequency of the two signals are detected and the error signal according to the difference in the phase and frequency is charged in the pump 102 )

Then, the charge pump 102 performs a pull-up or pull-down operation by the pull-up switch S1 and the pull-down switch S2 to charge / discharge the current of the capacitor of the loop filter 107. do. That is, when the high signal is input to the pull-up switch S1 and the low signal is input to the pull-down switch S2, the current from the current source I1 is charged to the capacitor of the loop filter 107, and to the pull-up switch S1. When the low signal is input and the high signal is input to the pull-down switch S2, current flows to the ground side through the current source I2, so that the current charged in the capacitor of the loop filter 107 is the pull-down switch S2 → It is discharged to the ground side through the current source I2.

When the voltage generated while the loop filter 107 is charged and discharged is transferred to the voltage controlled oscillator 108, the voltage controlled oscillator 108 performs an oscillation operation to output a signal having a constant frequency. It is fed back to the phase frequency detector 101 to compare the input signal with phase and frequency again.

This operation is repeated until the phase and frequency of the input signal and the voltage controlled oscillator 108 match. The state where the phase and frequency of the two signals coincide is called a phase lock state.

As described above, the operation of the phase frequency detector 101 for detecting and comparing the phase and the frequency until the phase locked state is as follows.

When the input signal is input to the phase frequency detector 101, the first deflip-flop 103 receives the input signal through the clock terminal CLK1, and matches the clock input terminal with the signal received by the clock terminal CLK1. D1) receives the power supply voltage and outputs it to the output terminal Q1.

When the first flip-flop 103 is operated, the second flip-flop 104 receives a signal output from the voltage controlled oscillator 108 through its clock terminal CLK2, and inputs it to the clock terminal CLK2. The power supply voltage is received at the clock input terminal D2 and output to the output terminal Q2 in accordance with the received signal.

The output signal is transmitted to the charge pump 102 and input to the AND gate 106.

That is, the output signal of the first deflip-flop 103 and the output signal of the second deflip-flop 104 are received by the AND gate 106 and output to the delay unit 105. ) Outputs a low signal when the output signal of the first deflip-flop 103 and the output signal of the second deflip-flop 104 do not coincide with each other, and outputs a low signal. When the output signal of and the phase and the frequency of the output signal of the second flip-flop 104 is the same and outputs a high signal to the delay unit 105.

Then, when the low signal is inputted from the AND gate 106, the delay unit 105 does not reset the first and second dip-flop 103 and the second de-flop flop 104. The phase and frequency of the output signal of 108 are detected, and an error signal corresponding to the phase and frequency difference is outputted to the charge pump 102. When the high signal is input from the AND gate 106, the delay unit 105 delays the predetermined time and then signals the first and second flip-flop 103 and the second flip-flop 104 to the reset terminal RESET. To provide a reset.

Because, when the phase and the frequency of the two signals output from the first deflip-flop 103 and the second deflip-flop 104 is in phase locked state, the output pulse width of the phase frequency detector 101 is inputted. It appears as narrow as the static phase error signal between the signal and the output signal of the voltage controlled oscillator 108. If the narrow pulse width is so narrow that the switches S1 and S2 of the charge pump 102 cannot be turned on, a dead zone problem occurs.

To solve this problem, the delay unit 105 is delayed by a predetermined delay value, and then the first deflip-flop 103 and the second deflip-flop 104 are reset to output the pulse width output from the phase frequency detector 101. To adjust.

However, in the prior art as described above, the phase frequency detector to solve the dead zone (DEAD ZONE) problem that the output signal width of the phase frequency detector in the phase locked state is too narrow to prevent the normal operation of the charge pump switch A delay element with a constant delay value was added to the reset path of. When deciding the value of this additional delay element, the design of having MARGIN to ensure that the charge pump operates normally regardless of process variation or temperature variation, pull-up and pull-down in the charge pump As the switch turns on at the same time, the jitter is not only worsened but also a current path is formed from the source current to the sink current, thereby causing unnecessary STATIC current consumption. There is this.

Therefore, an object of the present invention for solving the conventional problems as described above is to provide a circuit for detecting the operation state of the charge pump switch, and optimize the delay time according to the operation state of the switch to be detected through the circuit unnecessary charge pump It provides a phase locked loop with improved jitter that reduces the consumption of STATIC CURRENT and at the same time improves jitter.

1 is an embodiment of a conventional phase locked loop.

2 is an embodiment of a phase locked loop that improves the jitter characteristic of the present invention.

3 is a flowchart illustrating a delay value detection according to a switch operation in FIG. 2.

4 is a detail view of a switch motion detector in FIG. 2;

***** Explanation of symbols for the main parts of the drawing *****

101: phase frequency detector 102: charge pump

103: first flip-flop 104: second flip-flop

106: AND gate 107: loop filter

108: voltage controlled oscillator 201: variable delay unit

202: switch motion detector

The present invention for achieving the above object in the phase locked loop consisting of a phase frequency detector, a charge pump, a loop filter and a full control oscillator, the phase frequency detector receives an input signal as a clock terminal to the clock; The first deflip-flop outputs the power supply voltage input to the data input terminal through the output terminal, and the output voltage of the voltage controlled oscillator is input to the second clock terminal according to the clock and the power supply voltage input to the data input terminal according to the clock. Compares the phases of the signals output from the first and second deflip flops, and outputs the comparison values, and outputs the comparison value, and an operating state of the switch in the charge pump. A switch operation detector which senses a pulse width at which the switch operates properly, and a comparison output from the end gate And after adjusting the delay in accordance with the switch operating pulse width detected by the motion detector switch characterized by including parts of the variable delay provided to the reset terminals of the first and second D flip-flop.

Hereinafter, described in detail with reference to the accompanying drawings.

FIG. 2 is a diagram illustrating an embodiment of a phase locked loop having an improved jitter characteristic according to an embodiment of the present invention. As shown in FIG. 2, a phase comparing a phase and a frequency of an input signal and an output signal of a voltage controlled oscillator and outputting an error signal accordingly is shown. A frequency detector 101, a charge pump 102 for charging and discharging a current in a capacitor of a loop filter according to the error signal, and a controlled oscillator for oscillating according to a voltage generated during charging and discharging to output a signal having a constant frequency In the phase locked loop composed of 108, the phase frequency detector 101 receives an input signal through the clock terminal CLK1 and outputs a power supply voltage input to the data input terminal D1 in accordance with the clock. The first deflip-flop 103 and the output signal of the voltage controlled oscillator 108 are input to the second clock terminal CLK2 and are input to the data input terminal D2 according to the clock. Compares the phases of the signals output from the second and second dip-flop 104 and the first and second dip-flop 103 and 104 outputting the power supply voltage through the output terminal Q2. An AND gate 106 for outputting a value, a switch operation detector 202 for detecting a pulse width at which the switch operates by sensing an operation state of the switch in the charge pump 102, and the AND gate 106 After adjusting the delay value according to the comparison value output from the switch operation pulse width detected by the switch operation detector 202 to the reset terminal (RESET) of the first and second dip-flop 103 (104) The variable delay unit 201 is provided.

As shown in FIG. 4, the switch operation detector 202 includes a delay unit 301 for delaying and outputting an input signal by a predetermined time, and an exclusive NOR between the value and the input signal through the delay unit 301. Exclusive Noring 302 for outputting a pulse generated by the ring (exclusive noring), and on or off in accordance with the output of the Exclusive Noagate 302 to avoid charging and discharging to the series-connected capacitor 304 A MOS transistor 303 and a controller 305 which obtains a pulse width at which the PMOS transistor 303 operates according to a voltage generated during charge / discharge of the capacitor 304 and transmits the pulse width to the delay unit 301. do.

Referring to the operation and effect of the present invention configured as described in detail as follows.

When the input signal and the output signal from the voltage controlled oscillator 108 are respectively input to the phase frequency detector 101, the first deflip-flop 103 of the phase frequency detector 101 outputs the input signal to the clock terminal CLK1. The power supply voltage is received at the clock input terminal D1 in accordance with the signal received by the clock terminal CLK1, and output to the output terminal Q1.

As described above, when the first flip-flop 103 is operated, the second flip-flop 104 receives a signal output from the voltage controlled oscillator 108 through its clock terminal CLK2, and the clock terminal CLK2. In accordance with the signal input to the clock input terminal (D2) receives the power supply voltage and outputs to the output terminal (Q2).

That is, the first and second flip-flops 103 and 104 detect the phase and frequency of the signal output from the input signal and the voltage controlled oscillator and occupy an error signal according to the difference in the phase and frequency. Output to the pump 102 and the end gate 106, respectively.

Then, the charge pump 102 performs a pull-up or pull-down operation by the pull-up switch S1 and the pull-down switch S2 to charge / discharge the current of the capacitor of the loop filter 107. do. That is, when the high signal is input to the pull-up switch S1 and the low signal is input to the pull-down switch S2, the current from the current source I1 is charged to the capacitor of the loop filter 107, and to the pull-up switch S1. When the low signal is input and the high signal is input to the pull-down switch S2, current flows to the ground side through the current source I2, so that the current charged in the capacitor of the loop filter 107 is the pull-down switch S2 → Discharge to the ground side via current source I2.

When the voltage generated while the loop filter 107 is charged and discharged is transferred to the voltage controlled oscillator 108, the voltage controlled oscillator 108 performs an oscillation operation to output a signal having a constant frequency. It is fed back to the phase frequency detector 101 to compare the input signal with phase and frequency again.

This operation is repeated until the phase and frequency of the input signal and the voltage controlled oscillator 108 match. The state where the phase and frequency of the two signals coincide is called a phase lock state.

As described above, the AND gate 106 of the phase frequency detector 101 which detects and compares the phase and the frequency until the phase locked state is the first and second flip-flops 103 and 104 Receives and outputs the signal output from the output to the variable delay unit 201. That is, a high signal is outputted when the frequency and phase of the two signals output from the first and second flip-flops 103 and 104 are the same, and a low signal is outputted when the frequency and phase of the two signals are different. do.

At this time, the switch operation detector 202 detects a pulse width when the pull-up switch S1 or the pull-down switch S2 of the charge pump 102 operates properly. The operation of the switch operation detector 202 will be described with reference to FIGS. 3 and 4 as follows.

As shown in FIG. 2, an input signal applied to the phase frequency detector 101 is received by the delay unit 301 of the switch operation detector 202 shown in FIG. 4, and as shown in FIG. Value (D = 1). (Step S101 in Fig. 3)

Afterwards, the exclusive NOR gate 302 receives the delayed signal and the input signal through the delay unit 301 and performs exclusive NORing to transmit a signal having a pulse width equal to the delay value to the gate of the PMOS transistor 303. Output

When the PMOS transistor 303 is turned on, the capacitor 304 is charged with a predetermined voltage. Otherwise, the PMOS transistor 303 is turned off. The capacitor 304 is to maintain the initial state.

For example, when the capacitor 304 is charged with a predetermined voltage, the controller 305 means that the PMOS transistor 303 operates normally. Therefore, the controller 305 determines the delay value as the delay value in the reset path of the phase frequency detector 101. (S102), otherwise, the controller 305 controls the delay unit 301 to gradually increase the delay value so as to repeatedly operate until the capacitor 304 is charged with a predetermined voltage.

Accordingly, the variable delay unit 201 delays by the delay value provided by the control unit 305 of the switch operation detector 202 shown in FIG. 4, and then the first and second dip flip-flops 103 and 104. It is provided by RESET terminal of).

In this way, the delay value is varied to prevent the output pulse width of the phase frequency detector 101 from appearing very narrow due to the fixed delay value.

As described above, the optimized delay value is found and provided to the reset path of the phase frequency detector 101 to reduce the static current consumption in the phase lock state and to improve the jitter characteristic.

As described in detail above, the present invention provides a phase locked loop using a switch operation detector for detecting a pulse width of a switch in which a charge pump switch operates properly and a variable delay unit for changing a reset path of a phase frequency detector according to the pulse width. This prevents the charge pump switch from operating unnecessarily during phase lock, reducing electrostatic current consumption and improving jitter, making it ideal for all chips with high performance phase locked loops.

Claims (3)

Phase frequency detector 101 for comparing the phase and frequency of the input signal and the output signal of the voltage-controlled oscillator and outputting an error signal according thereto, and a charge pump 102 for charging and discharging current in the capacitor of the loop filter according to the error signal. And a control oscillator 108 oscillating according to the voltage generated at the time of charge / discharge and outputting a signal having a constant frequency, the phase frequency detector 101 outputs an input signal to a clock terminal CLK1. ) And the output signal of the voltage-controlled oscillator 108 and the first deflip flop 103 for outputting the power supply voltage inputted to the data input terminal D1 according to the clock through the output terminal Q1. A second flip-flop 104 for outputting a power supply voltage inputted to the clock terminal CLK2 to the data input terminal D2 in accordance with the clock through the output terminal Q2, and the first and second deflips; Flop (103) (104 A switch for detecting the pulse width at which the switch operates by detecting the operation state of the switch in the charge pump 102 and the AND gate 106 for comparing the phases of the signals output from the outputs and outputting the comparison value. After adjusting the delay value according to the operation detector 202 and the comparison value output from the AND gate 106 and the switch operation pulse width detected by the switch operation detector 202, the first and second dip-flops A phase locked loop with improved jitter characteristic, comprising a variable delay unit 201 provided as a reset terminal (RESET) of (103) (104). The switch operation detector 202 of claim 1, wherein the switch operation detector 202 includes: a delay unit 301 for delaying and outputting an input signal by a predetermined time, and an exclusive noring of the value and the input signal through the delay unit 301. The PMOS transistor 303 that charges and discharges an exclusive no-gate 302 for outputting a pulse generated by the step-by-step and a capacitor 304 connected on or off in accordance with the output of the exclusive no-gate 302. And a controller 305 which obtains a pulse width at which the PMOS transistor 303 operates according to the voltage generated during charging / discharging of the capacitor 304 and transmits the pulse width to the delay unit 301. Phase locked loop with improved jitter. 3. The phase locked loop as claimed in claim 2, wherein the delay unit (301) is initially set to the smallest value and gradually increased.