CN113612474B

CN113612474B - Anti-jitter high-speed frequency discriminator circuit

Info

Publication number: CN113612474B
Application number: CN202110836758.9A
Authority: CN
Inventors: 林海军; 杨骁�
Original assignee: Xiamen Xinshili Microelectronics Co ltd
Current assignee: Xiamen Xinshili Microelectronics Co ltd
Priority date: 2021-07-23
Filing date: 2021-07-23
Publication date: 2023-12-29
Anticipated expiration: 2041-07-23
Also published as: CN113612474A

Abstract

The invention provides an anti-jitter high-speed discriminator circuit, wherein Q1, Q2, Q3 and Q4 are respectively the normal phase outputs of four D flip-flops 1, 2, 3 and 4, and Q3B, Q B is the reverse phase output of a third D flip-flop and a fourth D flip-flop; q3 and Q3B are connected to two inputs of the first AND gate, and Q4B are connected to two inputs of the second AND gate; the first AND gate outputs an UP signal, and the second AND gate outputs a DOWN signal; the first input end of the second D trigger is connected with the oscillation output Do, and the second input end of the second D trigger is connected with the input data Di n through a delay module; the first input ends of the third D trigger and the fourth D trigger are respectively connected to Q1; the second input ends of the third D trigger and the fourth D trigger are respectively connected to Q2.

Description

Anti-jitter high-speed frequency discriminator circuit

Technical Field

The present invention relates to a high frequency analog integrated circuit design technology, and more particularly, to a frequency detection method applied to a high frequency phase-locked loop.

Background

The frequency discriminator circuit (Frequency Detector), together with the phase discriminator circuit (Phase Detector PD), generally forms the core of the analog and digital phase locked loop circuits, and is an important component of a high speed communication transceiver system. The method comprises the steps of sensing the edge of an output signal of an oscillating circuit in a phase-locked loop (PLL) feedback system, generating a pulse signal by detecting the time difference between the edge of the output signal of the oscillating circuit and the edge of a reference clock signal, and adjusting the oscillation starting frequency of the oscillating circuit by the width of the pulse signal to enable the oscillation starting frequency of the oscillating circuit to be identical to a certain multiple of the reference clock frequency. Thereby realizing frequency and phase locking of the phase-locked loop circuit. The overall circuit block diagram is shown in fig. 1, the input signal of the frequency discriminator is input data or reference clock signal Din and output signal Do of the voltage-controlled oscillation circuit, rising edge time difference between Din and Do signals is converted into pulse signals through the frequency discriminator, the signals control the charge pump to realize output and inflow of charges, voltage/current conversion is realized, and the signals are filtered and noise reduced through the low-pass filter and then used as control signals of the voltage-controlled oscillation circuit to regulate the frequency and the phase of Do. In a high-speed (20 Gbps) clock and data recovery circuit, when the input data Din contains large jitter, a detection error of the discriminator is caused, so that frequency locking cannot be achieved.

Disclosure of Invention

The invention aims to solve the main technical problem of providing an anti-jitter high-speed frequency discriminator circuit, which solves the problem that the input data Din contains a larger jitter frequency discriminator detection error and cannot be subjected to frequency locking.

In order to solve the technical problems, the invention provides an anti-jitter high-speed discriminator circuit, which consists of four D triggers, a delay circuit and 2 AND gates;

q1, Q2, Q3, Q4 are the normal phase outputs of the four D flip-flops 1, 2, 3, 4, respectively, and Q3B, Q B is the inverted output of the third D flip-flop and the fourth D flip-flop; q3 and Q3B are connected to two inputs of the first AND gate, and Q4B are connected to two inputs of the second AND gate; the first AND gate outputs an UP signal, and the second AND gate outputs a DOWN signal; the first input end of the second D trigger is connected with the oscillation output Do, and the second input end of the second D trigger is connected with the input data Din through a delay module; the first input ends of the third D trigger and the fourth D trigger are respectively connected to Q1; the second input ends of the third D trigger and the fourth D trigger are respectively connected to Q2;

when the frequency of the input data Din is higher than the frequency of the oscillation output Do, the UP signal is in a high level, the charge pump supplies current to the filter, the output voltage of the filter is increased, and the output frequency of the oscillation circuit is improved; when the frequency of the input data Din is lower than the frequency of the oscillation output Do, the DOWN signal is high, the filter supplies current to the charge pump, the output voltage of the filter is reduced, and the output frequency of the oscillation circuit is reduced.

In a preferred embodiment: the UP signal and the DOWN signal are not always in opposite states.

In a preferred embodiment: when the input data Din contains a large jitter, the UP signal and the DOWN signal are simultaneously in a low state.

Drawings

Fig. 1 is a block diagram of a PLL circuit including a phase detector and a frequency detector in the prior art;

fig. 2 is a circuit diagram of an anti-jitter high-speed discriminator according to the preferred embodiment of the invention;

FIG. 3 is a signal timing diagram of a preferred embodiment of the present invention, wherein a is a timing diagram of input data Din with larger jitter; b is a timing diagram in which the input data does not contain large jitter;

fig. 4 is a diagram showing simulation results of a preferred embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention; it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments, and that all other embodiments obtained by persons of ordinary skill in the art without making creative efforts based on the embodiments in the present invention are within the protection scope of the present invention.

In the description of the present invention, it should be noted that the positional or positional relationship indicated by the terms such as "upper", "lower", "inner", "outer", "top/bottom", etc. are based on the positional or positional relationship shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the apparatus or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present invention, unless explicitly specified and limited otherwise, the terms "mounted," configured to, "" engaged with, "" connected to, "and the like are to be construed broadly, and may be, for example," connected to, "wall-mounted," connected to, removably connected to, or integrally connected to, mechanically connected to, electrically connected to, directly connected to, or indirectly connected to, through an intermediary, and may be in communication with each other between two elements, as will be apparent to those of ordinary skill in the art, in view of the detailed description of the terms herein.

Referring to fig. 2, the present embodiment provides an anti-jitter high-speed discriminator circuit, which is composed of four D flip-flops, a delay circuit, 2 and gates;

After the design, taking the case that the frequency of the input data Din is higher than the frequency of the oscillation output Do as shown in fig. 3, when the rising edge and the falling edge of the input data Din both contain large jitter, the Q3 and the Q4B generate opposite signals to enable the UP and the DOWN signals to keep low level, and charge and discharge are not performed, so that erroneous judgment caused by jitter is avoided. When the rising edge and the falling edge of the input data Din have smaller jitter, Q3 and Q4B can perform relatively clear frequency discrimination, and UP and DOWN signals normally work. Fig. 4 is a simulation result of the inventive circuit.

The foregoing is only a preferred embodiment of the present invention, but the design concept of the present invention is not limited thereto, and any person skilled in the art will be able to make insubstantial modifications of the present invention within the scope of the present invention disclosed herein by this concept, which falls within the actions of invading the protection scope of the present invention.

Claims

1. An anti-jitter high-speed discriminator circuit, characterized in that: the device consists of four D triggers, a delay circuit and 2 AND gates;

2. An anti-jitter high speed discriminator circuit according to claim 1, wherein: the UP signal and the DOWN signal are not always in opposite states.

3. An anti-jitter high speed discriminator circuit according to claim 1, wherein: when the input data Din contains a large jitter, the UP signal and the DOWN signal are simultaneously in a low state.