CN103187971A - Lock detection circuit for charge pump phase locked loop frequency synthesizer - Google Patents
Lock detection circuit for charge pump phase locked loop frequency synthesizer Download PDFInfo
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Abstract
The invention discloses a lock detection circuit for a charge pump phase locked loop frequency synthesizer, which is characterized in that two input ends of an XOR gate are respectively connected with two output signals (UP and DOWN) of a phase frequency detector, an output end of the XOR gate is connected with an input end of a first NOT gate (NOT_1), an output end of the first NOT gate (NOT_1) is connected with a resistor (R), and the other end of the resistor (R) is connected with an input end of an inverted Schmitt trigger (IST); and a capacitor (C) is connected to the input end of the inverted Schmitt trigger in parallel, the other end of the capacitor is grounded (GND), an output end of the inverted Schmitt trigger is connected with a second NOT gate (NOT_2), an output end of the second NOT gate (NOT_2) is connected with a reset end (Reset) of a N-digit counter, an input end (IN) of the N-digit counter is connected with a feedback signal (FDIV) with frequency divided of a frequency divider, and an output (OUT) of the N-digit counter is an output signal LOCK of the lock detection circuit.
Description
Technical field
The present invention relates to a kind of charge pump phase lock loop frequency synthesizer lock detecting circuit, belong to the integrated circuit (IC) design field.
Background technology
The charge pump phase lock loop frequency synthesizer is the key modules of transceiver radio frequency front end chip, stable, programmable, low noise local oscillated signal can be provided for the transceiver of various criterion, and its performance determines or affects the performance of whole wireless transceiver system.Because its output signal has spectral purity height, operating frequency height, phase noise is low, low in energy consumption, be easy to therefore be widely used in academia and industrial circle in advantages such as sheet are integrated.
As shown in Figure 1, be the basic structure of a typical charge pump phase lock loop frequency synthesizer, mainly comprise following part: phase frequency detector (PFD, Phase Frequency Detector), charge pump (CP, Charge Pump), loop filter (LPF, Low Pass Filter), voltage controlled oscillator (VCO, Voltage Control Oscillator), frequency divider (Divider) and lock detecting circuit (Lock Detector).
Briefly introduce the effect of each main modular of charge pump phase lock loop frequency synthesizer below:
Phase frequency detector: an input input reference signal (FREF) of phase frequency detector, the feedback signal (FDIV) of another input for the output signal (FOUT) of frequency synthesizer being carried out with frequency divider obtain behind the frequency division.Phase frequency detector carries out frequency, bit comparison and output frequency, phase place comparative result mutually to reference signal and feedback signal, namely produces pulse control signal UP, DOWN.Frequency, phase place extent reflect with the pulsewidth of UP, DOWN signal.
Charge pump: convert pulse control signal UP, DOWN to current signal Icp, and the electric capacity in the loop filter is charged and discharges, with the generation voltage corresponding with frequency, the phase difference of reference signal and feedback signal.
Loop filter: to produce control voltage of voltage-controlled oscillator Vctrl, in addition, loop filter also is used for the high fdrequency component of filtering current signal Icp with the capacitor charge and discharge in the loop filter of current signal Icp of charge pump generation.
Voltage controlled oscillator: be used for the output signal (FOUT) of output frequency synthesizer, its frequency of oscillation is determined by the control voltage Vctrl of loop filter output.
Frequency divider: be used for the output signal of voltage controlled oscillator is carried out Fractional-N frequency, be the feedback signal of reference signal and frequency divider output because of two inputs of phase frequency detector, so the output of phase frequency detector is by regulating the frequency of oscillation of voltage controlled oscillator after the loop filter filtering, formula during according to loop-locking: FREF=FDIV=FOUT/N, thus the output signal frequency of frequency divider changed indirectly.
Lock detecting circuit: in the charge pump phase lock loop frequency synthesizer, lock detecting circuit is exported high and low logic level and is represented that respectively loop is in the lock state or out-of-lock condition (defining logic high usually is losing lock for locking, logic low).
The existing testing circuit that whether locks for detection of phase-locked loop comprises following several:
First method is whether the degree of closeness at the variation edge of comparison reference signal and feedback signal comes detection loop to lock.Reference signal in continuous several clock cycle and the clock of feedback signal variation edge are very approaching, and then lock detecting circuit thinks that loop locks, otherwise not locking.But the weak point of this lock detecting circuit be with analog circuit accurately detect, relatively two signals the variation edge be very difficult at interval.If there is static receiver error in phase-locked loop in addition, even this moment, phase-locked loop locked, but lock detecting circuit still can think there is not locking, produces erroneous judgement.Be illustrated in figure 2 as the main schematic diagram of this method, within the pulsewidth scope at the locking window signal of differing of reference signal and feedback signal, think loop-locking, the output high level, and differing outside the pulsewidth scope of locking window signal when reference signal and feedback signal, think the loop losing lock, output low level.As seen from the figure, realize that so accurate locking window signal is very difficult.
Second method is by reference signal and feedback signal are counted, and relatively whether whether the pulse number of the pulse number of certain hour internal reference signals and feedback signal equate to adjudicate phase-locked loop and locks.The structure more complicated of this lock detecting circuit, need two counters, and not necessarily can correctly reflect the lock-out state of phase-locked loop, because before phase-locked loop is in the lock state, the feedback clock signal potentially unstable, if and gate time is shorter, might loop and non-locking the reference signal situation identical with the feedback signal count value but takes place, namely produce erroneous judgement.And to avoid judging by accident artificially gate time is arranged very long, the increase that then can bring time cost.Be illustrated in figure 3 as the implementation that adopts two counters to constitute lock detecting circuit, circuit comprises first frequency divider (DIV_1), second frequency divider (DIV_2), first counter (Counter_1), second counter (Counter_2), comparator (Compare), circuit be input as reference signal (FREF), feedback signal (FDIV), be output as lock-in detection output signal (OUT).First frequency divider carries out frequency division to reference signal, and second frequency divider carries out frequency division to feedback signal, and the frequency division modulus of two frequency dividers should be identical.First counter is to the reference signal counting through frequency division, second counter is to the feedback signal counting through frequency division, comparator compares the count value of two counters, output logic high level when both count values equate, otherwise output logic low level.
Summary of the invention
Goal of the invention: the problem and shortage at above-mentioned prior art exists the invention provides a kind of charge pump phase lock loop frequency synthesizer lock detecting circuit.
Technical scheme: in order to realize the foregoing invention purpose, the present invention proposes a kind of charge pump phase lock loop frequency synthesizer lock detecting circuit.Its main design thought is by the UP of relatively phase frequency detector output, the pulsewidth of DOWN signal, and when the loop losing lock, the pulsewidth of the UP of phase frequency detector output, DOWN signal is unequal in clock cycle, and the result of XOR has high level.And when loop-locking, UP, the DOWN signal pulsewidth of an interior phase frequency detector output of clock cycle equate, so the result of XOR must be low level.Finally export the high and low logic level of lock detecting signal LOCK by a series of processing of subsequent conditioning circuit and represent that respectively loop is in the lock state or out-of-lock condition.
Charge pump phase lock loop frequency synthesizer of the present invention includes XOR gate with lock detecting circuit, first not gate, resistance, electric capacity, reverse Schmidt trigger, second not gate, and N digit counter; Wherein, two inputs of described XOR gate connect two output signals of phase frequency detector respectively, the input of output termination first not gate of XOR gate, first not gate the output connecting resistance, the input of the reverse Schmidt trigger of another termination of resistance; Electric capacity is connected in parallel on the input of reverse Schmidt trigger, other end ground connection, output termination second not gate of reverse Schmidt trigger, the reset terminal of the output termination N digit counter of second not gate, feedback signal behind the input termination process frequency divider frequency division of N digit counter, the N digit counter is output as the output signal LOCK of lock detecting circuit.
Whether described XOR gate equates for the pulsewidth of two output signals of judging phase frequency detector, and the output comparative result; When loop was in out-of-lock condition, two output signal signal pulsewidths of an interior phase frequency detector of clock cycle must be unequal, so the result of XOR necessarily has high level; And when loop was in the lock state, two output signal signal pulsewidths of an interior phase frequency detector of clock cycle equated, so the result of XOR must be low level.
Described first not gate is made of a PMOS and a NMOS, and effect is to capacitor charge and discharge, and first not gate should be designed to the inverter of the weak strong N-type of P, and namely the size of PMOS is less, and it is very slow to charge, and the size of NMOS is bigger, and discharge is very fast.The purpose of doing like this is to guarantee that lock detecting circuit also can detect for very little phase difference.
Described resistance is used for the size of the charging and discharging currents of control first not gate, described electric capacity is used for giving reverse Schmidt trigger that an input voltage is provided, described reverse Schmidt trigger is for generation of the output voltage of voltage on the response electric capacity, and carry out logic level values for second not gate and judge, described second not gate is used for judging the magnitude of voltage of reverse Schmidt trigger output and waveform is carried out shaping, exports the result of a logic high or logic low with the reset terminal of control N digit counter.
A kind of charge pump phase lock loop frequency synthesizer of the present invention with the detection method of lock detecting circuit is: (1) is when charge pump phase lock loop is in normal operating conditions, in each input clock cycle, whether the pulsewidth that the first order XOR gate unit of lock detecting circuit all will detect two output signal signals of phase frequency detector equates, if pulsewidth equates, because reset terminal is logic high, then the N digit counter begins counting, otherwise N digit counter hold reset state; (2) when charge pump phase lock loop is in out-of-lock condition, the pulsewidth of the UP signal of phase frequency detector output is greater than or less than the pulsewidth of DOWN signal, this moment, the output of second not gate kept low level, so N digit counter hold reset state, the output signal LOCK of lock detecting circuit keeps low level; (3) when charge pump phase lock loop is in the lock state, the pulsewidth of two output signals of phase frequency detector equates, this moment, the output of second not gate kept high level, so the N digit counter begins counting, when the pulsewidth of two output signals of phase frequency detector kept N cycle constant, the N digit counter was exported effective LOCK signal.The input of described N digit counter is that output is the output signal LOCK of lock detecting circuit through the feedback signal FDIV behind the frequency divider frequency division, and the Reset end is reset terminal.When reset terminal was low level, N digit counter unit began clearly 0, output step-down and keep low level constant, and when reset terminal is high level and keeps N cycle when constant, the output of N digit counter becomes high level and namely exports effective LOCK signal.Beneficial effect: a kind of charge pump phase lock loop frequency synthesizer of the present invention's design lock detecting circuit reliability height, the difficult erroneous judgement by accident because simple in structure, is conducive to reduce circuit layout area and time cost simultaneously.Description of drawings Fig. 1 is the basic structure of charge pump phase lock loop frequency synthesizer, Fig. 2 is the lock-in detection mode that comparison reference signal and feedback signal change the edge, Fig. 3 is the lock detecting circuit that compares the pulse number of certain hour internal reference signals and feedback signal, a kind of charge pump phase lock loop frequency synthesizer lock detecting circuit that Fig. 4 the present invention proposes, the UP of phase frequency detector output when Fig. 5 is the loop losing lock, the DOWN signal, the UP of phase frequency detector output when Fig. 6 is loop-locking, the DOWN signal, Fig. 7 is the structure of first not gate, lock detecting circuit analog result schematic diagram when Fig. 8 is in out-of-lock condition for phase-locked loop, the lock detecting circuit analog result schematic diagram when Fig. 9 is in the lock state for phase-locked loop.
The technological means of embodiment in order to further specify advantage of the present invention place and specifically to take is described in further detail the specific embodiment of the present invention below in conjunction with accompanying drawing.Fig. 1-Fig. 3 repeats no more for the introduction of existing background technology.As shown in Figure 4, a kind of charge pump phase lock loop frequency synthesizer provided by the present invention comprises with lock detecting circuit: XOR gate XOR, the first not gate NOT_1, resistance R, capacitor C, reverse Schmidt trigger Inverting Schmitt Trigger, the second not gate NOT_2, and N digit counter Counter.Wherein, two inputs of described XOR gate meet two output signal: UP, DOWN of phase frequency detector respectively.The input of output termination first not gate of XOR gate.First not gate the output connecting resistance.The output of resistance connects the input of reverse Schmidt trigger.Electric capacity is connected in parallel on the input of reverse Schmidt trigger, other end ground connection.Output termination second not gate of reverse Schmidt trigger.The reset terminal Reset of the output termination N digit counter of second not gate.The input IN of N digit counter connects through the feedback signal FDIV behind the frequency divider frequency division, and the output OUT of N digit counter is the output signal LOCK of lock detecting circuit.Be whole lock detecting circuit be input as UP, DOWN signal, be output as lock detecting signal LOCK.When charge pump phase lock loop was in normal operating conditions, in each input clock cycle, the first order XOR gate unit of lock detecting circuit all will detect the UP of phase frequency detector output, whether the pulsewidth of DOWN signal equates.If pulsewidth equates that because reset terminal is logic high, then the N digit counter begins counting, otherwise N digit counter hold reset state.When charge pump phase lock loop is in out-of-lock condition, the pulsewidth of the UP signal of phase frequency detector output is greater than or less than the pulsewidth of DOWN signal, this moment, the output of second not gate kept low level, so N digit counter hold reset state, the output signal LOCK of lock detecting circuit keeps low level.When charge pump phase lock loop is in the lock state, the UP of phase frequency detector output, the pulsewidth of DOWN signal equate, this moment, the output of second not gate kept high level, so the N digit counter begins counting, when the pulsewidth of UP, DOWN signal kept N cycle constant, the N digit counter was exported effective LOCK signal.Its operation principle is: XOR gate detects the output signals UP of phase frequency detector, the pulsewidth of DOWN, and the output comparative result.As shown in Figure 5, this moment reference signal phase-lead in feedback signal, the loop non-locking, then the pulsewidth of UP, DOWN signal is unequal in a clock cycle, ideally should have only UP signal output pulse signal, and the DOWN signal should remain low level.But because the existence of non-ideal effects in the phase frequency detector, the DOWN signal can be exported small pulsewidth, and this is the delay owing to generations such as the reset circuits in the phase frequency detector, so the result of XOR gate XOR must have high level.As shown in Figure 7, be the structure of first not gate.First not gate is made of a PMOS and a NMOS, and effect is to capacitor charge and discharge.First not gate should be designed to the inverter of the weak strong N-type of P, and namely the size of PMOS is less, and it is very slow to charge, and the size of NMOS is bigger, and discharge is very fast.The purpose of doing like this is to guarantee that lock detecting circuit also can detect for very little phase difference.In a clock cycle, more percentage high level accounts for less percentage to the result of XOR for low level accounts for, and it is very fast to discharge owing to charging is very slow again, so the voltage integral body on the electric capacity is on a declining curve.The first non-resistance of series connection behind the door is mainly used in controlling the size of charging and discharging currents, and according to the needs of actual conditions, resistance can omit.The characteristics of described reverse Schmidt trigger are: when input voltage is lower than the negative sense threshold voltage, be output as height.And when input voltage is higher than positive threshold, be output as low.When input was between negative sense threshold value and positive threshold, output remained unchanged, and that is to say that when enough variations took place input voltage, output just changed, and this phenomenon shows that hysteresis phenomenon reverse Schmidt trigger has Memorability.When the voltage on the electric capacity drops to the negative sense threshold voltage of reverse Schmidt trigger when following, reverse Schmidt trigger output logic high level.So give the reset terminal of N digit counter by the second non-output low level behind the door.The input of described N digit counter is that output is the output signal LOCK of lock detecting circuit through the feedback signal (FDIV) behind the frequency divider frequency division, and the Reset end is reset terminal.Because during the loop losing lock, the reset terminal of N digit counter keeps low level, so the output signal LOCK of lock detecting circuit keeps low level constant.As shown in Figure 6, the phase place of reference signal equates loop-locking with the phase place of feedback signal at this moment.Ideally UP, DOWN signal all should remain low level.But because the existence of non-ideal effects in the phase frequency detector, UP, DOWN signal all can be exported small pulsewidth, and this is the delay owing to generations such as the reset circuits in the phase frequency detector, but the result of XOR gate XOR still keeps low level.So by first non-the continuing behind the door to the electric capacity charging, when the voltage on the electric capacity rises to the positive threshold that is higher than reverse Schmidt trigger, reverse Schmidt trigger output logic low level.So non-ly export the reset terminal that high level is given the N digit counter behind the door by second again.When reset terminal is high level and keeps N cycle when constant, the output of N digit counter becomes high level and namely exports effective LOCK signal.
As shown in Figure 8, lock detecting circuit analog result schematic diagram when being in out-of-lock condition for charge pump phase lock loop, be expressed as reference signal (FREF) among the figure from top to bottom respectively, feedback signal (FOUT), UP signal, DOWN signal, the pulse signal (XOR) of XOR gate output, voltage is the input (IST_IN) of reverse Schmidt trigger on the electric capacity, the oppositely output (IST_OUT) of Schmidt trigger, the output of second not gate (NOT_2).The phase-lead of reference signal is in feedback signal at this moment, the pulsewidth difference of UP, the output of DOWN signal, the result of XOR has high level in the one-period, when the voltage on the electric capacity is in the negative sense threshold value of reverse Schmidt trigger when following, oppositely Schmidt trigger is output as the logic height, so second not gate is output as low level.As shown in Figure 9, lock detecting circuit analog result schematic diagram when being in the lock state for charge pump phase lock loop, be expressed as reference signal (FREF) among the figure from top to bottom respectively, feedback signal (FOUT), the UP signal, DOWN signal, the pulse signal (XOR) of XOR gate output, the oppositely output (IST_IN) of Schmidt trigger, the output of second not gate (NOT_2).This moment, the phase place of reference signal was identical with the phase place of feedback signal, interior UP of clock cycle, a DOWN signal are all exported the small pulsewidth of same widths, the result of XOR is low level, when the voltage on the electric capacity is in the positive threshold of reverse Schmidt trigger when above, oppositely Schmidt trigger is output as logic low, so second not gate is output as high level.
In sum, the lock detecting circuit of a kind of charge pump phase lock loop frequency synthesizer provided by the invention is by the UP of relatively phase frequency detector output, the pulsewidth of DOWN signal, and the high and low logic level of output lock detecting signal LOCK represents that respectively loop is in the lock state or out-of-lock condition.The reliability height of lock detecting circuit, the difficult erroneous judgement by accident because simple in structure, is conducive to reduce circuit layout area and time cost simultaneously.It below only is example of the present invention, do not constitute any limitation of the invention, obviously, under thought of the present invention, any those skilled in the art, in not breaking away from technical scheme scope of the present invention, the technology contents that can utilize above-mentioned announcement is suitably adjusted circuit structure and components and parts size or is optimized, refer to any simple modification, equivalents and modification that above embodiment is done according to technology of the present invention, all belong to the scope of technical solution of the present invention.
Claims (6)
1. charge pump phase lock loop frequency synthesizer lock detecting circuit, it is characterized in that: this circuit includes XOR gate (XOR), first not gate (NOT_1), resistance (R), electric capacity (C), reverse Schmidt trigger (I ST), second not gate (NOT_2), and N digit counter (Counter); Wherein, two inputs of described XOR gate (XOR) connect two output signals (UP, DOWN) of phase frequency detector respectively, the input of output termination first not gate (NOT_1) of XOR gate, first not gate (NOT_1) output connecting resistance (R), the input of the reverse Schmidt trigger of another termination (IST) of resistance (R); Electric capacity (C) is connected in parallel on the input of reverse Schmidt trigger, other end ground connection (GND), output termination second not gate (NOT_2) of reverse Schmidt trigger, the reset terminal (Reset) of the output termination N digit counter of second not gate (NOT_2), the input of N digit counter (IN) connects through the feedback signal (F behind the frequency divider frequency division
DIV), the output of N digit counter (OUT) is the output signal LOCK of lock detecting circuit.
2. a kind of charge pump phase lock loop frequency synthesizer lock detecting circuit as claimed in claim 1, it is characterized in that: whether described XOR gate (XOR) equates for the pulsewidth of two output signals (UP, DOWN) of judging phase frequency detector, and the output comparative result; When loop was in out-of-lock condition, two output signals (UP, DOWN) the signal pulsewidth of an interior phase frequency detector of clock cycle must be unequal, so the result of XOR necessarily has high level; And when loop was in the lock state, two output signals (UP, DOWN) the signal pulsewidth of an interior phase frequency detector of clock cycle equated, so the result of XOR must be low level.
3. a kind of charge pump phase lock loop frequency synthesizer lock detecting circuit as claimed in claim 1, it is characterized in that: described first not gate (NOT_1) is made of a PMOS and a NMOS, effect is to capacitor charge and discharge, first not gate should be designed to the inverter of the weak strong N-type of P, the size that is PMOS is less, and it is very slow to charge, and the size of NMOS is bigger, discharge is very fast, and the purpose of doing like this is to guarantee that lock detecting circuit also can detect for very little phase difference.
4. a kind of charge pump phase lock loop frequency synthesizer lock detecting circuit as claimed in claim 1, it is characterized in that: described resistance (R) is used for the size of the charging and discharging currents of control first not gate, described electric capacity (C) is used for giving reverse Schmidt trigger that an input voltage is provided, described reverse Schmidt trigger is for generation of the output voltage of voltage on the response electric capacity, and carry out logic level values for second not gate and judge, described second not gate (NOT_2) is used for judging the magnitude of voltage of reverse Schmidt trigger output and waveform is carried out shaping, exports the result of a logic high or logic low with the reset terminal of control N digit counter.
5. an a kind of charge pump phase lock loop frequency synthesizer as claimed in claim 1 is characterized in that with the detection method of lock detecting circuit:
(1) when charge pump phase lock loop is in normal operating conditions, in each input clock cycle, whether the pulsewidth that the first order XOR gate unit of lock detecting circuit all will detect two output signals (UP, the DOWN) signal of phase frequency detector equates, if pulsewidth equates, because reset terminal is logic high, then the N digit counter begins counting, otherwise N digit counter hold reset state;
(2) when charge pump phase lock loop is in out-of-lock condition, the pulsewidth of the UP signal of phase frequency detector output is greater than or less than the pulsewidth of DOWN signal, this moment, the output of second not gate kept low level, so N digit counter hold reset state, the output signal LOCK of lock detecting circuit keeps low level;
(3) when charge pump phase lock loop is in the lock state, the pulsewidth of two output signals of phase frequency detector (UP, DOWN) equates, this moment, the output of second not gate kept high level, so the N digit counter begins counting, when the pulsewidth of two output signals (UP, DOWN) of phase frequency detector kept N cycle constant, the N digit counter was exported effective LOCK signal.
6. a kind of charge pump phase lock loop frequency synthesizer lock detecting circuit as claimed in claim 5 is characterized in that: the input of described N digit counter is for through the feedback signal F behind the frequency divider frequency division
DIV, output is the output signal LOCK of lock detecting circuit, the Reset end is reset terminal; When reset terminal was low level, N digit counter unit began clearly 0, output step-down and keep low level constant, and when reset terminal is high level and keeps N cycle when constant, the output of N digit counter becomes high level and namely exports effective LOCK signal.
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Application publication date: 20130703 |