CN112564697A - Phase-locked loop system and phase-locked control method - Google Patents
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- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
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Abstract
The invention discloses a phase-locked loop system, which comprises a quick locking circuit, a control circuit and a control circuit, wherein the quick locking circuit is used for providing charging current for a capacitor in a filter in a charge pump phase-locked loop so as to promote the control voltage of a voltage-controlled oscillator in the charge pump phase-locked loop; the charge pump phase-locked loop is controlled by the quick locking circuit after being electrified, and the locking process is independently completed until the quick locking circuit finishes working. The fast locking circuit comprises a PMOS transistor, a D trigger, a delay unit and an inverter; the output end of the delay unit is connected with the input end of the D trigger, the output end of the D trigger is connected with the input end of the phase inverter, and the output end of the phase inverter is connected with the input end of the PMOS transistor. The phase-locked loop system provided by the invention is additionally provided with the quick locking circuit on the basis of not changing the traditional phase-locked loop composition module, and the whole quick locking circuit has a simple structure, can improve the stability of the circuit performance and is beneficial to large-scale application.
Description
Technical Field
The invention belongs to the technical field of wired communication integrated circuits, and particularly relates to a phase-locked loop system and a phase-locked control method.
Background
In wired communication, a Phase Locked Loop (PLL) is a core function circuit that provides a clock signal required for transmitting data to a Transmitter (TX) and a Receiver (RX). The wired communication protocol typically specifies the reference clock frequency, loop bandwidth (loop bandwidth), and lock time of the PLL, in addition to the signal quality provided by the PLL. However, the loop bandwidth and the locking time are compromised in the most widely used Charge Pump Phase Locked Loop (CPPLL) design, which puts higher requirements on the design of the pll.
The core module of the CPPLL includes a crystal oscillator (XO), a Phase Frequency Detector (PFD), a Charge Pump (CP), a Loop Filter (LF), a Voltage Controlled Oscillator (VCO), and a frequency divider (divider). The basic principle is that the phase of a clock signal of a VCO after frequency division is compared with the phase of a reference clock signal through a PFD (pulse frequency detector), so that signals for controlling a current source and a current sink of a charge pump are generated to charge and discharge a capacitor in a filter, and further, the voltage for controlling the VCO is generated to realize the stable frequency multiplication function of the clock signal output by the VCO on the reference clock signal. The whole loop realizes a negative feedback mechanism to ensure the locking relation of the phases of the frequency division clock and the reference clock. In order to ensure the stability of the loop and ease the design of the loop parameters, it is usually necessary to ensure that the loop bandwidth of the PLL is less than one tenth of the reference clock frequency, which means that the reference clock frequency limits the upper limit of the loop bandwidth. In addition, when the VCO is of an LC type structure, a small loop bandwidth can bring better noise performance to the phase-locked loop system, i.e., a small bandwidth phase-locked loop is necessary in many application contexts. Meanwhile, the loop bandwidth of the PLL determines the locking time of the loop system, i.e. a larger loop bandwidth can achieve a shorter locking time.
In many communication protocols, however, a PLL is required to achieve fast loop lock at low loop bandwidth. This requires the addition of an auxiliary fast lock function in the conventional CPPLL architecture. The first one is to increase the injection current value of a charge pump when a PLL is electrified through a control circuit; the second method is to pre-configure the control voltage of the VCO through a digital-analog hybrid circuit; the third method is to use an analog circuit composed of a plurality of operational amplifiers to control the current source to additionally charge the filter capacitor. The three methods all use an auxiliary module to quickly push the control voltage of the VCO to be near a locking level to realize a quick locking function, but the three schemes are complicated in design and not beneficial to the wide application of the technology.
Disclosure of Invention
Therefore, in the prior art, the current loop locking method is very complex in implementation process and is not suitable for wide application.
Therefore, there is a great need for a phase-locked loop system that can achieve a fast locking function of the phase-locked loop system even when the phase-locked loop system has a simple structure.
In a first aspect of embodiments of the present invention, there is provided a phase-locked loop system, comprising: a fast locking circuit and a charge pump phase locked loop; the fast locking circuit is used for providing charging current for a capacitor in a filter in the charge pump phase-locked loop so as to promote the control voltage of a voltage-controlled oscillator in the charge pump phase-locked loop; and the charge pump phase-locked loop is controlled by the quick locking circuit after being electrified, and independently finishes the locking process until the quick locking circuit finishes working.
In one embodiment of the present invention, a fast locking circuit includes a PMOS transistor, a D flip-flop, a delay unit, and an inverter; an output end of the delay unit is connected with an input end of the D flip-flop, an output end of the D flip-flop is connected with an input end of the inverter, and an output end of the inverter is connected with an input end of the PMOS transistor;
in another embodiment of the present invention, the charge pump phase-locked loop includes a crystal oscillator, a phase frequency detector, a charge pump, the filter, a frequency divider, and the voltage-controlled oscillator, and the phase frequency detector, the charge pump, the filter, the voltage-controlled oscillator, and the frequency divider are sequentially connected to form a loop; the output end of the crystal oscillator is connected with the input end of the phase frequency detector.
In another embodiment of the present invention, a first capacitor and a second capacitor are disposed in the filter.
In yet another embodiment of the present invention, an output terminal of the PMOS transistor of the fast locking circuit is connected to the first capacitor.
In yet another embodiment of the present invention, the output terminal of the crystal oscillator and the output terminal of the phase frequency detector are respectively connected to the input terminal of the delay unit of the fast locking circuit; the output end of the charge pump is connected with the input end of the PMOS transistor of the quick locking circuit.
In a second aspect of the embodiments of the present invention, there is provided a phase-lock control method of a phase-locked loop system, including:
the output signal of the voltage-controlled oscillator is divided by the frequency divider to obtain a frequency division signal and a reference clock signal generated by the crystal oscillator simultaneously enter the phase frequency detector;
the phase frequency detector outputs a first pulse to enter a D trigger by comparing the frequency difference between the frequency division signal and the reference clock signal;
the reference clock signal generated by the crystal oscillator enters the D flip-flop through a delay unit;
the D flip-flop samples the first pulse according to the reference clock signal and outputs a second pulse;
the second pulse enters the PMOS transistor through the inverter;
the PMOS transistor changes a conduction state according to the second pulse;
when the PMOS transistor is in a conducting state, the charge pump continuously supplies power to the first capacitor;
when the PMOS transistor is in a closed state, the charge pump phase-locked loop works independently to complete phase locking.
In an embodiment of the invention, the delay time provided by the delay unit is greater than the sum of the pulse width generated by the phase frequency detector when the loop is locked and the trigger time of the D flip-flop.
In another embodiment of the present invention, the PMOS transistor changing the on state according to the second pulse includes:
when the second pulse is at high level, the PMOS transistor is conducted;
when the second pulse is at a low level, the PMOS transistor is turned off.
In another embodiment of the present invention, when the frequency of the frequency-divided signal is lower than the frequency of the reference clock signal, the first pulse is at a high level;
when the frequency of the frequency-divided signal is close to or higher than the frequency of the reference clock signal, the first pulse is at a low level.
The phase-locked loop system provided by the embodiment of the invention is additionally provided with the quick locking circuit on the basis of not changing the traditional phase-locked loop composition module, and the whole quick locking circuit has a simple structure, can improve the stability of the circuit performance and is beneficial to large-scale application.
Meanwhile, the rapid locking circuit provided by the embodiment of the invention can greatly shorten the time of the voltage-controlled oscillator for climbing from 0V to the vicinity of the level required by locking. And when the quick locking circuit is designed, the delay time provided by the delay unit can be flexibly adjusted to change the locking precision of the quick locking circuit, namely, the smaller delay time can enable the phase-locked loop system to be closer to a locking state after the quick locking process, and the control is convenient.
Drawings
Fig. 1 is a schematic structural diagram of a phase-locked loop system according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a fast lock circuit and a loop filter according to an embodiment of the present invention;
in the figure: 1. a crystal oscillator; 2. a phase frequency detector; 3. a charge pump; 4. a filter; 5. a voltage controlled oscillator; 6. a frequency divider; 7. a fast lock circuit; 8. a delay unit; 9. a D flip-flop; 10. an inverter; 11. and a PMOS transistor.
Fig. 3 is a flowchart of a phase-lock control method of a phase-locked loop system according to an embodiment of the present invention.
Fig. 4 is a timing diagram illustrating the operation of the fast locking circuit when the frequency of the output signal of the frequency divider is lower than the frequency of the reference clock signal during the operation of the pll system according to an embodiment of the present invention.
Fig. 5 is a timing diagram illustrating operation of a fast lock circuit when the frequency of the divider output signal approaches or exceeds the frequency of the reference clock during operation of the phase locked loop system, according to an embodiment of the present invention.
Fig. 6 is a schematic diagram of simulated waveforms of VQ, VC1, and VC2 in the fast locking circuit provided by the embodiment of the present invention during system locking.
Fig. 7 is a diagram illustrating a comparison of simulation results of a locking process provided by an embodiment of the present invention and a locking process of a conventional charge pump phase-locked loop.
Detailed Description
In order that the objects, technical solutions and advantages of the present invention will become more apparent, the present invention will be further described in detail with reference to the accompanying drawings in conjunction with the following specific embodiments.
The fast lock circuit and the phase-locked loop system of the exemplary embodiment of the present invention are described below with reference to fig. 1 and 2.
Fig. 1 is a schematic structural diagram of a phase-locked loop system according to an embodiment of the present invention; FIG. 2 is a schematic diagram of a fast lock circuit and a loop filter according to an embodiment of the present invention;
the phase-locked loop system provided by the embodiment of the invention comprises: a fast locking circuit 7 and a charge pump 3 phase locked loop; the fast locking circuit 7 is used for providing charging current for a capacitor in the filter 4 in the charge pump phase-locked loop so as to boost the control voltage of the voltage-controlled oscillator 5 in the charge pump phase-locked loop; and the charge pump phase-locked loop is controlled by the quick locking circuit 7 after being electrified, and the locking process is independently completed until the quick locking circuit 7 finishes working.
In the present embodiment, as shown in fig. 2, the quick lock circuit 7 includes a PMOS transistor 11, a D flip-flop 9, a delay unit 8, and an inverter 10; the output end of the delay unit 8 is connected with the input end of the D trigger 9, the output end of the D trigger 9 is connected with the input end of the phase inverter 10, and the output end of the phase inverter 10 is connected with the input end of the PMOS transistor 11;
in this embodiment, as shown in fig. 1, the charge pump phase-locked loop includes a crystal oscillator 1, a phase frequency detector 2, a charge pump 3, a filter 4, a frequency divider 6, and a voltage-controlled oscillator 5, where the phase frequency detector 2, the charge pump 3, the filter 4, the voltage-controlled oscillator 5, and the frequency divider 6 are connected in sequence to form a loop; the output end of the crystal oscillator 1 is connected with the input end of the phase frequency detector 2; the filter 4 is provided with a first capacitor and a second capacitor therein.
In the present embodiment, as shown in fig. 1 and fig. 2, the output terminal of the PMOS transistor 11 of the fast latch circuit 7 is connected to the first capacitor; the output end of the crystal oscillator 1 and the output end of the phase frequency detector 2 are respectively connected with the input end of a delay unit 8 of the quick locking circuit 7; the output of the charge pump 3 is connected to the input of a PMOS transistor 11 of the fast lock circuit 7.
According to the embodiment of the invention, a quick locking circuit is added on the basis of not changing the traditional phase-locked loop composition module, and the whole quick locking circuit has a simple structure, can improve the stability of the circuit performance and is beneficial to large-scale application.
After the structures of the fast locking circuit and the phase-locked loop system provided by the embodiment of the present invention are introduced, a phase-locked control method of the phase-locked loop system provided by the embodiment of the present invention is described below with reference to fig. 3.
Fig. 3 is a flowchart of a phase-lock control method of a phase-locked loop system according to an embodiment of the present invention.
As shown in fig. 3, the phase-lock control method of the phase-locked loop system according to the present embodiment includes operations S101 to S108.
In operation S101, a frequency-divided signal obtained by dividing the output signal of the voltage-controlled oscillator 5 by the frequency divider 6 and a reference clock signal generated by the crystal oscillator 1 are simultaneously input to the phase frequency detector 2.
In operation S102, the phase frequency detector 2 outputs a first pulse into the D flip-flop 9 by comparing a frequency difference between the frequency-divided signal and the reference clock signal.
In operation S103, the reference clock signal generated by the crystal oscillator 1 enters the D flip-flop 9 through the delay unit 8.
In operation S104, the D flip-flop 9 samples the first pulse according to the reference clock signal and outputs the second pulse.
In operation S105, the second pulse enters the PMOS transistor 11 through the inverter 10.
In operation S106, the PMOS transistor 11 changes the on state according to the second pulse.
In operation S107, the charge pump 3 continuously supplies power to the first capacitor when the PMOS transistor 11 is in the on state.
In operation S108, when the PMOS transistor 11 is in the off state, the charge pump phase-locked loop operates alone to complete phase locking. In the present embodiment, the delay time provided by the delay unit 8 is greater than the sum of the pulse width generated by the phase frequency detector 2 when the loop is locked and the trigger time of the D flip-flop 9.
According to the embodiment of the invention, the charging process of the first capacitor is continuous when the fast locking circuit works, and when the phase of the frequency division signal analyzed by the phase frequency detector lags behind the phase of the reference clock signal, the PMOS transistor can be in a conducting state all the time by the D trigger through sampling the first pulse, so that the continuous charging of the first capacitor is realized until the phase of the frequency division signal approaches or exceeds the phase of the reference clock signal. In the prior art, the power supply of a charge pump in the phase-locked loop to the filter is changed in real time according to the output pulse width of the phase frequency detector, and the charging process is discontinuous. Compared with the prior art, the fast locking circuit provided by the embodiment of the invention can greatly shorten the time of the voltage-controlled oscillator for climbing from 0V to the vicinity of the level required by locking.
In this embodiment, when the frequency of the divided signal is lower than the frequency of the reference clock signal, the first pulse is at a high level;
the first pulse is at a low level when the frequency of the divided signal is close to or higher than the frequency of the reference clock signal.
In the present embodiment, the PMOS transistor 11 changing the on state according to the second pulse includes:
when the second pulse is at a high level, the PMOS transistor 11 is turned on;
when the second pulse is low, the PMOS transistor 11 is turned off.
According to the embodiment of the invention, the quick locking circuit can greatly shorten the time for the control voltage of the voltage-controlled oscillator to climb from 0V to the vicinity of the level required by locking. And when the quick locking circuit is designed, the delay time provided by the delay unit can be flexibly adjusted to change the locking precision of the quick locking circuit, namely, the smaller delay time can enable the phase-locked loop system to be closer to a locking state after the quick locking process, and the control is convenient.
The operation principle of the fast locking circuit and the phase-locked loop system provided by the embodiment of the present invention is described below with reference to fig. 1, fig. 2, fig. 4, and fig. 5.
As shown in fig. 1, the fast lock circuit 7 is an auxiliary circuit added on the basis of a conventional CPPLL. The fast locking circuit 7 is controlled by a reference clock signal VFREFAnd the output signal V of the phase frequency detector 2UPAnd requires a bias voltage V provided by the charge pump 3B. At the same time, the charge pump 3 supplies a charging current I to the loop filter 4F。
As shown in FIG. 2, the fast lock circuit 7 is essentially a reference clock signal V controlled byFREFAnd the output signal V of the phase frequency detector 2UPOf the current source, which outputs a current IFFor the capacitor C in the filter 41Charging to raise the voltage VC1Thereby raising the voltage VC2. Whether the current source outputs current or not is controlled by the switch PMOS transistor 11M1. When M is1When the gate voltage is low, the transistor 11 is turned on and the current source is the capacitor C1Providing IFThe current of (a); when M is1When the gate voltage is high, the transistor 11 is turned off and the current source stops to be the capacitor C1Providing an electric current. At the same time, the gate voltage of M1 is output V by D flip-flop 9QObtained by a phase inverter 10, the clock signal of a D flip-flop 9 is obtained by a reference clock signal after passing through a delay unit 8, and the function of the D flip-flop 9 is to sample the output signal V of the phase frequency detector 2UP. That is, the quick locking circuit 7 basically functions as: when the fast locking circuit 7 identifies the output signal V of the phase frequency detector 2UPWhen high, the capacitor C is applied to the filter 41Charging with a charging current of IF(ii) a When the fast locking circuit 7 recognizes the signal VUPWhen low, the capacitor C of the filter 4 is stopped1And (6) charging.
Fig. 4 is a timing diagram illustrating the operation of the fast locking circuit when the frequency of the output signal of the frequency divider is lower than the frequency of the reference clock signal during the operation of the pll system according to an embodiment of the present invention.
As shown in fig. 4, at VFDIVFrequency lower than VFREFAt a frequency of (i.e. V)FDIVIs more retarded than VFREFIn the phase of (2), the output signal V of the phase frequency detectorUPTime t of highUP1Greater than the delay time t provided by the delay unit 8DLYAt this time, the D flip-flop 9 will pick up a high level.
Fig. 5 is a timing diagram illustrating operation of a fast lock circuit when the frequency of the divider output signal approaches or exceeds the frequency of the reference clock during operation of the phase locked loop system, according to an embodiment of the present invention.
As shown in fig. 5, at VFDIVFrequency approaching or exceeding VFREFAt a frequency of (i.e. V)FDIVIs close to or leads VFREFIn the phase of (2), the output signal V of the phase frequency detectorUPTime t of highUP0Less than the delay time t provided by the delay unit 8DLYAt this time, the D flip-flop 9 will pick up a low level.
Note that t isUP0Namely, the pulse width of the output signal of the phase frequency detector 2 when the phase-locked loop system is locked, the necessary reason for the pulse width is that the switch for controlling the on-off of the output current of the charge pump 3 cannot enable the charge pump 3 to output the full current value (i.e. the charge pump 3 has a work dead zone) within the excessively short on time, and t is the pulse width of the output signal of the phase frequency detector 2 when the phase-locked loop system is lockedUP0Is present in that this dead zone is eliminated. To ensure that fast latch circuit 7 can enter the timing state shown in FIG. 4, the settling time t of D flip-flop 9 is taken into accountSETUPThe following conditions must be ensured when designing the delay unit 8:
tDLY＞tUP0+tSETUP(A)
With reference to the above description, the working principle of the phase-locked loop system provided in this embodiment is as follows: v of the first capacitor after the phase-locked loop system is powered onC1And V of the second capacitanceC2Is always started to rise from 0V, i.e. VFDIVIs always below V at the start of system operationFREFThat is, after the system is powered on, the PLL system always starts from the timing chart described in FIG. 3，VQRemains high, and the fast latch circuit 7 is now a capacitor C1Charging, will VC1And VC2The level of (2) is pulled up rapidly. When V isFDIVIs close to or slightly exceeds VFREFAt a frequency of (d), the pll system enters the timing state, V, depicted in fig. 4QHeld low, fast latch circuit 7 stops coupling capacitor C1And (6) charging. Then, the phase-locked loop system returns to the traditional working mode to complete the final fine locking process.
The function of the present invention is further described by the simulation result of the phase-locked loop system.
Fig. 6 is a schematic diagram of simulated waveforms of VQ, VC1, and VC2 in the fast locking circuit provided by the embodiment of the present invention during system locking.
As shown in FIG. 6, at the start of simulation (simulating the state when the chip is powered on), VC1And VC2Are all in a 0V voltage state, and then VQIs pulled high, i.e. the fast locking circuit starts to operate, VC1And VC2At a level of VQIs pulled up quickly to near the level required for the locked state when high.
At VFDIVHas a frequency slightly exceeding VFREFAfter frequency of (V)QIs pulled down, namely the quick locking circuit starts to work, and the phase-locked loop returns to the traditional working mode to complete the subsequent locking process.
Fig. 7 is a diagram illustrating a comparison of simulation results of a locking process provided by an embodiment of the present invention and a locking process of a conventional charge pump phase-locked loop. As can be seen from fig. 7, the present invention requires only 5us to complete locking, whereas the conventional CPPLL requires 12us to complete locking.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A phase-locked loop system, comprising:
the fast locking circuit is used for providing charging current for a capacitor in a filter in the charge pump phase-locked loop so as to promote the control voltage of a voltage-controlled oscillator in the charge pump phase-locked loop;
the fast locking circuit comprises a PMOS transistor, a D trigger, a delay unit and an inverter; the output end of the delay unit is connected with the input end of the D trigger, the output end of the D trigger is connected with the input end of the phase inverter, and the output end of the phase inverter is connected with the input end of the PMOS transistor;
the charge pump phase-locked loop is controlled by the quick locking circuit after being electrified, and the locking process is independently completed after the quick locking circuit finishes working.
2. The phase-locked loop system of claim 1, wherein the charge pump phase-locked loop comprises a crystal oscillator, a phase frequency detector, a charge pump, the filter, a frequency divider, and the voltage controlled oscillator, and wherein the phase frequency detector, the charge pump, the filter, the voltage controlled oscillator, and the frequency divider are connected in sequence to form a loop; and the output end of the crystal oscillator is connected with the input end of the phase frequency detector.
3. The phase-locked loop system of claim 2, wherein the filter has a first capacitor and a second capacitor disposed therein.
4. The phase-locked loop system of claim 3, wherein the output of the PMOS transistor of the fast lock circuit is coupled to the first capacitor.
5. The phase-locked loop system of claim 2, wherein an output of the crystal oscillator and an output of the phase frequency detector are respectively connected to an input of a delay unit of the fast lock circuit.
6. The phase-locked loop system of claim 2, wherein an output of the charge pump is coupled to an input of a PMOS transistor of the fast lock circuit.
7. A phase-lock control method of a phase-locked loop system according to any one of claims 1 to 6, comprising:
the output signal of the voltage-controlled oscillator is divided by the frequency divider to obtain a frequency division signal and a reference clock signal generated by the crystal oscillator simultaneously enter the phase frequency detector;
the phase frequency detector outputs a first pulse to enter a D trigger by comparing the frequency difference between the frequency division signal and the reference clock signal;
the reference clock signal generated by the crystal oscillator enters the D flip-flop through a delay unit;
the D flip-flop samples the first pulse according to the reference clock signal and outputs a second pulse;
the second pulse enters the PMOS transistor through the inverter;
the PMOS transistor changes a conducting state according to the second pulse;
when the PMOS transistor is in a conducting state, the charge pump continuously supplies power to the first capacitor;
and when the PMOS transistor is in a closed state, the charge pump phase-locked loop works independently to complete phase locking.
8. The method of claim 7, wherein the delay unit provides a delay time greater than a sum of a pulse width generated by the phase frequency detector when the loop is locked and a trigger time of the D flip-flop.
9. The method of claim 7, wherein the phase frequency detector outputting a first pulse into a D flip-flop by comparing a frequency difference between the divided signal and the reference clock signal comprises:
when the frequency of the frequency division signal is lower than the frequency of the reference clock signal, the first pulse is at a high level;
when the frequency of the frequency division signal is close to or higher than the frequency of the reference clock signal, the first pulse is at a low level.
10. The method of claim 7, wherein the PMOS transistor changing on-state according to the second pulse comprises:
when the second pulse is at a high level, the PMOS transistor is conducted;
and when the second pulse is at a low level, the PMOS transistor is closed.
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| CN101908870A (en) * | 2010-08-02 | 2010-12-08 | 中国电子科技集团公司第二十四研究所 | Quick locking control circuit of pulse width control loop |
| CN103187971A (en) * | 2013-02-03 | 2013-07-03 | 南京邮电大学 | Lock detection circuit for charge pump phase locked loop frequency synthesizer |
| CN106209079A (en) * | 2016-07-05 | 2016-12-07 | 中国电子科技集团公司第五十八研究所 | A kind of phase-locked loop circuit reducing the loop-locking time |
| CN111835344A (en) * | 2020-07-29 | 2020-10-27 | 展讯通信（上海）有限公司 | Phase-locked loop circuit and terminal |
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