CN101159433A - Fast locked phase-locked loop circuit - Google Patents
Fast locked phase-locked loop circuit Download PDFInfo
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- CN101159433A CN101159433A CNA2006100630270A CN200610063027A CN101159433A CN 101159433 A CN101159433 A CN 101159433A CN A2006100630270 A CNA2006100630270 A CN A2006100630270A CN 200610063027 A CN200610063027 A CN 200610063027A CN 101159433 A CN101159433 A CN 101159433A
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Abstract
The invention discloses a swift phase-lock loop circuit that includes frequency demodulation phase discriminator, charge pump, loop circuit wave filter, voltage controlled oscillator, frequency divider and swift locking circuit. The frequency demodulation phase discriminator receives input signal and feedback signal from the frequency divider and acquires their signal difference; the charge pump responds to the signal difference, charges and discharges the loop circuit filtering circuit. The output voltage of the loop circuit wave filter controls the voltage-controlled oscillator to generate phase-lock loop output signal which is fed back to the input end of the frequency demodulation phase discriminator after frequency demultiplication through the frequency divider. The swift locking circuit responds to the signal difference outputted from the frequency demodulation phase discriminator. When the phase-lock loop circuit nears the lockdown state, only charge pump with lower current charge/discharge the loop circuit wave filter; when the frequency difference between the input signal and the feedback signal from the frequency divider is significant, charge pump with higher current will be used to charge/discharge the loop circuit wave filter. The invention has enhanced the locking speed for the phase-lock loop circuit under the precondition that the stability of the system is ensured.
Description
[technical field]
The present invention relates to a kind of phase-locked loop circuit, more particularly, relate to and a kind ofly provide the charging and discharging electric currents of different sizes to realize the phase-locked loop circuit of quick lock in to loop filter according to varying in size of frequency difference.
[background technology]
Phase-locked loop is crucial module in the integrated circuit (IC) design, is widely used in the communications field.Phase-locked loop mainly contains two aspect purposes: clock and data recovery and frequency synthesis.Present widely used phase-locked loop is charge pump phase lock loop CPPLL, shown in Fig. 1 (a), it comprises following module: phase frequency detector (is the frequency/phase detector, Phase Frequency Detector, PFD), charge pump (Charge-Pump, CP), loop filter (Loop Filter, Low PassFilter, LPF), voltage controlled oscillator (Voltage Controlled Oscillator, VCO) and frequency divider (Frequency Counter, Frequency Divider).Phase frequency detector is to be used for detecting phase place between input signal and the feedback signal and frequency (detected phase difference in fact just, accumulation by phase difference so detected frequency difference) difference, activate charge pump by this difference, then to loop low-pass filter circuit (integrating circuit) charge or discharge, the output voltage control VCO of loop filter produces the output signal (frequency-doubled signal) of phase-locked loop, feed back to the PFD input behind the pll output signal process frequency divider frequency division, make the output frequency of PLL reach N times (N is the frequency divider coefficient) of its frequency input signal gradually by the effect of feeding back.PFD is a kind of in the many phase discriminators of phase-locked loop, its output two signal UP (first signal) and DN (secondary signal).When input signal Fr was leading with respect to feedback signal Fv phase place, shown in Fig. 1 (b), two outputs of PFD were as follows: the rising edge of Fr makes UP generation rising edge and is high level, up to the rising edge arrival of Fv, makes UP produce trailing edge and also is low level.And DN can produce a rising edge when the rising edge of Fv, but because UP this moment is a high level, so DN produces a trailing edge at once, thereby has not just changed back to low level again when DN also enters high level fully, shows the mechanism of a PULSE.When the leading Fr of Fv phase place, the work of UP and DN is exchanged just.
In the frequency synthesis process, some system such as cell phone system need the quick switching between frequency, they need phase-locked loop can respond the variation of its incoming frequency or frequency divider numerical value fast and make output frequency reach target frequency fast, and the design of the phase-locked loop of quick lock in just becomes very important aspect in the circuit design like this.
Mainly determine by the time-delay three who is input to output the locking time of phase-locked loop by the resistance-capacitance parameter of loop filter, the charge/discharge current of charge pump and each module of phase-locked loop.General, the response speed of the phase frequency detector of phase-locked loop, voltage controlled oscillator and frequency divider is all than comparatively fast, so the lock speed of phase-locked loop is mainly determined i.e.: the resistance capacitance parameter of charge pump current and loop filter decision by the loop parameter of phase-locked loop.
The characteristic of phase-locked loop tends to be reflected by its some measurement parameters, and these parameters comprise: locking time T
LOCK, locking frequency domain scope (Pull-in range), unlocked frequency scope (lock outrange), output frequency shake (Jitter) or the like.And top these parameters are that natural frequency ω n and damping coefficient ζ decide by two other parameter of phase-locked loop mainly, and these two parameters are the most important things in the phase-locked loop design.Natural frequency and damping coefficient can be determined by the cycle of phase-locked loop equation, is example with the phase-locked loop (only containing the first-order loop filter) of a second order: set PFD﹠amp; The Gain of CP is Kpfd, and the Gain of loop filter is K
Loop, the Gain of VCO is K
Vco, the loop equation of phase-locked loop is as follows like this:
P
feedback＝(P
ref*K
pfd*K
loop*K
vco/NS)/(1+K
pfd*K
loop*K
vco/NS)[1]
K
loop＝(R
2+1/SC)，τ
2＝R
2*C[2]
ωn＝(K
vco*K
pfd/NC)
1/2[3]
ζ＝ω
n*τ2/2，T
lock≈2π/ω
n?[4]
Loop equation by second-order PLL as can be seen, its locking behavior can be explained by two kinds of systems: overdamp concussion system and damped vibration system.For overdamp concussion system, ζ is bigger and ω n is less; ω n is bigger for the ζ of damped vibration system is smaller.General, the concussion locking system of phase-locked loop mainly belongs to the damped vibration system, can have following formula to represent:
θe＝θe_initial*e
-βt*cos(ωt)[5]
β＝ζ*ωn ω＝(ωn
2-β
2)
1/2[6]
Wherein θ e_initial is phase-locked loop signal difference between input signal and the feedback signal when just having begun to carry out phase locking.The phase locking time of phase-locked loop is closely related with β ω, little for being become locking time try one's best to reach quick lock in, need adjust natural frequency and damping coefficient preferably, make θ e in the formula [5] in the short as far as possible time, reach in the desired scope (it is qualified becoming 0.1% o'clock of input signal cycle as θ e), promptly realized quick lock in.
At present, when PLL (phase-locked loop) enters the phase locking process, do not have very good way to reduce locking time effectively, and in locking time occupy very most proportion at PLL the locking time of phase place, this makes the lock speed of phase-locked loop have no idea further to improve.
[summary of the invention]
At the problems referred to above, the object of the present invention is to provide a kind of phase-locked loop of locking can realized fast, and after locking is finished system stability better, (ripple) is less for burr; Do not bring the significantly increase of phase-locked loop area simultaneously.
To achieve these goals, the invention provides a kind of phase-locked loop circuit of quick lock in, comprise phase frequency detector, charge pump, loop filter, voltage controlled oscillator and frequency divider, the feedback signal of described phase frequency detector receiving inputted signal and frequency divider, and obtain their signal difference, charge pump responds this signal difference, the loop filtering circuit is carried out charging and discharging, the output voltage control voltage controlled oscillator of described loop filter produces pll output signal, feed back to the phase frequency detector input behind the described pll output signal process frequency divider frequency division, this phase-locked loop circuit also comprises the quick lock in circuit, the signal difference of described quick lock in circuit response phase frequency detector output, be used for when described phase-locked loop circuit approach locking state, little electric current charge pump is only arranged to the loop filter charge/discharge, when the frequency difference between the feedback signal of input signal and frequency divider is big, then increase large-current electric lotus pump to the loop filter charge/discharge.
Described quick lock in circuit comprises one or more branch roads, each branch road comprises control circuit and additional charge pump, described control circuit is used to respond the output of phase frequency detector, the charging start and end time of control additional charge pump, and described additional charge delivery side of pump is coupled to loop filter.
Wherein, described control circuit comprises and is used to detect first of phase frequency detector output phase difference, two phase difference comparison circuit, be used to control first of the charge/discharge duration, two charging and discharging time control circuits, first, two latch controllers, the described first phase difference comparison circuit and the first charging and discharging time control circuit respond first signal of phase frequency detector output respectively, its output is coupled to first latch controllers, the output of described first latch controllers is coupled to the additional charge pump, the described second phase difference comparison circuit and the second charging and discharging time control circuit respond the secondary signal of phase frequency detector output respectively, its output is coupled to second latch controllers, and the output of described second latch controllers is coupled to the additional charge pump.
Wherein, described first, second phase difference comparison circuit is identical circuit, comprise first delay unit and and logic control circuit, the input of described first delay unit and the signal difference of exporting with the first input end response phase frequency detector of logic control circuit (i.e. first signal), the output of described first delay unit is coupled to second input with logic control circuit.
Preferred version is: the time-delay of first delay unit of described N branch road is greater than the time-delay of first delay unit of N-1 branch road, and wherein N is the integer greater than 1.
Wherein said second delay unit is the even number CMOS reverser of series connection.
Wherein said first, second charging and discharging time control circuit is identical circuit, comprise second delay unit and NOR gate, the signal difference of the input of described second delay unit and the output of the first input end of NOR gate response phase frequency detector, the output of described second delay unit is coupled to second input of NOR gate.
Preferred version is: the time-delay of described second delay unit is chosen and can be shortened with the increase of charge pump charging current.
Wherein, described first, second latch controllers is the RS latch.
The invention has the beneficial effects as follows: the phase-locked loop circuit of quick lock in provided by the present invention strengthens charging current Icp when phase-locked loop need lock onto a new frequency, makes phase-locked loop very fast near new frequency; At phase-locked loop near new frequency and during the approach locking state, commutation circuit reduces charging current Icp, thereby suitable increase damping coefficient can be stabilized under the new frequency phase-locked loop, thereby has improved the speed that latchs of phase-locked loop circuit under the prerequisite that guarantees the stability of a system.The present invention make full use of be not used to charge/discharge in the pll lock process time (in the phase locking process of phase-locked loop, the time that is used for charge/discharge is smaller at shared proportion of the phase locking time of phase-locked loop, the logic level values of " UP or DN " is a high level during this period of time, thereby has reduced the phase locking time of PLL and the locking time of whole PLL effectively.
Feature of the present invention and advantage will be elaborated in conjunction with the accompanying drawings by embodiment.
[description of drawings]
Fig. 1 (a) is the block diagram of existing charge pump phase-locked loop circuit;
Fig. 1 (b) is the sequential chart of the signal difference of phase frequency detector output and input signal, feedback signal;
Fig. 2 (a) is a functional-block diagram of the present invention;
Fig. 2 (b) is the block diagram of a branch road of quick lock in circuit among the present invention;
Fig. 2 (c) is the circuit diagram of the quick lock in circuit branch a kind of embodiment in road among the present invention;
Fig. 3 is the circuit diagram of phase difference comparison circuit of the quick phase-locked loop circuit of the embodiment of the invention;
Fig. 4 (a) and (b) for being used to prolong the analogous diagram of charge pump charge;
Fig. 5 (a) and (b), (c) and (d) be respectively the circuit diagram of realizing phase frequency detector, voltage controlled oscillator, frequency divider and loop filter in the preferred embodiment of the present invention;
Fig. 6 (a) and (b), (c) and (d) be respectively the embodiment of the invention begins lock condition from 0Hz simulation result figure;
Fig. 7 (a) and (b), (c) and (d) be respectively the embodiment of the invention begins lock condition from 1GHz simulation result figure.
[embodiment]
Existing relational expression about locking time and relevant parameter shows, the square root relation of being inversely proportional to of locking time and Icp (charging current), promptly along with the increase of charging current Icp, can diminish locking time, therefore the present invention adopts following technical scheme: functional-block diagram is shown in Fig. 2 (a), increase a quick lock in circuit in parallel, when phase-locked loop need lock onto a new frequency, strengthen Icp, phase-locked loop is comparatively fast changed near the new frequency with charge pump; When phase-locked loop approach locking state, commutation circuit reduces Icp, thereby increases damping coefficient, and phase-locked loop can be stabilized under the new frequency.
A preferred embodiment of quick lock in circuit is, wherein two branch roads have been set at the frequency difference of input signal and feedback signal, each branch road comprises control circuit and additional charge pump, control circuit is used to respond the output of phase frequency detector, the charging start and end time of control additional charge pump, and the additional charge delivery side of pump is coupled to loop filter.Control circuit comprises two branch branch roads, responds the output first and second signal UP and the DN of phase frequency detector respectively, and two branch branch roads have identical circuit connection structure, and two inputs of additional charge pump are coupled in its output, shown in Fig. 2 (b).Each branch branch road comprises phase difference comparison circuit 1, is used to control charging and discharging time control circuit 2, latch controllers 3 and the additional charge pump 4 of charge/discharge duration shown in Fig. 2 (c), phase difference comparison circuit 1 and charging and discharging time control circuit 2 respond the signal UP or the DN of phase frequency detector output respectively, its output is coupled to latch controllers 3, and the output of latch controllers 3 is coupled to additional charge pump 4.The charge pump of two branch roads adds original charge pump, always has three charge pumps, and its electric current is respectively Icp1, Icp2, Icp3, is used for different phase loop filter is carried out charge or discharge.Locking when Icp1 is for phase-locked loop approach locking the state here and stable electric current that provides (electric charge) of phase-locked loop is provided.Icp2 for phase-locked loop frequency near new frequency but the charging and discharging currents (this electric current can be very not big yet) that the locking of phase place when still having than big-difference provides, the total current that provide for loop filter this moment is Icp1+Icp2.Locking when Icp3 has than big-difference for frequency provides electric current.The total current that provide for loop filter this moment is Icp1+Icp2+Icp3.In the present embodiment, particularly, Icp2 is 2 times of Icp1, and Icp3 is 20 times of Icp1.Obviously, also can adopt other Icp2 and Icp3 value.
It is to be noted that Icp1 is present in the course of work of phase-locked loop always, Icp2 also can occur when Icp3 occurred, and Icp3 may not occur when Icp2 occurred.
The control signal of Icp1 is output signals UP and the DN of PFD, and the control signal of Icp2, Icp3 is obtained through circuit conversion by UP and DN.The foundation of conversion is as follows: frequency difference can be reflected by the output signal of PFD, must cause that when frequency difference is big UP or DN are the chronic of high level.Frequency difference can be reflected by phase difference, must cause very big phase difference when frequency difference is big.Can judge the residing operating state of phase-locked loop by the length of this high level time, thereby whether decision Icp2 and Icp3 work.
Certainly, the quick lock in circuit also can be the branch road of other quantity as the case may be.
Below specify the formation of the quick phase-locked loop circuit that constitutes present embodiment.
1) phase difference comparison circuit
The phase difference comparison circuit of each branch road is divided into the first phase difference comparison circuit and the second phase difference comparison circuit, the first phase difference comparison circuit has identical circuit structure with the second phase difference comparison circuit, it is the input signal difference, the first phase difference comparison circuit meets the signal UP of phase frequency detector output, the second phase difference comparison circuit meets the signal DN of phase frequency detector output, each phase difference comparison circuit is shown in Fig. 2 (c), comprise first delay unit 11 and with logic control circuit 12, the input of first delay unit 11 and the signal UP or the DN that export with the first input end response phase frequency detector of logic control circuit 12, the output of first delay unit 11 is coupled to second input with logic control circuit 12.
First delay unit of two branch roads is designed to different time-delay DELAY_CELL2 and DELAY_CELL3, is used to determine Icp2 and Icp3 just start working under greater than which type of phase difference.When phase difference during greater than top a certain delay line, produce a control signal, making electric current is the charge pump charge or discharge of Icp2 or Icp3.It realizes circuit as shown in Figure 3, and inverter is an even number, and the design of DELAY_CELL is vital, and it has determined whether phase-locked loop systems can be stablized.According to inventor's emulation experiment, the unlocking condition of Icp2 or Icp3 is that 1/32 or 1/16 of input signal cycle Tref gets final product.
With first branch road is that example describes, the phase difference comparison circuit determines at first whether phase-locked loop approaches its lock-out state, if phase-locked loop is when lock-in state, it is very little very little that signal UP or DN are that the time of high level is bound to, when UP or DN are that time of high level is during greater than the DELAY_CELL2 of first delay unit, with logic control circuit 12 output high level.
2) charging and discharging time control circuit
The charging and discharging time control circuit of each branch road is divided into the first charging and discharging time control circuit and the second charging and discharging time control circuit, the first charging and discharging time control circuit has identical circuit structure with the second charging and discharging time control circuit, it is the input signal difference, the first charging and discharging time control circuit meets the signal UP of phase frequency detector output, and the second charging and discharging time control circuit meets the signal DN of phase frequency detector output.Each charging and discharging time control circuit is shown in Fig. 2 (c), comprise: second delay unit 21 and NOR gate 22, the signal UP or the DN of the first input end response phase frequency detector output of the input of second delay unit 21 and NOR gate 22, the output of second delay unit 21 is coupled to second input of NOR gate 22.
Pass through the time of T2 again after the trailing edge (becoming low level by high level) of UP or DN is come after, the output of NOR gate becomes high level ".
When phase-locked loop was in Lock_in range, mainly decided by Lock time its locking time, by Fig. 4 (a) and (b), as can be seen, the time of charge/discharge all very short (comparing) in this section locking process with an incoming frequency Fref cycle.It is the change of small frequency that phase-locked loop frequency changes majority, and the locking process major part is all in Lock-in range.Those skilled in the art can know from known technology general knowledge, under the preceding topic of the damping coefficient ζ of less change phase-locked loop circuit, increase the charging interval in each cycle, make ω diminish and rate of change bigger, thereby phase difference 0 the time of passing diminishes, after the process several times crossed 0, phase difference decayed in the desired scope, promptly reaches lock-out state.Through the compromise between the time of a zero passage number of times and zero passage, can reduce the locking time of phase-locked loop thereupon.Based on such principle, the present invention has designed a kind of circuit, can so that UP and DN charge pump still can charge/discharge a period of time when being " 0 ", thereby reduced the needed time of locking effectively.Sort circuit is applied to additional charge pump (Icp2) and additional charge pump (Icp3), and can not be used to keep the Icp1 of stabilized.In the present invention, according to inventor's emulation experiment, the time of the charging that prolongs for charge pump 2 is Tref/4, is Tref/16 for charge pump 3 prolongs the charging intervals.
3) latch controllers
The latch controllers of each branch road also is divided into first latch controllers and second latch controllers, first latch controllers has identical circuit structure with second latch controllers, wherein first latch controllers responds the output of the first phase difference comparison circuit and the first charging and discharging time control circuit, and second latch controllers responds the output of the second phase difference comparison circuit and the second charging and discharging time control circuit.
Latch controllers is produced by following two conditions: a) when begin charge/discharge; B) charge/discharge how long.Design a circuit with charging and discharging time control circuit output out and phase difference comparison circuit output CTRL1 as input, can produce above effect.Its circuit diagram is shown in Fig. 2 (c), the main structure of circuit is that a RS latch (is Latch, latch circuit,), it has realized time surface function: when UP/DN during greater than DELAY_CELL2 or DELAY_CELL3, shows that phase-locked loop frequency of living in (phase place) and target frequency (phase place) have than big difference for time of " 1 ", phase difference comparison circuit output high level, this part is used for control and opens Icp2 and Icp3, and the output hopping of latch controllers is a high level, is " 1 " expression with Output.When Output is " 1 ", after UP/DN becomes " 0 " a period of time (time that second delay unit is postponed), charging and discharging time control circuit output high level, the output hopping of latch controllers is a low level, be that Output can become " 0 ", expression Icp2 and Icp3 are closed.
How much time that the charging and discharging time control circuit is determining the additional charge pump to open has, i.e. when decision turns off the additional charge pump, and making it neither charges does not discharge yet.If the time-delay of first delay unit of phase difference comparison circuit is T1a, the time-delay of second delay unit of charging and discharging time control circuit is T1b, the time of then opening is to calculate like this: opening of additional charge pump is that time-delay from signal UP or DN begins during greater than T1a, and at this moment the output UP2 of latch controllers can be put high level.The time of closing is such: when signal UP or DN transferred low level to, the output UP2 of latch controllers or DN2 can be changed to low level after the time-delay of T1b.The whole like this charging and discharging time become (the flat time-delay of the height point of UP+T1b-T1a) or (the height point of DN is flat delays time+T1b-T1a).
For realizing above-mentioned charging and discharging requirement, additional charge pump one-level one-level is opened, the time-delay of first delay unit of phase difference comparison circuit should be increasing, and promptly the T1a of the 3rd group of circuit should be greater than the T1a of second group of circuit.
The time-delay of second delay unit of charging and discharging time control circuit is also relevant with charging current, and charging current is big more, and delay time can be chosen short more, the charging interval (Extra time) that promptly reduces fast circuit and increased.
The design also can cooperate the design as the control circuit of Icp2 and Icp3 of circuit that charge pump current changes with phase difference, and to reach lock speed quickly, this technology is the known technology of this area, is not described in detail in this.
The principle of quick lock in of the present invention is exactly that the control voltage of VCO can produce bigger a little variations along with the variation of phase difference, thereby output frequency can change and change along with phase difference faster.
The electric current that at first increases charge pump can (UP or DN are the time of high level) make that VCO control change in voltage is bigger in the identical time, thereby frequency change is also very big, and then can enter the less state of frequency difference between input signal and the feedback signal fast.When frequency difference was very little between input signal and the feedback signal, charge pump current must reduce, otherwise VCO control voltage can vibrate near phase-lock-ring output frequency vibration back and forth certain frequency just back and forth near certain voltage.(each phase-locked loop all can vibrate about the preset frequency of output, and what just shake varies in size, and this also is the main cause that Jitter produces.The pll lock state of our defined also is near the very little state of a kind of shake a certain frequency).The reducing to be reflected as in the design of charge pump current has only charge pump 1 in work, and its electric current is very little.It is directly controlled by UP/DN, makes phase-locked loop do extremely little shake (this shake can be interpreted as stabilized on certain frequency, does not shake) near certain frequency to keep, and is promptly stable.Phase-locked loop enters lock-out state.
Secondly, we can use the control voltage that the way that increases the charging and discharging time changes VCO faster.During the phase-locked loop approach locking, UP and DN are that the time of high level is all very short, thereby during this period, VCO control voltage changes all very little (because charge pump current can not be too big) in each input signal cycle, and UP/DN is that the low level time is all very long, if this section was also utilized for the low level time, charge with the another one charge pump, make VCO control voltage can change big (promptly very fast), phase-locked loop frequency changes comparatively fast so, can enter lock-out state fast equally.The time of charging and discharging is exactly (flat time-delay of the height point of UP+T1b-T1a) or (the flat time-delay of the height point of DN+T1b-T1a), and the ratio UP/DN that can regulate during this period of time is big a lot.This is the design's a main thought, and it is just auxiliary to increase charge pump current, makes locking time littler.
It should be noted that the design unsettled phenomenon can occur equally, similar with the wild effect effect that large-current electric lotus pump produces.But can make phase-locked loop circuit not produce concussion by regulating T1a and the size of T1b and the size of charge pump current, can make the stabilized as making charge pump current be reduced to suitable degree.
Above three parts formed the charge/discharge control of second charge pump (Icp2) and tricharged pump (Icp3) jointly.Through control, can make phase-locked loop operation under the state of optimizing to each delay unit time-delay.When locking, can access bigger Icp, after locking was finished, the stability of system was higher relatively, and burr can be smaller.
In the phase-locked loop of present embodiment, be achieved as follows as the circuit of each module of the formation phase-locked loop circuit indicated among Fig. 2 (a):
Phase frequency detector PFD has adopted TSPC (True Single-phase clock) structure, and circuit diagram is done like this and can be simplified circuit (metal-oxide-semiconductor use number is less) and make the PFD discriminability improve (the TSPC partial response is than very fast) shown in Fig. 5 (a).
Voltage controlled oscillator VCO adopts encircles the VCO that shakes, and can effectively save the VCO circuit area, and circuit diagram is shown in Fig. 5 (b), and its output frequency has the better linearity degree between 500MHz～1.8GHz between 10MHz～2GHz.
Frequency divider is an elementary cell with the Delay Flip-Flop that adopts the TSPC structure equally, cooperates combinational logic circuit, and realization can change the frequency divider of frequency divider coefficient, and circuit diagram is shown in Fig. 5 (c).
Loop filter adopts the second order integration filter, is burr (ripple) phenomenon that effective rejects trap output produces, and circuit diagram is shown in Fig. 5 (d).
The circuit of the present invention's design should be attached to PFD﹠amp; In the CP module, constitute a plurality of phase frequency detector structures, promptly produce three charge pumps of Icp1, Icp2 and Icp3 and control their phase place decision circuitry.Its overall circuit figure shown in Fig. 2 (a), need to prove, selecting the number of additional charge pump among this embodiment is two, is in order to reduce the complexity of phase-locked loop systems.In actual applications, the number of additional charge pump can come fixed as required, but charge pump of every increase, and phase-locked loop just increases a loop, causes the instability of phase-locked loop probably.Therefore under the prerequisite that has solved the stability of a system, can increase more charge pump as required.
Carry out experiment simulation to using phase-locked loop of the present invention, adopted SMIC 0.18um, the technology of 1.8V, the result adopts mode of comparing, be two groups altogether, be respectively: (1) 0 frequency begins to arrive preset frequency, and the result is as Fig. 6 (a) and (b), (c) with (d); (2) frequency (1GHz) from (relatively intermediate frequency) certain frequency difference arrives preset frequency (940MHz), and the result is as Fig. 7 (a) and (b), (c) with (d).
First group, above putting in order of three emulation be a charge pump, two charge pumps and three charge pumps successively, can see the Circuit lock that has three charge pumps optimum of fixing time, the frequency lock of two charge pumps and have only the frequency lock time difference of a charge pump few, but the phase locking time will be significantly better than the phase-locked loop that has only a charge pump, and Fig. 6 (d) is total effect contrast figure.
Second group, above putting in order of three emulation also be a charge pump, two charge pumps and three charge pumps successively, the channel frequency that has two charge pumps as can be seen obviously is better than the circuit of a charge pump locking time, and the circuit of three charge pumps is better than the circuit of two charge pumps slightly, and Fig. 7 (d) is total effect contrast figure.
The time that the phase-locked loop circuit that is used for quick lock in of the present invention can utilize pll lock process part to be wasted is locked in output signal on the preset frequency apace, and does not attract significantly increase on the area to phase-locked loop.Design is based on the technology of SMIC 0.18um, described phase-locked loop can be used for fields such as mobile communication.
Claims (9)
1. the phase-locked loop circuit of a quick lock in, comprise phase frequency detector, charge pump, loop filter, voltage controlled oscillator and frequency divider, the feedback signal of described phase frequency detector receiving inputted signal and frequency divider output, and obtain their signal difference, charge pump responds this signal difference, the loop filtering circuit is carried out charging and discharging, the output voltage control voltage controlled oscillator of described loop filter produces pll output signal, feed back to the phase frequency detector input behind the described pll output signal process frequency divider frequency division, it is characterized in that: this phase-locked loop circuit also comprises the quick lock in circuit, the signal difference of described quick lock in circuit response phase frequency detector output, be used for when described phase-locked loop circuit approach locking state, little electric current charge pump is only arranged to the loop filter charge/discharge, when the frequency difference between the feedback signal of input signal and frequency divider is big, then increase large-current electric lotus pump to the loop filter charge/discharge.
2. phase-locked loop circuit as claimed in claim 1, it is characterized in that: described quick lock in circuit comprises one or more branch roads, each branch road comprises control circuit and additional charge pump, described control circuit is used to respond the output of phase frequency detector, the charging start and end time of control additional charge pump, and described additional charge delivery side of pump is coupled to loop filter.
3. phase-locked loop circuit as claimed in claim 2, it is characterized in that: described control circuit comprises and is used to detect first of phase frequency detector output phase difference, two phase difference comparison circuit, be used to control first of the charge/discharge duration, two charging and discharging time control circuits, first, two latch controllers, the described first phase difference comparison circuit and the first charging and discharging time control circuit respond first signal of phase frequency detector output respectively, its output is coupled to first latch controllers, the output of described first latch controllers is coupled to the additional charge pump, the described second phase difference comparison circuit and the second charging and discharging time control circuit respond the secondary signal of phase frequency detector output respectively, its output is coupled to second latch controllers, and the output of described second latch controllers is coupled to the additional charge pump.
4. phase-locked loop circuit as claimed in claim 3, it is characterized in that: described first, second phase difference comparison circuit is identical circuit, comprise first delay unit and and logic control circuit, the input of described first delay unit and respond first signal with the first input end of logic control circuit, the output of described first delay unit is coupled to second input with logic control circuit.
5. phase-locked loop circuit as claimed in claim 4 is characterized in that: the time-delay of first delay unit of described N branch road is greater than the time-delay of first delay unit of N-1 branch road, and wherein N is the integer greater than 1.
6. phase-locked loop circuit as claimed in claim 5 is characterized in that: described second delay unit is the even number CMOS inverter of series connection.
7. phase-locked loop circuit as claimed in claim 5, it is characterized in that: described first, second charging and discharging time control circuit is identical circuit, comprise second delay unit and NOR gate, the output of described second delay unit of first signal of the input of described second delay unit and the output of the first input end of NOR gate response phase frequency detector is coupled to second input of NOR gate.
8. phase-locked loop circuit as claimed in claim 7 is characterized in that: the time-delay of described second delay unit is chosen and can be shortened with the increase of charge pump charging current.
9. phase-locked loop circuit as claimed in claim 7 is characterized in that: described first, second latch controllers is the RS latch.
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| CN2006100630270A CN101159433B (en) | 2006-10-08 | 2006-10-08 | Fast locked phase-locked loop circuit |
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