CN105634475B - A kind of charge pump ring-oscillating phase-locking ring - Google Patents
A kind of charge pump ring-oscillating phase-locking ring Download PDFInfo
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- CN105634475B CN105634475B CN201510980579.7A CN201510980579A CN105634475B CN 105634475 B CN105634475 B CN 105634475B CN 201510980579 A CN201510980579 A CN 201510980579A CN 105634475 B CN105634475 B CN 105634475B
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
- H03L7/1072—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the charge pump, e.g. changing the gain
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
The present invention relates to a kind of charge pump ring-oscillating phase-locking rings.Charge pump ring-oscillating phase-locking ring includes phase frequency detector, charge pump group, automatic biasing loop filter, frequency divider and quick lock in device.Wherein phase frequency detector, charge pump group, automatic biasing loop filter and frequency divider constitute the first feedback control loop, automatic biasing loop filter, frequency divider and quick lock in device constitute the second feedback control loop, and two feedback control loops realize the connection of nested type by automatic biasing loop filter.The first feedback control loop in the present invention is the work loop of stabilized state, and the second feedback control loop is quick lock in loop, and the coarse regulation ability of the second feedback control loop significantly improves the lock speed of phaselocked loop.The present invention uses automatic biasing technology to avoid resistance device is used also in multiple internal structures simultaneously, significantly reduces the output jitter of charge pump ring-oscillating phase-locking ring and the process dependency to processing procedure.
Description
Technical field
The present invention relates to a kind of phaselocked loop more particularly to a kind of charge pump ring-oscillating phase-locking rings.
Background technology
Charge pump ring-oscillating phase-locking ring is a kind of common phase-locked loop structures, generally comprises phase frequency detector, charge pump, low
Bandpass filter, voltage controlled oscillator and frequency divider.Charge pump ring-oscillating phase-locking ring is differentiated in locking process by phase frequency detector
Go out the phase-difference control charge pump of input clock signal and signal after phaselocked loop output clock division, charge pump generates correspondence
Voltage is controlled, after control voltage inhibits steady-state error by low-pass loop filter, control voltage controlled oscillator is from low frequency to high frequency
Oscillation.In phase-locked loop circuit, phase frequency detector, charge pump, low-pass filter, voltage controlled oscillator and frequency divider form one
Reponse system, the reponse system is when reference clock is consistent with feedback signal phase or one fixed value of difference, by locking phase
Ring locks.Therefore by phase-locked loop circuit, frequency can be generated and phase is locked into the output signal of fixed frequency and phase.
Under normal conditions, charge pump ring-oscillating phase-locking ring need phase frequency detector adjustment charge pump control ring shake from low frequency to
The higher-order of oscillation, since original frequency is relatively low, phaselocked loop needs longer time that could enter locking.And losing lock once occurs, it is whole
A phaselocked loop reenters stable state and still needs the long period.On the other hand, traditional charge pump ring-oscillating phase-locking ring is adopted
With the low pass model of resistance/capacitance structure loop filter, the loop bandwidth and damping factor of phaselocked loop are a fixed values, because
, there is increasing with output frequency, bandwidth is insufficient and shakes the problem of increasing for this.Meanwhile traditional charge pump loop oscillation type locking phase
Ring needs ring is maintained to shake linear in working band, therefore also need to benchmark and shake stable oscillation stationary vibration for ring, needs consumption additional
Area and power consumption.
Invention content
The technical problem to be solved in the present invention is to provide it is a kind of can quick lock in, the low phaselocked loop of shake,.
The technical solution adopted by the present invention to solve the technical problems is：A kind of charge pump ring-oscillating phase-locking ring, including mirror
Frequency phase discriminator, charge pump group, automatic biasing loop filter, adaptive quick lock in device, voltage controlled oscillator and frequency divider, the electricity
Lotus pump group is made of the first charge pump and the second charge pump in parallel, and it is anti-that first is provided in the charge pump ring-oscillating phase-locking ring
Present loop and the second feedback control loop；The phase frequency detector, charge pump group, automatic biasing loop filter, voltage controlled oscillator and point
Frequency device is sequentially connected, and the output end of frequency divider is connected with the input terminal of phase frequency detector, and the charge pump loop oscillation type is constituted with this
First feedback control loop of phaselocked loop；The input of the output end access automatic biasing loop filter of the adaptive quick lock in device
End, the output end of the frequency divider are also connected with the input terminal of adaptive quick lock in device, the adaptive quick lock in device, self-bias
Set the second feedback control loop that loop filter, voltage controlled oscillator and frequency divider constitute the charge pump ring-oscillating phase-locking ring.
The input terminal of the phase frequency detector receives the sub-frequency clock signal of input clock signal and frequency divider output simultaneously,
The output end of the phase frequency detector is respectively to the first charge pump and the second charge pump output control signal, first charge pump
Output end merge with the output end of adaptive quick lock in device connection after access automatic biasing loop filter, second charge
The output end of pump is independently accessed automatic biasing loop filter.
The charge pump ring-oscillating phase-locking ring is capable of providing reset signal RST to phase frequency detector, adaptive quick lock in
Device, automatic biasing loop filter and frequency divider make phase frequency detector, adaptive quick lock in device, automatic biasing loop filter and divide
Frequency device is in reset state, and the adaptive quick lock in device is capable of providing enable signal to phase frequency detector, the first charge pump
With the second charge pump control phase frequency detector, the first charge pump and the second charge pump unlatching/closing.
Specifically, the automatic biasing loop filter includes first switch capacitance, second switch capacitance, third switch electricity
Appearance, the first automatic biasing generator, the second automatic biasing generator and third automatic biasing generator；The first switch capacitance, second
Switching capacity and third switching capacity structure having the same, each switching capacity by a transistor and with the transistor
The grid of the capacitance composition of drain electrode connection, transistor connects reset signal, and the source electrode of transistor connects power supply；First switch capacitance
The first capacitance and the exporting of the first charge pump, the output of adaptive quick lock in device and the input of the first automatic biasing generator connect
It connects；Second capacitance of the second switch capacitance and output of the second charge pump, the input of the second automatic biasing generator and the first self-bias
Set the output connection of generator；The output of the third capacitance of third switching capacity and the second automatic biasing generator and third automatic biasing
The input of generator connects；Third automatic biasing generator generates control signal and exports to voltage controlled oscillator.
Further, the first automatic biasing generator, the second automatic biasing generator and third automatic biasing generator architecture
Identical, each automatic biasing generator includes the amplifier of Differential Input, the first balanced load, the second balanced load and current mirror
Backfeed loop；The PMOS transistor M4 and PMOS transistor M5 that first balanced load is intercoupled by source electrode and drain electrode are formed, the
The PMOS transistor M6 and PMOS transistor M7 that two balanced loads are intercoupled by source electrode and drain electrode are formed；The one of the amplifier
The grid of end input connection PMOS transistor M4, the other end input while connecting the drain electrode of PMOS transistor M4, PMOS transistor
The grid of M5 and drain electrode, the drain electrode of NMOS transistor M8；The current mirror backfeed loop includes NMOS transistor M8 and NMOS brilliant
The output of the grid of body pipe M9, NMOS transistor M8, the grid of NMOS transistor M9 and amplifier is connected with each other, M8 and M9's
Source level is grounded；The drain electrode of the drain electrode output connection NMOS transistor M8 of first balanced load, the drain electrode output of the second balanced load
Connect the drain electrode of NMOS transistor M9；The source electrode of first balanced load and the second balanced load is all connected with power supply, PMOS transistor
Input terminal of the grid of M4 as automatic biasing generator, the output end of the grid of PMOS transistor M7 as automatic biasing generator.
Specifically, the adaptive quick lock in device include first frequency electric pressure converter, second frequency electric pressure converter,
Control compensator, comparator, benchmark and adaptive charge adjuster；The input of first frequency electric pressure converter connects frequency-dividing clock
And input clock, output connection comparator；The input of second frequency electric pressure converter connects input clock, output connection comparator
With control compensator；Comparator exports two complementary comparison result E and EN；The output connection control compensator of benchmark；It is adaptive
It answers charge adjuster while connecting comparator and control compensator.
Further, the first frequency electric pressure converter and second frequency electric pressure converter structure having the same, often
A FV convertor includes frequency discriminator, the 4th switching capacity, the 5th switching capacity, the 6th switching capacity and constant-current source；
4th switching capacity is made of transistor M25 and the 4th capacitance, and the 5th switching capacity is made of transistor M26 and the 5th capacitance,
6th switching capacity is made of transistor M27 and the 6th capacitance；The drain electrode of transistor M25 connects power supply, and grid connects frequency discriminator,
4th capacitance one end (C4) connects the drain electrode in the source and transistor M26 of M25, other end ground connection simultaneously；The grid of transistor M26 connects
Connect frequency discriminator, the drain electrode of drain electrode the 5th capacitance, constant-current source and transistor M27 of connection；5th capacitance (C5) other end is grounded；Crystal
The grid of pipe M27 connects reset signal, drain electrode the 6th capacitance of connection and output signal, the 6th capacitance (C6) other end ground connection；Institute
The control signal that the frequecy characteristic of input signal is converted to switch by frequency discriminator is stated, capacitance charge/discharge in switching capacity is controlled, it will
Signal frequency and the relationship of electric current are converted to voltage on capacitance.
Further, the control compensator include PMOS transistor M10, PMOS transistor M11, PMOS transistor M15,
PMOS transistor M16, NMOS transistor M12, NMOS transistor M13 and NMOS transistor M14；PMOS transistor M10 and PMOS
The source and drain of transistor M11 is connected, and source electrode accesses power supply；The grid connection second frequency electric pressure converter of PMOS transistor M11 is defeated
The voltage signal gone out, the grid of PMOS transistor M10 connect the drain electrode of the drain electrode and PMOS transistor M11 of its own；NMOS is brilliant
The leakage of the drain electrode and PMOS transistor M11 of the grid, PMOS transistor M10 of the drain electrode connection NMOS transistor M14 of body pipe M12
Pole, the drain electrode of the source electrode and NMOS transistor M14 of the grid connection NMOS transistor M13 of NMOS transistor M12, NMOS transistor
The source electrode of M12 is grounded；The source electrode of NMOS transistor M13 is grounded, and grid is controlled by the benchmark being connect with control compensator；PMOS is brilliant
The drain electrode of body pipe M15 accesses power supply, source electrode and the PMOS transistor M16 of PMOS transistor M15 with the drain electrode of PMOS transistor M16
The drain electrode of grid, NMOS transistor M14 of grid and PMOS transistor M16 of source electrode, PMOS transistor M15 be connected with each other shape
At the output of control compensator (SCB1).
Further, the adaptive charge adjuster includes voltage-controlled current source, the 7th switching capacity, bias voltage generation
Unit and channel switch；Bias voltage generates unit and is made of concatenated PMOS transistor M17 and PMOS transistor M18, PMOS
The source electrode and output signal of the drain electrode connection PMOS transistor M18 of transistor M17, the grid and PMOS of PMOS transistor M17 are brilliant
The grid of body pipe M18 connects and receives the enable signal of comparator output, and the source electrode of PMOS transistor M17 connects power supply, PMOS
The grounded drain of transistor M18；7th switching capacity includes transistor M23 and the 7th capacitance, and the source electrode of transistor M23 is grounded,
The drain electrode of transistor M23 connects power supply, and source electrode connects the 7th capacitance (C7), drain electrode the 7th capacitance of connection, grid by or gate logic
It is exported and is controlled by the E of reset signal and comparator simultaneously；Voltage-controlled current source includes four NMOS transistors, is NMOS crystal successively
The drain electrode of pipe M19 to NMOS transistor M22, the NMOS transistor M19 to NMOS transistor M22 are grounded, NMOS transistor
The grid of M19, the source electrode of NMOS transistor M19, the grid of NMOS transistor M20 and NMOS transistor M21 grid receive it is inclined
Set the output signal of voltage generating unit；The source electrode of NMOS transistor M20 connects the 7th capacitance with the source electrode of NMOS transistor M22
And output is formed, which connects automatic biasing loop filter；Channel switch is made of transistor M24, the source electrode of transistor M24
The output of connection control compensator, grid connect the E outputs of comparator, the source electrode and NMOS of drain electrode connection NMOS transistor M21
The grid of transistor M22.
The beneficial effects of the invention are as follows：(1) present invention introduces two feedback control loops in phaselocked loop, and the first feedback control loop is
The work loop of stabilized state, the second feedback control loop are quick lock in loop, the coarse regulation ability of the second feedback control loop
Significantly improve the lock speed of phaselocked loop；Meanwhile adaptive quick lock in device in phase-locked loop circuit because of the excessive hair of frequency departure
After raw losing lock, stable state can be reentered by Acceleration of starting phaselocked loop automatically.(2) automatic biasing loop filter of the present invention
Using non-resistance structure, which enables loop bandwidth and the damped coefficient of phaselocked loop with the increase of target frequency
And bandwidth is adjusted, reduce shake；The structure is not necessarily to that biased reference is arranged in rear class to ensure the linear of ring oscillation simultaneously；This
Outer automatic biasing loop filter is lower to the degree of dependence of technique due to without resistance, be more easy under different technique into
The shake increase that the temperature coefficient of resistance is brought has been evaded in row transplanting.
Description of the drawings
Present invention will be further explained below with reference to the attached drawings and examples.
Fig. 1 is a kind of structural schematic diagram of charge pump ring-oscillating phase-locking ring of the present invention.
Fig. 2 is automatic biasing loop filter structure schematic diagram.
Fig. 3 is automatic biasing generator architecture schematic diagram.
Fig. 4 is adaptive quick lock in device structural schematic diagram.
Fig. 5 is FV convertor structural schematic diagram.
Fig. 6 is control compensator structure schematic diagram.
Fig. 7 is adaptive charge adjuster structural schematic diagram.
1- automatic biasings loop filter, 11- current mirrors backfeed loop, the adaptive quick lock in devices of 2-, 21- constant currents in figure
Source.
Specific implementation mode
In conjunction with the accompanying drawings, the present invention is further explained in detail.These attached drawings are simplified schematic diagram, only with
Illustration illustrates the basic structure of the present invention, therefore it only shows the composition relevant to the invention.
As shown in Figure 1, a kind of charge pump ring-oscillating phase-locking ring of the present invention includes phase frequency detector PFD, charge pump group, self-bias
Loop filter 1, adaptive quick lock in device 2, voltage controlled oscillator VCO and frequency divider N/D are set, the charge pump group is by parallel connection
First charge pump CP1 and the second charge pump CP2 are constituted, be provided in the charge pump ring-oscillating phase-locking ring the first feedback control loop and
Second feedback control loop.
The phase frequency detector PFD, charge pump group, automatic biasing loop filter 1, voltage controlled oscillator VCO and frequency divider N/D
It is sequentially connected, the output end of frequency divider N/D is connected with the input terminal of phase frequency detector PFD, and charge pump loop oscillation type lock is constituted with this
First feedback control loop of phase ring.
The input terminal of the output end access automatic biasing loop filter 1 of the adaptive quick lock in device 2, the frequency divider
The output end of N/D is also connected with the input terminal of adaptive quick lock in device 2, the adaptive quick lock in device 2, the filter of automatic biasing loop
Wave device 1, voltage controlled oscillator VCO and frequency divider N/D constitute the second feedback control loop of charge pump ring-oscillating phase-locking ring.
The input terminal of the phase frequency detector PFD receives input clock F_CLKIN signals and frequency divider N/D outputs simultaneously
Frequency-dividing clock N_HCLK signals, the output end of the phase frequency detector PFD is respectively to the first charge pump CP1 and the second charge pump
The output end of the output end and adaptive quick lock in device 2 of CP2 output control signals UP/DOWN, the first charge pump CP1 closes
And access automatic biasing loop filter 1 after connecting, the output end of the second charge pump CP2 is independently accessed automatic biasing loop filtering
Device 1.
Charge pump ring-oscillating phase-locking ring of the present invention is capable of providing reset signal RST to phase frequency detector PFD, adaptive
Answer quick lock in device 2, automatic biasing loop filter 1 and frequency divider N/D make phase frequency detector PFD, adaptive quick lock in device 2,
Automatic biasing loop filter 1 and frequency divider N/D are in reset state, and the adaptive quick lock in device 2 is capable of providing enabled letter
Number EN is to phase frequency detector PFD, the first charge pump CP1 and the second charge pump CP2 control phase frequency detectors PFD, the first charge pump
CP1 and the second charge pump CP2 unlatchings/closing.
First feedback control loop of charge pump ring-oscillating phase-locking ring of the present invention is the building ring of stabilized state
Road, the second feedback control loop are quick lock in loop.In original state or after receiving RST reset signals, adaptive quick lock in device 2
The first feedback control loop is closed, voltage controlled oscillator VCO frequency approaches target frequency is quickly enabled by the second feedback control loop；It shakes with voltage-controlled
The frequency of oscillation of device VCO is swung close to target frequency, adaptive quick lock in device 2 opens phase frequency detector PFD and charge pump group, by
The control signal that charge pump group generates control phaselocked loop after the filtering of automatic biasing loop filter 1 enters lock-out state.When because outer
Boundary's reason make phaselocked loop occur to deviate suddenly target frequency is larger and the duration be more than adaptive quick lock in device 2 resolution window
When mouth, adaptive quick lock in device 2 will be again switched off the first feedback control loop, and voltage controlled oscillator is enabled again by the second feedback control loop
The frequency of oscillation of VCO quickly approaches target frequency.When the first feedback control loop works, two charge pumps obtain frequency and phase discrimination simultaneously
The output frequency phase deviation information of device PFD, and charge is extracted/injects to respective output node according to the information, form two
The voltage of road fluctuation controls information；Two path control signal simultaneously enter automatic biasing loop filter 1, it is filtered after control letter
Number it is treated as 1 tunnel control signal, control voltage controlled oscillator VCO work.
The structure of automatic biasing loop filter 1 is as shown in Fig. 2, automatic biasing loop filter 1 is sent out by concatenated 3 grades of automatic biasings
Raw device composition, the input terminal per level-one automatic biasing generator connect a switching capacity being connect with power supply, are integrally formed one
The filter of adaptive-bandwidth.Switching capacity is controlled by reset signal, after reset signal discharges, the automatic biasing generator per level-one
A firstorder filter is constituted with the switching capacity of series connection with it, has been integrally formed 3 rank automatic biasing filters.First order automatic biasing
The input of generator while the output for being also connected with charge pump and adaptive quick lock in device 2, when adaptive quick lock in device 2 works
When charge air pump inoperative, by the automatic biasing filter that thtee-stage shiplock filter is constituted carry out control signal filtering；When frequency is forced
After close-target value, adaptive quick lock in device 2 is closed, two charge pump startups, wherein the control signal warp of the first charge pump CP1
Enter the second level, while the control signal of the second charge pump CP2 and the Signal averaging after crossing the processing of first order automatic biasing generator
Enter second level automatic biasing generator afterwards, the output of second level automatic biasing generator enters third level automatic biasing generator.It can be with
Find out, entire automatic biasing loop filter 1 does not have electric resistance structure, and the parameter of filter is by process deviation influence very little.
During the second feedback control loop works, the adaptive charge pump for accelerating lock 2 to simulate a low precision
And frequency and phase discrimination behavior, the control voltage change of the behavior is larger, therefore higher order filter can preferably handle control at this time
Signal processed, and then ensure that the work of voltage controlled oscillator VCO is linear.When the first backfeed loop works, two charge pumps in parallel
There is provided two-way completely the same control signal, the input on the second bias generator SG2 obtains one and occurs from the first biasing
The high-order compensation of device SG1, the automatic biasing loop filter 1 in this stage are the filter of 2 ranks, the equivalent input capacitance of bigger
Make the bandwidth bigger of filter at this time, entire phaselocked loop thus the loop tracks ability for obtaining adaptation high bandwidth.
The structure of automatic biasing generator as shown in figure 3, the balanced load of automatic biasing generator input stage by a pair of of source and drain phase
The PMOS transistor of mutual coupling forms, and the grid of two transistor connects the input of subsequent difference amplifier simultaneously, signal from its
In PMOS transistor grid input, the grid of another transistor and draining connects in a manner of diode.Automatic biasing is sent out
The output stage of raw device is also intercoupled by one group of source and drain and grid and drain electrode are connected into the PMOS transistor of diode pattern and form.From
The output stage of bias generator is connect with input stage by the current mirror backfeed loop 11 controlled by difference amplifier, and input is believed
It is number linear to be transmitted to output, one resistance behavior of simulation.
Adaptive 2 structure of quick lock in device is as shown in figure 4, two FV convertors monitor jointly with comparator CP1
The deviation of oscillator frequency and target frequency；Automatic biasing control compensator SCB1 provide compensation for adaptive charge adjustment unit
It releases control；A reference source controls compensator SCB1 for automatic biasing and provides stable operating condition；Adaptive charge adjuster ACC1
Simulate the behavior of a fast charge pump.When entire phaselocked loop in the initial state, target frequency corresponding conversion at voltage it is high
In the voltage that oscillator frequency is converted into, comparator CP1 can export the level higher than threshold value, corresponding to open adaptive charge adjustment
Device ACC1 simultaneously closes charge pump and phase frequency detector PFD, while larger voltage deviation can control compensator by automatic biasing
SCB1 accelerates charge and regulates the speed；When frequency of oscillation increases, automatic biasing control compensator SCB1 continuously decreases compensating proportion, into
And it reduces charge and regulates the speed；As frequency of oscillation is further approached, comparator CP1 outputs are less than the level of threshold value, charge tune
Whole device completely closes, while controlling inhibition of the signal release to charge pump and phase frequency detector PFD.
The structure of FV convertor frequency discriminator DF1, switching capacity and constant-current source 21 as shown in figure 5, be made of, frequency discrimination
The frequency characteristic of input signal is converted to the closure cyclophysis of switching capacity by device DF1, is existed by the charge and discharge of switching capacity
Voltage output is formed on the switching capacity of output stage.More particularly, each frequency discriminator DF1 inputs a clock to be measured simultaneously
CLK and reference clock REF_CLK respectively enters two d type flip flops.When measured frequency is less than reference frequency, the 4th switching capacity
The speed of the upper charge accumulateds of SC4 is less than the speed that the 5th switching capacity SC5 is discharged by constant-current source 21, output voltage values at this time
Far below target.With the rising for waiting for measured frequency, the 4th switching capacity SC4 charge accumulating rates increase.When accumulating rate with release
When putting speed and reaching balance, the charge of remaining progresses into the 6th switching capacity SC6 on the 5th switching capacity SC5.Work as time window
Mouth is accumulative full, and sufficiently high voltage is accumulated on the 6th switching capacity SC6, that is, thinks clock frequency to be measured close to reference clock frequency
Rate.
Automatic biasing controls structure such as Fig. 6 of compensator SCB1, automatic biasing control compensator SCB1 include third balanced load,
4th balanced load and current feedback loop, two groups of balanced loads are all made of the PMOS transistor that source and drain intercouples, and are made
For the voltage of the grid receives frequency electric pressure converter output of PMOS transistor M11 in the 4th balanced load of input stage, PMOS
The grid of transistor M10 is connected with drain electrode in a manner of diode.As the third balanced load of output stage, two POMS crystal
The grid of pipe is connected, while drain is connected with each other as output；4th balanced load is connected to third balanced load by NMOS
The input stage and output stage for the adjustment type current source that transistor is constituted.4th balanced load converts input voltage into electric current, leads to
It crosses and is transmitted by the current source that NMOS transistor is constituted, be then converted to by third balanced load in output node stable
Voltage output.
The structure of adaptive charge adjuster ACC1 is as shown in fig. 7, adaptive charge adjuster ACC1 includes bias voltage
Generate unit VB1, voltage-controlled current source VCS1, switching capacity and channel switch S1.When set, enable signal EN is not yet in effect, pressure
Control current source controls the transistor M23 of the 7th switching capacity first, is the 7th capacitance C7 chargings, the bottom crown of the 7th capacitance C7
Identical charges can be accumulated rapidly.After enable signal EN is effective, bias voltage generates unit and generates bias voltage, the voltage starting
Master in voltage-controlled current source releases access, while the offset voltage that automatic biasing control compensator SCB1 is generated starts supplement channel
Charge discharging resisting access so that realize a fast charge pump in enable signal EN valid periods adaptive charge adjuster ACC1
Function.
To sum up, the present invention introduces adaptive quick lock in device 2 and second in the feedback loop construction of phaselocked loop and feeds back
Loop reduces the locking time consumption of phaselocked loop；Meanwhile adaptive quick lock in device 2 in phase-locked loop circuit because of frequency departure mistake
After big generation losing lock, stable state can be reentered by Acceleration of starting phaselocked loop automatically.On the other hand, automatic biasing of the present invention
For loop filter 1 using non-resistance structure, which enables loop bandwidth and the damped coefficient of phaselocked loop with mesh
It marks the increase of frequency and adjusts bandwidth, reduce output jitter, while the connection structure of its automatic biasing so that in the first feedback control loop
And second have different bandwidth and stopband attenuation feature under feedback control loop both of which, adapts to different operating modes.
It is enlightenment with above-mentioned desirable embodiment according to the present invention, through the above description, relevant staff is complete
Various changes and amendments can be carried out without departing from the scope of the technological thought of the present invention' entirely.The technology of this invention
Property range is not limited to the contents of the specification, it is necessary to determine its technical scope according to right.
Claims (6)
1. a kind of charge pump ring-oscillating phase-locking ring, it is characterized in that：Including phase frequency detector（PFD）, charge pump group, automatic biasing loop
Filter（1）, adaptive quick lock in device（2）, voltage controlled oscillator（VCO）And frequency divider（N/D）, the charge pump group is by parallel connection
The first charge pump（CP1）With the second charge pump（CP2）It constitutes, the first feedback is provided in the charge pump ring-oscillating phase-locking ring
Loop and the second feedback control loop；
The phase frequency detector（PFD）, charge pump group, automatic biasing loop filter（1）, voltage controlled oscillator（VCO）And frequency divider
（N/D）It is sequentially connected, frequency divider（N/D）Output end and phase frequency detector（PFD）Input terminal be connected, the electricity is constituted with this
Lotus pumps the first feedback control loop of ring-oscillating phase-locking ring；
The adaptive quick lock in device（2）Output end access automatic biasing loop filter（1）Input terminal, the frequency divider
（N/D）Output end be also connected with adaptive quick lock in device（2）Input terminal, the adaptive quick lock in device（2）, automatic biasing
Loop filter（1）, voltage controlled oscillator（VCO）And frequency divider（N/D）Constitute the charge pump ring-oscillating phase-locking ring second is anti-
Present loop；
The phase frequency detector（PFD）Input terminal simultaneously receive input clock（F_CLKIN）Signal and frequency divider（N/D）Output
Frequency-dividing clock（N_HCLK）Signal, the phase frequency detector（PFD）Output end respectively to the first charge pump（CP1）With second
Charge pump（CP2）Output control signal (UP/ DOWN), first charge pump（CP1）Output end and adaptive quick lock in
Device（2）Output end merge connection after access automatic biasing loop filter（1）, second charge pump（CP2）Output end list
Solely access automatic biasing loop filter（1）；
The charge pump ring-oscillating phase-locking ring is capable of providing reset signal RST to phase frequency detector（PFD）, adaptive quick lock in
Device（2）, automatic biasing loop filter（1）And frequency divider（N/D）Make phase frequency detector（PFD）, adaptive quick lock in device（2）,
Automatic biasing loop filter（1）And frequency divider（N/D）In reset state, the adaptive quick lock in device（2）It is capable of providing
Enable signal EN is to phase frequency detector（PFD）, the first charge pump（CP1）With the second charge pump（CP2）Control phase frequency detector
（PFD）, the first charge pump（CP1）With the second charge pump（CP2）Unlatching/closing；
The adaptive quick lock in device（2）Including first frequency electric pressure converter（F_V1）, second frequency electric pressure converter（F_
V2）, control compensator（SCB1）, comparator (CP1), benchmark（VR1）With adaptive charge adjuster（ACC1）；First frequency electricity
Pressure converter（F_V1）Input connect frequency-dividing clock（N_HCLK）And input clock（F_CLKIN）, output connection comparator
(CP1)；Second frequency electric pressure converter（F_V2）Input connect input clock（F_CLKIN）, output connection comparator (CP1)
With control compensator（SCB1）;Comparator (CP1) exports two complementary comparison result E and EN；Benchmark（VR1）Output connection
Control compensator（SCB1）；Adaptive charge adjuster（ACC1）Comparator (CP1) and control compensator are connected simultaneously（SCB1）.
2. a kind of charge pump ring-oscillating phase-locking ring according to claim 1, it is characterized in that：The automatic biasing loop filter
（1）Including first switch capacitance（SC1）, second switch capacitance（SC2）, third switching capacity（SC3）, the first automatic biasing generator
（SG1）, the second automatic biasing generator（SG2）With third automatic biasing generator（SG3）；The first switch capacitance（SC1）, second
Switching capacity（SC2）With third switching capacity（SC3）Structure having the same, each switching capacity by a transistor and with
The grid of the capacitance composition of the drain electrode connection of the transistor, transistor connects reset signal RST, the source electrode connection electricity of transistor
Source；First switch capacitance（SC1）The first capacitance（C1）With the first charge pump（CP1）Export, adaptive quick lock in device（2）
Output and the first automatic biasing generator（SG1）Input connection；Second switch capacitance（SC2）The second capacitance（C2）With second
Charge pump（CP2）Output, the second automatic biasing generator（SG2）Input and the first automatic biasing generator（SG1）Output connect
It connects；Third switching capacity（SC3）Third capacitance（C3）With the second automatic biasing generator（SG2）Output and third automatic biasing hair
Raw device（SG3）Input connection；Third automatic biasing generator（SG3）Control signal VCTL is generated to export to voltage controlled oscillator
（VCO）.
3. a kind of charge pump ring-oscillating phase-locking ring according to claim 2, it is characterized in that：It is according to claim 2
A kind of charge pump ring-oscillating phase-locking ring, it is characterized in that：The first automatic biasing generator（SG1）, the second automatic biasing generator
（SG2）With third automatic biasing generator（SG3）Structure is identical, and each automatic biasing generator includes the amplifier of Differential Input
（AP1）, the first balanced load（RP1）, the second balanced load（RP2）With current mirror backfeed loop（11）；First balanced load
（RP1）Including PMOS transistor M4 and PMOS transistor M5, the source of the source electrode and PMOS transistor M5 of the PMOS transistor M4
Pole intercouples, and the drain electrode of the PMOS transistor M4 and the drain electrode of PMOS transistor M5 intercouple；Second balanced load
（RP2）Including PMOS transistor M6 and PMOS transistor M7, the source of the source electrode and PMOS transistor M7 of the PMOS transistor M6
Pole intercouples, and the grid of the PMOS transistor M6, the grid of drain electrode and PMOS transistor M7, drain electrode intercouple；It is described
Current mirror backfeed loop（11）Including NMOS transistor M8 and NMOS transistor M9；The amplifier（AP1）In-phase end input
The grid of PMOS transistor M4 is connected, inverting input connects the drain electrode of PMOS transistor M4, the grid of PMOS transistor M5 simultaneously
The drain of pole and drain electrode, NMOS transistor M8；The grid of NMOS transistor M8, the grid and amplifier of NMOS transistor M9
（AP1）Output be connected with each other, the source level ground connection of M8 and M9；First balanced load（RP1）Drain electrode output connection NMOS crystal
The drain electrode of pipe M8, the second balanced load（RP2）Drain electrode output connection NMOS transistor M9 drain electrode；First balanced load
（RP1）With the second balanced load（RP2）Source electrode be all connected with power supply；The grid of PMOS transistor M4 is as automatic biasing generator
Input terminal, the output end of the grid of PMOS transistor M7 as automatic biasing generator.
4. a kind of charge pump ring-oscillating phase-locking ring according to claim 1, it is characterized in that：The first frequency voltage conversion
Device（F_V1）With second frequency electric pressure converter（F_V2）Structure having the same, each FV convertor include frequency discrimination
Device（DF1）, the 4th switching capacity（SC4）, the 5th switching capacity（SC5）, the 6th switching capacity（SC6）And constant-current source（21）；Its
In, frequency discriminator（DF1）It is constituted using two d type flip flops；4th switching capacity（SC4）By transistor M25 and the 4th capacitance（C4）
Composition, the 5th switching capacity（SC5）By transistor M26 and the 5th capacitance（C5）Composition, the 6th switching capacity（SC6）By transistor
M27 and the 6th capacitance（C6）Composition；The drain electrode of transistor M25 connects power supply, and grid connects frequency discriminator（DF1）；4th capacitance
（C4）One end connects the drain electrode in the source and transistor M26 of M25, other end ground connection simultaneously；The grid of transistor M26 connects frequency discriminator
（DF1）, source electrode the 5th capacitance of connection（C5）One end, constant-current source（21）With the drain electrode of transistor M27；5th capacitance（C5）The other end
Ground connection；The grid of transistor M27 connects reset signal RST, and source electrode connects the 6th capacitance（C6）One end and output signal；6th electricity
Hold（C6）The other end is grounded；The frequency discriminator（DF1）The frequecy characteristic of input signal is converted to the control signal of switch, is controlled
The relationship of signal frequency and electric current is converted to voltage on capacitance by the capacitance charge/discharge in switching capacity.
5. a kind of charge pump ring-oscillating phase-locking ring according to claim 1, it is characterized in that：The control compensator（SCB1）
Including PMOS transistor M10, PMOS transistor M11, PMOS transistor M15, PMOS transistor M16, NMOS transistor M12,
NMOS transistor M13 and NMOS transistor M14；PMOS transistor M10 is connected with the source and drain of PMOS transistor M11, source electrode access
Power supply；The grid of PMOS transistor M11 connects second frequency electric pressure converter（F_V2）The voltage signal of output, PMOS transistor
The grid of M10 connects the drain electrode of the drain electrode and PMOS transistor M11 of its own；The drain electrode connection NMOS of NMOS transistor M12 is brilliant
The grid of the drain electrode of the drain electrode and PMOS transistor M11 of the grid, PMOS transistor M10 of body pipe M14, NMOS transistor M12 connects
Connect the drain electrode of the source electrode and NMOS transistor M14 of NMOS transistor M13, the source electrode ground connection of NMOS transistor M12；NMOS transistor
The source electrode of M13 is grounded, grid by with control compensator（SCB1）The benchmark of connection（VR1）Control；The drain electrode of PMOS transistor M15
Drain electrode with PMOS transistor M16 accesses power supply, and the source electrode of PMOS transistor M15 and the source electrode of PMOS transistor M16, PMOS are brilliant
The grid of body pipe M15 and the drain electrode of the grid, NMOS transistor M14 of PMOS transistor M16 are interconnected to form control compensator
（SCB1）Output.
6. a kind of charge pump ring-oscillating phase-locking ring according to claim 1, it is characterized in that：The adaptive charge adjuster
（ACC1）Including voltage-controlled current source（VCS1）, the 7th switching capacity（SC7）, bias voltage generate unit（VB1）And channel switch
（S1）；Bias voltage generates unit（VB1）It is made of concatenated PMOS transistor M17 and PMOS transistor M18, PMOS transistor
The source electrode and output signal E_VB of the drain electrode connection PMOS transistor M18 of M17, the grid and PMOS crystal of PMOS transistor M17
The grid of pipe M18 connects and receives the enable signal EN of comparator (CP1) output, the source electrode connection electricity of PMOS transistor M17
Source, the drain electrode connection ground of PMOS transistor M18；
7th switching capacity（SC7）Including transistor M23 and the 7th capacitance（C7）, the drain electrode of transistor M23 connects power supply, and source electrode connects
Connect the 7th capacitance（C7）, grid by or gate logic simultaneously by the E of reset signal RST and comparator (CP1) export control；
Voltage-controlled current source（VCS1）It is NMOS transistor M19 to NMOS transistor M22, institute successively including four NMOS transistors
The drain electrode for stating NMOS transistor M19 to NMOS transistor M22 is grounded, grid, the NMOS transistor M19 of NMOS transistor M19
Source electrode, NMOS transistor M20 grid and NMOS transistor M21 grid receive bias voltage generate unit（VB1）It is defeated
Go out signal E_VB；The source electrode of NMOS transistor M20 connects the 7th capacitance with the source electrode of NMOS transistor M22（C7）And it is formed defeated
Go out, which connects automatic biasing loop filter（1）；
Channel switch（S1）It is made of transistor M24, the source electrode connection control compensator of transistor M24（SCB1）Output, grid
Pole connects the E outputs of comparator (CP1), the grid of the source electrode and NMOS transistor M22 of drain electrode connection NMOS transistor M21.
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| CN106130545B (en) * | 2016-06-17 | 2019-02-22 | 中国电子科技集团公司第五十八研究所 | A kind of automatic biasing PLL ruggedized construction of Anti-single particle radiation |
| CN108616271A (en) * | 2016-12-12 | 2018-10-02 | 中国航空工业集团公司西安航空计算技术研究所 | Phase locked loop fast lock circuit |
| CN109639272B (en) * | 2018-12-14 | 2023-06-09 | 北京时代民芯科技有限公司 | Self-adaptive broadband phase-locked loop circuit |
| CN110855291B (en) * | 2019-10-07 | 2024-05-03 | 珠海一微半导体股份有限公司 | Phase-locked acceleration circuit applied to phase-locked loop system and phase-locked loop system |
| CN112073065B (en) * | 2020-08-12 | 2023-03-14 | 西安电子科技大学 | Millimeter wave sub-sampling DDS (direct digital synthesizer) mixing decimal frequency division phase-locked loop structure |
| CN116155273B (en) * | 2023-04-17 | 2023-06-23 | 南京航空航天大学 | Injection locking frequency locking loop and method based on frequency-voltage conversion |
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