CN113054997B - Quick locking delay phase-locked loop - Google Patents
Quick locking delay phase-locked loop Download PDFInfo
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- CN113054997B CN113054997B CN201911360550.3A CN201911360550A CN113054997B CN 113054997 B CN113054997 B CN 113054997B CN 201911360550 A CN201911360550 A CN 201911360550A CN 113054997 B CN113054997 B CN 113054997B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
Abstract
The invention provides a fast-locking time-delay phase-locked loop circuit, which belongs to the technical field of integrated circuits and comprises a phase frequency detector, a charge pump, a low-pass filter, a voltage-controlled delay line and a frequency doubling circuit. The reference clock and the feedback clock enter the PFD, the PFD converts the phase difference between the reference clock and the feedback clock into pulse signals up and down with constant clock period, and the CP and the LPF further convert the pulse signals up and down into stable control signals vc. vc not only controls the delay time of the reference clock in the VCDL, but also feeds back the reference clock to the charge pump to adjust the current of the charge pump, so that after a limited number of clock cycles, the phase difference between the reference clock and the feedback clock is 0, and the purpose of phase locking is achieved. After the delay locked loop is locked, the output signal of the VCDL may be accessed to the frequency doubling circuit to obtain a frequency doubled signal.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and relates to a time delay phase-locked loop circuit which changes the charge and discharge current of a charge pump according to the voltage value so as to achieve quick locking.
Background
Today, the phase-locked loop is proposed to solve the problem of synchronous reception of the receiver, and especially the development of the spatial technology has greatly promoted the development of the phase-locked loop technology. The voltage-controlled delay line-based delay phase-locked loop is also concerned due to the excellent performance of the delay phase-locked loop, and has the characteristics of unconditional stability, strong anti-interference capability and the like.
The delay phase-locked loop can eliminate clock delay, realize zero transmission delay and minimize the deviation between a clock input signal and the internal clock of the whole chip. The time delay phase-locked loop not only has the function of phase locking, but also has the function of frequency multiplication.
The conventional delay-locked loop structure is shown in fig. 1, and the structure has the following disadvantages: firstly, the phase difference between two clocks needs to be continuously compared by the phase frequency detector with a tri-state structure, and the phase difference may be that a reference clock is ahead of a feedback clock or that the feedback clock is ahead of the reference clock, so that the whole phase frequency detector is complicated to work; second, the current of the conventional charge pump is a fixed current, which has no selectivity, easily causes system instability, and keeps the lock time of the dll conservative.
Disclosure of Invention
The invention provides a rapid locking delay phase-locked loop, aiming at overcoming the problems in the prior art, such as complex phase detection, one fixed current, conservative locking time and the like of a phase frequency detector.
The invention is realized by the following technical scheme:
a fast locking delay phase-locked loop comprises a Phase Frequency Detector (PFD), a Charge Pump (CP), a low-pass filter (LPF), a voltage-controlled delay line (VCDL) and a frequency doubling circuit; the phase frequency detector is used for comparing the phase difference between a reference clock and a feedback clock and generating output signals up and down with fixed clock period; the up signal and the down signal are used as input signals of the charge pump, and output voltage vc is generated through charging and discharging of a low-pass filter capacitor; the vc and the reference clock enter a voltage-controlled delay line to obtain multi-phase output clocks, wherein one output clock is fed back to the phase frequency detector and is used as an input clock of the phase frequency detector, namely a feedback clock; meanwhile, vc is fed back to the charge pump to control the current of the charge pump; and the multi-phase output of the voltage-controlled delay line passes through a frequency doubling circuit to obtain frequency doubling output.
Furthermore, the phase frequency detector structure consists of five D triggers; the five flip-flops are D1, D2, D3, D4 and D5 flip-flops respectively; the input reference clock and the feedback clock respectively perform AND operation with a control signal en to generate an rclk clock and a bclk clock, the rclk clock is used as the input clock of the D2 flip-flops, the D3 flip-flops and the D4 flip-flops, the reverse direction of the rclk clock is used as the reset signal of the D1 flip-flops, the bclk clock is used as the input clock of the D5 flip-flops, and the reverse direction of the bclk clock is used as the input clock of the D1 flip-flops; the D4 and D5 triggers form a traditional three-state structure phase frequency detector, so that up and down signals are output, and a buffer is arranged between reset signals of the up and down signals reaching the D triggers and used for increasing the reset time delay of the up and down signals reaching the D4 and D5 triggers.
Further, the charge pump is composed of a self-biasing structure and a core module; the self-bias structure is used for generating reference current, and the reference current generates reference voltage bias to be supplied to the core module as bias voltage, so that the core module generates the required bias current.
Further, the self-bias structure consists of a self-bias current, a comparator module and a selection module; the self-bias current has no input signal, generates a reference current inside the self-bias current, and generates a bias voltage signal b by the current to supply to the selection module as an input signal; the positive input end of the comparator is vref, the negative input end of the comparator is vc, the output result is used for being connected with the grid electrode of the selection module, the on and off of the grid electrode are controlled, and then the magnitude of the bias current is selected to be supplied to the core module.
Further, the self-bias current is composed of mos tubes M1, M2, M3 and M4 and a resistor R1, wherein the grid electrode of the M1 tube is connected with the drain electrode, and the grid electrode of the M2 and the drain electrode of the M3 are connected at the same time; the grid electrode and the drain electrode of the M4 tube are connected, the grid electrode of the M3 and the drain electrode of the M2 are simultaneously connected, and a resistor R is connected between the source electrode of the M3 and the ground;
the comparator module consists of M9, M10, M11, M12, M13, M14 and M15, wherein the positive input end of the comparator is connected with vref, and the negative input end of the comparator is connected with a control signal vc; vb is a tail power supply control signal, vb is respectively connected with the gates of M9 and M12, the drain of M9 is respectively connected with the sources of M10 and M11, M10 and M11 are input geminate transistors, the drain of M10 is respectively connected with the gate and the drain of M12, the drain of M11 is respectively connected with the drain of M13 and the gate of M15, the gate of M12 is connected with the gate of M13, and the drain of M14 is connected with the drain of M15 to serve as an output out;
the selection module consists of M5, M6, M7, M8 and an inverter, the output of the comparator module is divided into two paths, one path of output is directly connected with the grid electrode of the selection module M6, the other path of output is connected with the input of the selection module inverter INV1, the output of the inverter is connected with the grid electrode of M5, the source electrode of M5 is connected with the grid electrode of M7, the source electrode of M6 is connected with the grid electrode of M8, and the drain electrodes of M5 and M6 are connected with the grid electrode of the self-bias current structure M4; the drains of M5 and M6 are connected to the gate b of the self-bias current structure M4, M5 and M6 function as switches, when M5 and M6 are turned on, M7 and M8 are mirrored with the self-bias structure M4, and the drains of M7 and M8 are used as the output bias voltage bias to be supplied to the charge pump core module.
Further, the charge pump core module consists of a current mirror and a unity gain operational amplifier, wherein M16, M17 and M18 form one group of current mirrors, and M23 and M24 form the other group of current mirrors; the bias voltage bias of the charge pump is from the drains of self-bias structures M7 and M8, the bias voltage bias is connected with the gates of M16, M17 and M18, and the gate of M16 is connected with the drain; the drain of M17 is connected with the gate and drain of M25, M25 is used for regulating current, the source of M25 is connected with the gate and drain of M23, and the gates of M23 and M24 are connected; up and down are output signals generated by the phase frequency detector, and up _ b and down _ b are reverse signals of up and down respectively; up, up _ b, down _ b are respectively connected with the gates of M20, M19, M22 and M21, the drain of M18 is connected with the sources of M19 and M20, the drain of M19 and the drain of M21 are simultaneously connected with the output end of the unity gain operational amplifier, the negative input end of the unity gain operational amplifier is connected with the output of the unity gain operational amplifier, the sources of M21 and M22 are simultaneously connected with the drain of M24, the drain of M20 and the drain of M22 are simultaneously connected with the positive input end of the unity gain operational amplifier as output vc.
Furthermore, the voltage-controlled delay line module adopts a push-pull type delay unit structure and is composed of 33 voltage-controlled delay units connected end to end, the voltage-controlled delay unit is composed of a current source, M26, M27, M28, M29 and inverters, the grid electrodes of M26 and M27 are connected to be used as an input in, the input in of the first delay unit is a reference clock refclk, the drain electrode of M26 is connected with the drain electrode of M27 and outputs out1 through two inverters, namely clk <0>, the grid electrodes of M28 and M29 are connected at the same time, the drain electrodes of M28 and M29 are connected to be used as an output out, the output is an out2 through three inverters, namely clk <2>, the output is connected with the input in of the next delay unit, and 65 clocks, namely clk <0> to <63> and the 65 th clock output is output through 33 voltage-controlled delay units.
Further, the frequency doubling circuit is composed of an and gate and an inverter, the inversion and operation of the input signals clk <0> and clk <2> results in p1, the inversion and operation of clk <2> and clk <4> results in n1, and the relationship between pi, ni and clk can be expressed by the following sub-equations:
p i ＝clk＜4i-4＞×clkn＜4i-2＞
n i ＝clk＜4i-2＞×clkn＜4i＞
wherein clk < 4i-4 > represents the output of the 2i-1 th delay cell, clk < 4i-2 > represents the output of the 2 i-th delay cell; clkn < 4i-2 > is the output result of clk < 4i-2 > through an inverter; n1 to n16 are respectively the gates of M48 to M63, the drains of M48 to M63 are connected to the gate of M31 and the drain of M30 at the same time, p1 to p16 are respectively the gates of M32 to M47, the drains of M32 to M47 are connected to the gate of M30 and the drain of M31 at the same time, and pass through a buffer output out.
Compared with the prior art, the invention has the following advantages:
according to the fast locking delay phase-locked loop structure, the phase frequency detector is additionally provided with the control module, so that an input clock entering the phase frequency detector firstly is a feedback clock, and a phase difference comparison process that a reference clock is ahead of the feedback clock is omitted, so that the phase detection of the phase frequency detector becomes simple and uncomplicated. A comparator structure is added in the charge pump structure, and the size of the current of the charge pump is selected by monitoring the change of vc, so that the locking speed of the time delay phase-locked loop is improved.
Drawings
FIG. 1 is a block diagram of a conventional delay locked loop;
FIG. 2 is a block diagram of a DLL architecture according to the present invention;
fig. 3 is a schematic structural diagram of a phase frequency detector provided by the present invention;
FIG. 4 is a schematic diagram of a charge pump biasing architecture according to the present invention;
FIG. 5 is a schematic diagram of a comparator according to the present invention;
FIG. 6 is a schematic diagram of a charge pump core module according to the present invention;
FIG. 7 is a schematic diagram of a voltage controlled delay cell according to the present invention;
FIG. 8 is a schematic diagram of a frequency multiplier circuit according to the present invention;
fig. 9 is a timing diagram of a frequency multiplier circuit according to the present invention.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.
An example of the present invention provides a fast-locking dll architecture as shown in fig. 2. The structure consists of five parts, namely a phase frequency detector PFD, a charge pump CP, a low pass filter LPF, a voltage-controlled delay line VCDL and a frequency doubling circuit.
The phase frequency detector PFD is described in the embodiments with reference to fig. 3. The en signal is a control signal of the phase frequency detector. When the en signal is 0, the phase frequency detector does not work; when the en signal is 1, the phase frequency detector performs phase detection operation. The reference clock refclk and the feedback clock back clk respectively and with the en signal, and the obtained results are rclk and bclk respectively. The rclk is the clk clock of the D2, D3 and D4 flip-flops, and the bclk is the clk clock of the D5 flip-flop. The output result of the D2 flip-flop is connected with the D input end of the D3 flip-flop, and the D input ends of the D1, the D2, the D4 and the D5 flip-flop are connected with a power supply. The output ends Q of the D4 flip-flops and the D5 flip-flops are respectively the outputs up and down of the phase frequency detector. The result of the NAND operation of the up and down signals is further NAND-operated with the output Q of the D3 flip-flop, delayed by a segment of buffer to be used as the rst reset signal of the D4 and D5 flip-flops, and the delay is 800 ps. The inversion of bclk is the clk clock of the D1 flip-flop, the inversion of rclk is the rst reset signal of the D1 flip-flop, and the output of the D1 flip-flop goes through the inversion as the rst reset terminals of the D2 and D3 flip-flops. The D1, D2 and D3 flip-flops function to make the input clock of the phase frequency detector as feedback clock, and the D4 and D5 flip-flops function as phase frequency detector.
The charge pump biasing structure is described in the detailed description of fig. 4. The module consists of three parts, one is a self-bias current module, the grid electrode of the M1 tube is connected with the drain electrode, and the grid electrode of the M2 tube and the drain electrode of the M3 tube are simultaneously connected; the grid electrode of the M4 tube is connected with the drain electrode, and the grid electrode of the M3 tube and the drain electrode of the M2 tube are connected at the same time, the connection mode can effectively avoid the influence of the change of the power supply voltage on the bias current, a resistor R is connected between the source electrode of the M3 tube and the ground, the bias current can have a unique value, and the current of 10uA is generated from a bias current structure; the positive input end of the comparator is connected with vref, the voltage value of a connecting line between the resistors R1 and R2 in series is vref, the negative input end of the comparator is connected with a control signal vc, the comparator is implemented by combining with the graph shown in FIG. 5, vb is a tail power supply control signal, vb is respectively connected with the gates of M9 and M12, the drain of M9 is respectively connected with the sources of M10 and M11, M10 and M11 are input geminate transistors, the drain of M10 is respectively connected with the gate and the drain of M12, the drain of M11 is respectively connected with the drain of M13 and the gate of M15, the gate of M12 is connected with the gate of M13, and the drain of M14 is connected with the drain of M15 to serve as output out; the third is a selection module, the selection module is composed of M5, M6, M7, M8 and an inverter, the output of the comparator module is divided into two paths, one path of output is directly connected with the grid of the selection module M6, the other path of output is connected with the input of the selection module inverter INV1, the output of the inverter is connected with the grid of M5, the source of M5 is connected with the grid of M7, the source of M6 is connected with the grid of M8, and the drains of M5 and M6 are connected with the grid of the self-bias current structure M4. The drains of M5 and M6 are connected to the gate b of the self-bias current structure M4, M5 and M6 function as switches, when M5 and M6 are turned on, M7 and M8 are approximately mirrored with the self-bias structure M4, and the drains of M7 and M8 are used as the output bias voltage bias to be supplied to the charge pump core module. Taking the width-length ratio of M4 as W/L, M7 as 6W/L and the width-length ratio of M8 as 2W/L, the ratio of the branch current of M7 to that of M8 is 3:1, the branch current of M7 is 60uA, and the branch current of M8 is 20 uA. Before locking, vc is greater than vref, the output of the comparator is 0, M5 is conducted, M6 is closed, the current from the M7 branch is 60uA, namely the charge pump bias circuit selects large current, the discharge speed of the charge pump is increased by 3 times, and the reduction speed of vc is increased by 3 times; when vc < vref, the comparator output is 1, M5 is turned off, M6 is turned on, the current from the M8 branch is 20uA, i.e., the charge pump bias current assumes the normal current value, and the charge pump discharge speed returns to the normal speed. For vc close to vref, choosing large and small currents has no effect on the result, since the time is short, only instantaneous.
The charge pump core module is composed of two parts, namely a current mirror and a unity gain operational amplifier, and the specific implementation mode is combined with the figure 6. The bias voltage bias of the charge pump comes from the drains of the self-bias structures M7, M8, which are connected with the gates of M16, M17, M18, and the gate of M16 is connected with the drain. The drain of M17 is connected to the gate and drain of M25, and the source of M25 is connected to the gate and drain of M23, and the gates of M23 and M24. up and down are output signals generated by the phase frequency detector, and up _ b and down _ b are inverted signals of up and down respectively. up, up _ b, down _ b are respectively connected with the gates of M20, M19, M22 and M21, the drain of M18 is connected with the sources of M19 and M20, the drain of M19 and the drain of M21 are simultaneously connected with the output end of the unity gain operational amplifier, the negative input end of the unity gain operational amplifier is connected with the output of the unity gain operational amplifier, the sources of M21 and M22 are simultaneously connected with the drain of M24, the drain of M20 and the drain of M22 are simultaneously connected with the positive input end of the unity gain operational amplifier as output vc. The width-length ratios of M16, M17 and M18 are respectively 2.5 times and 2.4 times and 6 times from the first stage to the third stage, and the width-length ratio of M24 to M23 is 2.4 times. Due to the clamping effect of the unity gain operational amplifier, the drain voltages of M19 and M21 are equal to the drain voltages of M20 and M22, namely vc is equal to v0, so that the matching of the up and down currents is greatly improved when the up and down currents of the charge pump charge and discharge the capacitor.
The voltage-controlled delay unit is implemented in combination with fig. 7. The sizes of the current sources I1 and I2 are controlled by vc, the sizes of the current sources control the delay time, and the delay time and the inverse number of the current form a certain linear relation. The M26 is connected with the gate of M27 as an input in, the input in of the first delay unit is a reference clock refclk, the drain of M26 is connected with the drain of M27, the output of the drain is out1 (namely clk <0 >), the gates of M28 and M29 are connected at the same time, the drains of M28 and M29 are connected as an output out, the output of the out is out2 (namely clk <2 >), the output is connected with the input in of the next delay unit, the outputs are connected end to end through 33 voltage-controlled delay units, 65 clocks (namely clk <0> -clk <63 >), and the back clk is used as the 65 th clock output.
The frequency multiplier circuit is described in the embodiment with reference to fig. 8. The frequency multiplier circuit of the invention is 16 times frequency. To achieve 16 frequency multiplication, there are 32 inputs in the circuit, p1, p2, …, p16, n1, n2 … n16, respectively, where
p i ＝clk＜4i-4＞×clkn＜4i-2＞
n i ＝clk＜4i-2＞×clkn＜4i＞
Wherein clk < 4i-4 > represents the output of the 2i-2 th delay cell, clk < 4i-2 > represents the output of the 2 i-th delay cell; clkn < 4i-2 > is the output of clk < 4i-2 > through an inverter. The relationship of the output out to the various inputs is:
the timing of the frequency multiplier circuit is shown in FIG. 9, with the phase difference between clk <0> and clk <2> being the first pulse of output out, the phase difference between clk <4> and clk <6> being the second pulse of output out, and so on, and the phase difference between clk <60> and clk <62> being the 16 th pulse of output out. The clock frequency of the output out is enlarged by 16 times relative to the clock frequencies of clk <0> to clk <62>, that is, different phase output clocks of the voltage-controlled delay line pass through the frequency doubling circuit, and 16 frequency-doubled output clocks are obtained.
The preferred embodiments of the present invention have been described in detail with reference to the accompanying drawings, however, the present invention is not limited to the specific details of the above embodiments, and various simple modifications can be made to the technical solution of the present invention within the technical idea of the present invention, and these simple modifications are within the protective scope of the present invention.
It should be noted that the various technical features described in the above embodiments can be combined in any suitable manner without contradiction, and the invention is not described in any way for the possible combinations in order to avoid unnecessary repetition.
In addition, any combination of the various embodiments of the present invention can be made, and the same should be considered as the disclosure of the present invention as long as the idea of the present invention is not violated.
Claims (5)
1. A fast locking delay phase-locked loop is characterized by comprising a phase frequency detector PFD, a charge pump CP, a low pass filter LPF, a voltage-controlled delay line VCDL and a frequency multiplier circuit; the phase frequency detector is used for comparing the phase difference between a reference clock and a feedback clock and generating output signals up and down with fixed clock period; the up signal and the down signal are used as input signals of a charge pump, and an output signal of the charge pump generates an output voltage vc through the charge and discharge of a low-pass filter capacitor; the vc and the reference clock enter a voltage-controlled delay line to obtain multi-phase output clocks, wherein one output clock is fed back to the phase frequency detector and is used as an input clock of the phase frequency detector, namely a feedback clock; meanwhile, vc is fed back to the charge pump to control the current of the charge pump; the multi-phase output of the voltage-controlled delay line passes through a frequency doubling circuit to obtain frequency doubling output;
the frequency and phase discriminator structure consists of five D triggers; the five flip-flops are D1, D2, D3, D4 and D5 flip-flops respectively; the reference clock and the feedback clock respectively perform AND operation with a control signal en to generate an rclk clock and a bclk clock, wherein the rclk clock is used as input clocks of D2, D3 and D4 triggers, the reverse direction of the rclk clock is used as a reset signal of the D1 trigger, the bclk clock is used as an input clock of the D5 trigger, and the reverse direction of the bclk clock is used as an input clock of the D1 trigger; the D4 and D5 triggers form a traditional three-state structure phase frequency detector, and then output up and down signals, a buffer is arranged between the reset signals of the up and down signals reaching the D triggers and is used for increasing the reset time delay of the up and down signals reaching the D4 and D5 triggers;
the charge pump consists of a self-biasing structure and a core module; the self-biasing structure is used for generating reference current, and the reference current generates reference voltage bias which is supplied to the core module to be used as bias voltage, so that the core module generates the required bias current;
the self-bias structure consists of a self-bias current, a comparator module and a selection module; the self-bias current has no input signal, generates a reference current in the self-bias current, and generates a bias voltage signal b by the current to supply the bias voltage signal b to the selection module as an input signal; the positive input end of the comparator is vref, the negative input end of the comparator is vc, the output result is used for being connected with the grid electrode of the selection module, the on and off of the grid electrode are controlled, and then the magnitude of the bias current is selected to be supplied to the core module.
2. The fast lock-delay locked loop of claim 1, wherein the self-bias current is composed of mos transistors M1, M2, M3, M4 and a resistor R1, the gate of the M1 transistor is connected to the drain, and the gate of the M2 transistor is connected to the drain of the M3 transistor; the grid electrode and the drain electrode of the M4 tube are connected, the grid electrode of the M3 and the drain electrode of the M2 are simultaneously connected, and a resistor R is connected between the source electrode of the M3 and the ground;
the comparator module consists of mos tubes M9, M10, M11, M12, M13, M14 and M15, wherein the positive input end of the comparator is connected with vref, and the negative input end of the comparator is connected with a control signal vc; vb is a tail power supply control signal, vb is respectively connected with the gates of M9 and M12, the drain of M9 is respectively connected with the sources of M10 and M11, M10 and M11 are input geminate transistors, the drain of M10 is respectively connected with the gate and the drain of M12, the drain of M11 is respectively connected with the drain of M13 and the gate of M15, the gate of M12 is connected with the gate of M13, and the drain of M14 is connected with the drain of M15 to serve as an output out;
the selection module consists of mos tubes M5, M6, M7, M8 and an inverter, the output of the comparator module is divided into two paths, one path of output is directly connected with the grid electrode of the selection module M6, the other path of output is connected with the input of the selection module inverter INV1, the output of the inverter is connected with the grid electrode of M5, the source electrode of M5 is connected with the grid electrode of M7, the source electrode of M6 is connected with the grid electrode of M8, and the drain electrodes of M5 and M6 are connected with the grid electrode of a self-bias current structure M4; the drains of M5 and M6 are connected to the gate b of the self-bias current structure M4, M5 and M6 function as switches, when M5 and M6 are turned on, M7 and M8 are mirrored with the self-bias structure M4, and the drains of M7 and M8 are used as the output bias voltage bias to be supplied to the charge pump core module.
3. The fast lock-delay locked loop of claim 2, wherein the charge pump core module comprises a current mirror and a unity gain op-amp, the mos transistor M16, M17 and M18 comprises a set of current mirrors, and the M23 and M24 comprise another set of current mirrors; the bias voltage bias of the charge pump is from the drains of self-bias structures M7 and M8, the bias voltage bias is connected with the gates of M16, M17 and M18, and the gate of M16 is connected with the drain; the drain of M17 is connected with the gate and drain of M25, M25 is used for regulating current, the source of M25 is connected with the gate and drain of M23, and the gates of M23 and M24 are connected; up and down are output signals generated by the phase frequency detector, and up _ b and down _ b are reverse signals of up and down respectively; up, up _ b, down _ b are respectively connected with the gates of M20, M19, M22 and M21, the drain of M18 is connected with the sources of M19 and M20, the drain of M19 and the drain of M21 are simultaneously connected with the output end of the unity gain operational amplifier, the negative input end of the unity gain operational amplifier is connected with the output of the unity gain operational amplifier, the sources of M21 and M22 are simultaneously connected with the drain of M24, the drain of M20 and the drain of M22 are simultaneously connected with the positive input end of the unity gain operational amplifier, and the drain of M20 is used as an output vc.
4. The fast locked delay locked loop of claim 1, wherein the voltage-controlled delay line module is a push-pull delay unit structure, and comprises 33 voltage-controlled delay units connected end to end, the voltage-controlled delay units comprise current sources, mos transistors M26, M27, M28, M29, and inverters, M26 is connected to the gate of M27 as the input in, the first delay unit input in is the reference clock refclk, the source of M26 is connected to one end of the current source I1, the other end of the current source I1 is connected to VDD, the source of M27 is connected to one end of the current source I2, the other end of the current source I2 is connected to ground, the drain of M26 is connected to the drain of M27, and the output is out1 through two inverters, that is clk <0>, the drain of M26 and the drain of M27 are connected to the gates of M28 and M29, the source of M28 is connected to one end of the current source I1, and the other end of I1 is connected to VDD, the source of the M29 is connected with one end of a current source I2, the other end of the current source I2 is connected with the ground, the drain of the mos tube M28 is connected with the drain of the M29 to serve as an output out, the output of the out is out2 through three inverters, namely clk <2>, and the out is connected with the input in of the next delay unit; the reference clock refclk passes through 33 voltage controlled delay units, and 65 clocks, i.e., clk <0> to clk <63> and back clk are output, wherein back clk is output as the 65 th clock.
5. The fast locking delay locked loop of claim 4, wherein the frequency multiplier circuit comprises an AND gate and an inverter, the inversion AND operation of the input signals clk <0> and clk <2> yields p1, the inversion AND operation of clk <2> and clk <4> yields n1, and the relationship between pi, ni and clk is represented by the following equation, wherein i ranges from 1 to 16:
p i ＝clk＜4i-4＞×clkn＜4i-2＞
n i ＝clk＜4i-2＞×clkn＜4i＞
wherein clk < 4i-4 > represents the output of the 2i-1 th delay cell, clk < 4i-2 > represents the output of the 2 i-th delay cell; clkn < 4i-2 > is the output result of clk < 4i-2 > through an inverter; n1 to n16 are respectively connected to the gates of mos transistors M48 to M63, the drains of M48 to M63 are connected to the gate of M31 and the drain of M30 at the same time, p1 to p16 are connected to the gates of M32 to M47, the drains of M32 to M47 are connected to the gate of M30 and the drain of M31 at the same time, and pass through a buffer output out 3; the sources of M32-M47 are also connected to ground, and the sources of M48-M63 are all connected to ground.
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