CN109639272A - A kind of adaptive wideband phase-locked loop circuit - Google Patents
A kind of adaptive wideband phase-locked loop circuit Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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Abstract
The present invention relates to a kind of adaptive wideband phase-locked loop circuits, including adaptive driver, first voltage-current converter, charge pump, loop filter, adaptive driver, the phase difference that phaselocked loop exports clock and reference clock is accumulated, coarse adjustment control voltage is obtained, and coarse adjustment is controlled into voltage output to first voltage-current converter；Coarse adjustment control voltage is converted into coarse adjustment control electric current by first voltage-current converter；Charge pump, using the image current of coarse adjustment control electric current as current source, the leading phase difference signal " UP " and lagging phase difference signal " DOWN " of input reference clock are compared according to output clock, charge is pumped into loop filter or pumps out charge from loop filter, exports the control voltage signal V of voltage controlled oscillatorCTRL.Phase-locked loop circuit of the present invention has widened the reference frequency output of phaselocked loop, shortens capture time, can be applied to the clock circuit and high-speed serial interface circuit of high-speed AD converter.
Description
Technical field
The present invention relates to a kind of adaptive wideband phase-locked loop circuits, belong to technical field of integrated circuits, are mainly used to generate
The stabilizing clock of high-speed wideband, the circuit shorten locking time by adaptive drive module adjustment loop bandwidth, go here and there for high speed
Line interface provides clock, guarantees the accurate transmission of high-speed data.
Background technique
The meaning of phase-locked loop circuit be it can flexibly be provided according to a reference clock signal multi-frequency when
Clock signal.Although frequency signal can be generated using crystal oscillating circuit in some applications, it adjusts not flexible, the output of frequency
The speed of high cost and chip interface when high-frequency signal all limits its application in integrated circuits.Phase-locked loop circuit passes through
The frequency dividing ratio for adjusting frequency divider can provide the frequency-doubled signals of multiple frequencies, become in most of IC systems can not or
Scarce some.
Phase-locked loop circuit is widely used in high-speed data processing circuit frequently as jitter filter or frequency synthesizer.With
The raising of processing speed and the increase of application flexibility, also proposed more harsh requirement to phaselocked loop, such as low-voltage, wideband
Rate, low-power consumption and low noise etc..
The phaselocked loop of charge pump construction is mostly used in the application of most systems at present.Traditional charge pump phase lock loop, respectively
The parameter of a module be it is fixed, it can only export high performance frequency signal in very narrow working range, such as very narrow
Input, reference frequency output and division range, expanding range is usually to sacrifice output signal jitter performance as cost.
Fixed-bandwidth phaselocked loop is defective, for example selects lower bandwidth, will cause longer acquisition time or compared with
Big chip area；When phase-locked loop operation condition changes, fixing belt width values prevent phaselocked loop from inhibiting more noise jammings；Gu
Fixed pll parameter is easy to be influenced by technique, supply voltage and temperature change, so that phaselocked loop final argument and design
It is larger to be worth deviation；In addition, the phaselocked loop of fixed-bandwidth, circuit cost are higher.
Summary of the invention
Technology of the invention solves the problems, such as: overcome the deficiencies in the prior art, proposes a kind of adaptive wideband phaselocked loop
Technology, using configurable ring oscillator phaselocked loop, by self-adaptive driving circuit adjust automatically loop bandwidth, when shortening locking
Between.
The technical solution of the invention is as follows: a kind of adaptive wideband phase-locked loop circuit, the phase-locked loop circuit include frequency discrimination
Phase discriminator, adaptive driver, first voltage-current converter, charge pump, loop filter, voltage controlled oscillator, in which:
Adaptive driver will be locked according to lagging phase difference signal and leading phase difference signal that phase frequency detector exports
The phase difference that phase ring exports clock and reference clock is accumulated, and obtains coarse adjustment control voltage, and coarse adjustment is controlled voltage output to the
One voltage-current converter；
Coarse adjustment control voltage is converted into coarse adjustment control electric current by first voltage-current converter；
Charge pump, using the image current of coarse adjustment control electric current as current source, according to leading phase difference signal " UP " and
Charge is pumped into loop filter or pumps out charge from loop filter by lagging phase difference signal " DOWN ", output pressure
Control the control voltage signal V of oscillatorCTRL；
Voltage controlled oscillator, in control voltage signal VCTRLControl under export clock signal, while the clock signal being made
For phaselocked loop output clock feedback to phase frequency detector input terminal.
The voltage controlled oscillator includes second voltage-current converter and ring oscillator；
Second voltage-current converter, the control voltage signal V that loop filter is exportedCTRLBe converted to control electric current
Signal ICTRLIt exports to ring oscillator；
Ring oscillator, in control current signal ICTRLControl under export clock signal, while the clock signal being made
Phase frequency detector input terminal is fed back to for the output clock value of phaselocked loop.
Coarse adjustment is also controlled voltage output to second voltage-current converter by adaptive driver, and second voltage-electric current turns
Coarse adjustment control voltage is converted to coarse adjustment control electric current by parallel operation, while coarse adjustment being controlled to the control of voltage and loop filter output
Voltage signal VCTRLAs cascode current source gate voltage signal generate fine tuning control electric current, then by coarse adjustment control electric current with it is micro-
Regulate and control electric current superposition processed, by the control electric current I after superpositionCTRLIt exports to ring oscillator.
The adaptive wideband phase-locked loop circuit further includes frequency divider, and frequency divider is to externally input reference clock and locking phase
The output clock of ring carries out scaling down processing respectively, and the reference clock CLK2 after the output clock CLK1 and frequency dividing after frequency dividing is sent
Output clock and reference clock frequency having the same to phase frequency detector, after frequency dividing；
Phase frequency detector, the phase between the reference clock CLK2 after output clock CLK1 and frequency dividing after detecting frequency dividing
Difference, and export the lagging phase difference signal " DOWN " and table of the reference clock that the output clock after indicating frequency dividing lags behind after frequency dividing
Output clock after showing frequency dividing is ahead of the leading phase difference signal " UP " of the reference clock after frequency dividing.；
Voltage controlled oscillator exports clock signal under the control of control voltage signal, while using the clock signal as lock
The input terminal for exporting clock feedback to frequency divider of phase ring.
The frequency divider is using different frequency division coefficients to the output clock point of externally input reference clock and phaselocked loop
Not carry out scaling down processing, the frequency division coefficient can be arranged by external control signal.
The adaptive driver includes N number of driving unit, current source I_1, current source I_2, PMOS tube M_1, NMOS tube
M_2, in which:
N-th of driving unit, including PMOS tube M [n] _ 0, M [n] _ 1, M [n] _ 2, NMOS tube M [n] _ 3, M [n] _ 4, M
[n] _ 5, capacitor C [n], phase inverter N [n]；The leakage of source electrode the connection power supply, PMOS tube M [n] _ 0 of PMOS tube M [n] _ 0, M [n] _ 1
Pole connects the drain electrode of PMOS tube M [n] _ 1 and the source electrode of PMOS tube M [n] _ 2, and the drain electrode of PMOS tube M [n] _ 2 drives as n-th
The voltage output end OUT [n] of unit connects the drain electrode of NMOS tube M [n] _ 3 and the input terminal of phase inverter N [n], while passing through electricity
Hold C [n] ground connection, the drain electrode of source electrode connection NMOS tube M [n] _ 4 of NMOS tube M [n] _ 3 and the drain electrode of NMOS tube M [n] _ 5, NMOS
The source level ground connection of pipe M [n] _ 4, M [n] _ 5.The output end of phase inverter N [n] connects (n+1)th driving unit PMOS tube M [n+1] _ 1
With the grid of the PMOS tube M [n-1] _ 2 and NMOS tube M [n-1] _ 4 of the grid and (n-1)th driving unit of NMOS tube M [n+1] _ 3
Pole, n=1~N-2.
The N-1 driving unit includes PMOS tube M [N-1] _ 0, M [N-1] _ 1, M [N-1] _ 2, NMOS tube M [N-1] _ 3, M
[N-1] _ 4, M [N-1] _ 5, capacitor C [N-1], phase inverter N [N-1]；The source electrode of PMOS tube M [N-1] _ 0 and the source electrode of M [N-1] _ 1
The drain electrode of drain electrode connection PMOS tube M [N-1] _ 1 of power supply, PMOS tube M [N-1] _ 0 is connected, the drain electrode of PMOS tube M [N-1] _ 1 connects
Meet the source electrode of PMOS tube M [N-1] _ 2, voltage output end OUT of the drain electrode of PMOS tube M [N-1] _ 2 as the N-1 driving unit
[N-1] connects the drain electrode of NMOS tube M [N-1] _ 3 and the input terminal of phase inverter N [N-1], while being grounded by capacitor C [N-1],
The output end of phase inverter N [N-1] connects the grid of the PMOS tube M [N-2] _ 2 and NMOS tube M [N-2] _ 4 of the N-2 driving unit
Pole, the drain electrode of source electrode connection NMOS tube M [N-1] _ 4 of NMOS tube M [N-1] _ 3 and the drain electrode of NMOS tube M [N-1] _ 5, NMOS tube M
The source level of [N-1] _ 4, M [N-1] _ 5 are grounded.The grounded-grid of PMOS tube M [N-1] _ 2 and NMOS tube M [N-1] _ 4.
0th driving unit, including PMOS tube M [0] _ 0, M [0] _ 1, M [0] _ 2, NMOS tube M [0] _ 3, M [0] _ 4, M
[0] _ 5, capacitor C [0], phase inverter N [0]；The leakage of source electrode the connection power supply, PMOS tube M [0] _ 0 of PMOS tube M [0] _ 0, M [n] _ 1
Pole connects the drain electrode of PMOS tube M [0] _ 1 and the source electrode of PMOS tube M [0] _ 2, and the drain electrode of PMOS tube M [0] _ 2 drives as the 0th
The voltage output end OUT [0] of unit connects the drain electrode of NMOS tube M [0] _ 3 and the input terminal of phase inverter N [0], while passing through electricity
Hold C [0] ground connection, the drain electrode of source electrode connection NMOS tube M [0] _ 4 of NMOS tube M [0] _ 3 and the drain electrode of NMOS tube M [0] _ 5, reverse phase
The output end of device N [0] connects the grid of the 1st driving unit PMOS tube M [1] _ 1 and NMOS tube M [1] _ 3, NMOS tube M [0] _ 4,
The source level of M [0] _ 5 is grounded, and PMOS tube M [0] _ 1 and NMOS tube M [0] _ 3 grid connect power supply.
The source level of PMOS tube M_1 connects power supply, one end of drain electrode connection current source I_1, another termination of current source I_1
Ground, grid connect the grid of PMOS tube M [0] _ 0~M [N-1] _ 0；The open and close of current source I_1 are controlled by UP signal,
When UP signal is high, current source I_1 is opened, when UP signal is low, current source I_1 shutdown.
The one end current source I_2 connects power supply, and the other end connects the drain electrode of NMOS tube M_2, and the source electrode of NMOS tube M_2 is grounded,
The grid of grid connection NMOS tube M [0] _ 5~M [N-1] _ 5 of NMOS tube M_2.The open and close of current source I_2 pass through DOWN
Signal control, when DOWN signal is high, current source I_2 is opened, when DOWN signal is low, current source I_2 shutdown.
First voltage-the current converter (104) includes PMOS tube M2_ [0]~M2_ [N-1], and PMOS tube M2_ [0]~
The sources connected in parallel of M2_ [N-1] is connected on power supply, and PMOS tube M2_ [0]~M2_ [N-1] grid is respectively connected to adaptively drive
Voltage output end OUT [0]~OUT [N-1] of dynamic device, PMOS tube M2_ [0]~M2_ [N-1] drain electrode are connected in parallel, and export
Coarse adjustment controls electric current Icp.
Second voltage-current converter includes PMOS tube M3_ [0]~M3_ [N-1], M4_ [0]~M4_ [N-1], M5_ [0]
~M5_ [N-1]；
PMOS tube M3_ [0]~M3_ [N-1], M5_ [0]~M5_ [N-1] sources connected in parallel are connected on power supply, M5_ [0]
The drain electrode of~M5_ [N-1] is connected to M4_ [0]~M4_ [N-1] source electrode, PMOS tube M3_ [0]~M3_ [N-1] grid difference
It is connected to voltage output end OUT [0]~OUT [N-1] of adaptive driver, M4_ [0]~M4_ [N-1] grid and PMOS tube
M3_ [0]~M3_ [N-1] gate connected in parallel is connected to voltage output end OUT [0]~OUT [N-1] of adaptive driver；M5_
[0] the gate connected in parallel connection control voltage signal V of~M5_ [N-1]CTRL, PMOS tube M3_ [0]~M3_ [N-1], M4_ [0]~
The drain electrode of M4_ [N-1] is connected in parallel, output control electric current ICTRLTo ring oscillator.
The charge pump includes NMOS tube N1_1, N1_2, PMOS tube P1_1, P1_2, capacitor C1_1, amplifier A1_1, electricity
Stream source I_3, I_4；
The grid of NMOS tube N1_1 and the grid of NMOS tube N1_2 are separately connected leading phase difference signal and leading phase potential difference
The inversion signal of signal；The grid of PMOS tube P1_1 and the grid of PMOS tube P1_2 are separately connected the reverse phase of lagging phase difference signal
Signal and lagging phase difference signal；The source electrode of PMOS tube P1_1 and the source electrode of PMOS tube P1_2 connect current source I_3 jointly；NMOS
The source electrode of pipe N1_1 and the source electrode of NMOS tube N1_2 connect current source I_4 jointly；The drain electrode of PMOS tube P1_1 and with NMOS tube N1_
1 drain electrode is grounded by capacitor C1_1, while being connected to the output end of charge pump and the electrode input end of amplifier A1_1；Amplifier
The negative input of A1_1 is connected to the output end of amplifier A1_1；The output end of amplifier A1_1 is connected to PMOS tube simultaneously
The drain electrode of P1_2 and with NMOS tube N1_2 drain.
The reference clock frequency range is 1GHz to 4GHz, duty ratio 50%.
Compared with the prior art, the invention has the advantages that:
(1) present invention increases self-adaptive driving circuit on the basis of conventional charge pumps phaselocked loop, adaptive driving electricity
Road is tired to the phase difference of input clock and output clock according to the phase signal that phase frequency detector exports in acquisition procedure
Product, the control voltage that the phase difference of accumulation generates realize the quick lock in of phaselocked loop by coarse adjustment access.
(2), the present invention accumulates the phase difference of input clock and output clock, the control electricity that the phase difference of accumulation is generated
It is pressed on the basis of coarse adjustment, further by fine tuning access, i.e. second voltage-current converter, generates control current regulator
The frequency of oscillation of shape oscillator realizes the accurate locking of phaselocked loop.
(3), divider circuit of the invention is made of dual-modulus prescaler and three mould pre-dividers, corresponding by being arranged
Control bit realizes different frequency division coefficients, realizes adaptive bandwidth adjustment, meets requirement of the different application environment to clock；
(4), phaselocked loop of the present invention can carry out dynamic adjustment ring according to working condition, such as reference frequency and lock state
Road bandwidth, the shake for inhibiting each noise source to generate output signal as far as possible, with the performance parameter being optimal.
(5), present invention can apply to the clock circuit of high-speed AD converter and high speed serial interface systems, in next step
The analog-digital converter for developing more high sampling rate higher performance provides technical support.
Detailed description of the invention
Fig. 1 is phase-locked loop circuit schematic illustration of the invention；
Fig. 2 is the circuit structure diagram of frequency divider of the invention；
Fig. 3 is the structural schematic diagram of phase frequency detector of the invention；
Fig. 4 is the circuit structure diagram adaptively driven of the invention；
Fig. 5 is the circuit timing diagram adaptively driven of the invention；
Fig. 6 is -1 circuit structure diagram of Voltage-current conversion of the invention；
Fig. 7 is the structural schematic diagram of charge pump and loop filter of the invention；
Fig. 8 is -2 circuit structure diagram of Voltage-current conversion of the invention；
Fig. 9 is the structural schematic diagram of current limited type ring oscillator of the invention；
Specific embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.
The present invention provides a kind of specific embodiments of adaptive wideband phase-locked loop circuit.The circuit include frequency divider 101,
Phase frequency detector 102, adaptive driver 103, first voltage-current converter 104, charge pump 105, loop filter 108,
Second voltage-current converter 106 and ring oscillator module 107.Wherein:
Frequency divider 101, frequency divider carry out at frequency dividing the output clock of externally input reference clock and phaselocked loop respectively
Reference clock CLK2 after output clock CLK1 and frequency dividing after frequency dividing is sent to phase frequency detector 102 by reason, defeated after frequency dividing
Clock and reference clock frequency having the same out；It can be using different frequency division coefficients to externally input reference clock and lock
The output clock of phase ring carries out scaling down processing respectively, and the frequency division coefficient can be arranged by external control signal.
Phase frequency detector 102, the phase between the reference clock CLK2 after output clock CLK1 and frequency dividing after detecting frequency dividing
Potential difference, and export indicate frequency dividing after output clock lag behind divide after reference clock lagging phase difference signal " DOWN " and
Output clock after indicating frequency dividing is ahead of the leading phase difference signal " UP " of the reference clock after frequency dividing；
Self-adaptive driving circuit, according to lagging phase difference signal and leading phase difference signal, will output phase-locked loop clock with
The phase difference of reference clock is accumulated, and obtains coarse adjustment control voltage, and coarse adjustment is controlled voltage output to first voltage-electric current and is converted
Device 104；Coarse adjustment is controlled into voltage output to second voltage-current converter 106 simultaneously；
Coarse adjustment control voltage is converted into coarse adjustment control electric current by first voltage-current converter 104；
Charge pump, using the image current of coarse adjustment control electric current as current source, according to lagging phase difference signal " DOWN "
With leading phase difference signal " UP ", charge is pumped into loop filter or pumps out charge from loop filter, output pressure
Control the control voltage signal V of oscillatorCTRL；
Second voltage-current converter 106, the control voltage signal V that loop filter is exportedCTRLBe converted to control electricity
Flow signal ICTRL, coarse adjustment control voltage is converted into coarse adjustment control electric current；Coarse adjustment control voltage and loop filter are exported
Control voltage signal VCTRLGate voltage signal as cascode current source generates fine tuning control electric current, then coarse adjustment is controlled electric current
It is superimposed with fine tuning control electric current, by the control electric current I after superpositionCTRLIt exports to ring oscillator.
Ring oscillator, in control current signal ICTRLControl under realize different frequencies of oscillation, export clock signal,
102 input terminal of phase frequency detector is fed back to using the clock signal as the output clock value of phaselocked loop simultaneously.
Foregoing circuit increases self-adaptive driving circuit, self-adaptive driving circuit on the basis of conventional charge pumps phaselocked loop
In acquisition procedure, according to the phase signal that phase frequency detector exports, the phase difference of input clock and output clock is accumulated,
The control voltage that the phase difference of accumulation generates realizes the quick lock in and adaptive band of phaselocked loop by coarse adjustment and fine tuning two-way
Width adjustment finally realizes that it is zero that phase difference is kept between two signals of phase frequency detector input terminal in the state of ideal.
Due to input clock frequency height, in order to reduce the design difficulty of phase frequency detector, using frequency divider to clock signal
Frequency dividing.As shown in Fig. 2, in a certain specific embodiment of the invention, the frequency divider 101 of use by a dual-modulus prescaler and
One three mould pre-divider is constituted.Dual-modulus prescaler can work in L+1 frequency dividing or L frequency dividing both of which, the selection of frequency dividing ratio
Signal S2 is controlled by mould to realize.Wherein L is a fixed value, depending on inputting the height of frequency, generally takes 2n, such as take L
=4.Three mould pre-dividers, which can work, to be controlled in M frequency dividing or 2M frequency dividing or 4M frequency dividing Three models, the selection of frequency dividing ratio by mould
Signal S1, S0 are realized.Wherein M is a fixed value, such as takes M=1.
Frequency divider is to output clock CLKOUTWith input clock CLKINFrequency dividing, with M=1, for L=4, as shown in Fig. 2, working as
When S2 is low, CLK1 CLKOUT4 frequency dividings, when S2 is high, CLK1 CLKOUT5 frequency dividings, when S1S0 is low, CLK2 is
CLKINHomogenous frequency signal, when S1S0 is high, CLK2 CLKINFour frequency dividings, when S1S0 mono- for high one be low when,
CLK2 is CLKINTwo divided-frequency.Phaselocked loop entirety frequency division coefficient is the ratio of the two frequency dividing ratios.So entire frequency division coefficient can
To be configured as 1,1.25,2,2.5,4 or 5.In the practical application of circuit, it can choose different frequency division coefficients and obtain difference
Frequency range.
As shown in figure 3, the phase frequency detector circuit that the present embodiment uses, is eliminated using symmetrical structure due to not postponing not
The imbalance of static phase caused by matching, the requirement of high speed and low-power consumption is met using dynamic latch 301.In order to avoid frequency discrimination mirror
The dead-time problem of phase device needs that delay unit 302 is added on the reset path of circuit, delay is generated, so that pulse signal RST
There is time enough to open charge pump, to guarantee that entire phaselocked loop makes correct feedback.
As shown in figure 4, adaptively the phase difference of input clock in acquisition procedure and output clock is accumulated in driving 103, and
Change into corresponding control voltage.On the basis of conventional charge pump phaselocked loop is adjusted, locking phase has been widened in the addition adaptively driven
The reference frequency output of ring, shortens capture time.Its structure is as shown in Figure 4.
In the present embodiment, adaptive driving is made of 20 identical subelement Cell [19:0], and OUT [19:0] is these
The output of subelement.Current mirror reference current is logical above and below the phase signal " UP " of phase frequency detector output and " DOWN " control
It is disconnected, the presence or absence of control electric current Iup and Idown.
N-th of driving unit, including PMOS tube M [n] _ 0, M [n] _ 1, M [n] _ 2, NMOS tube M [n] _ 3, M [n] _ 4, M
[n] _ 5, capacitor C [n], phase inverter N [n]；The leakage of source electrode the connection power supply, PMOS tube M [n] _ 0 of PMOS tube M [n] _ 0, M [n] _ 1
Pole connects the drain electrode of PMOS tube M [n] _ 1 and the source electrode of PMOS tube M [n] _ 2, and the drain electrode of PMOS tube M [n] _ 2 drives as n-th
The voltage output end OUT [n] of unit connects the drain electrode of NMOS tube M [n] _ 3 and the input terminal of phase inverter N [n], while passing through electricity
Hold C [n] ground connection, the drain electrode of source electrode connection NMOS tube M [n] _ 4 of NMOS tube M [n] _ 3 and the drain electrode of NMOS tube M [n] _ 5, NMOS
The source level ground connection of pipe M [n] _ 4, M [n] _ 5.The output end of phase inverter N [n] connects (n+1)th driving unit PMOS tube M [n+1] _ 1
With the grid of the PMOS tube M [n-1] _ 2 and NMOS tube M [n-1] _ 4 of the grid and (n-1)th driving unit of NMOS tube M [n+1] _ 3
Pole, n=1~N-2.
The N-1 driving unit includes PMOS tube M [N-1] _ 0, M [N-1] _ 1, M [N-1] _ 2, NMOS tube M [N-1] _ 3, M
[N-1] _ 4, M [N-1] _ 5, capacitor C [N-1], phase inverter N [N-1]；The source electrode of PMOS tube M [N-1] _ 0 and the source electrode of M [N-1] _ 1
The drain electrode of drain electrode connection PMOS tube M [N-1] _ 1 of power supply, PMOS tube M [N-1] _ 0 is connected, the drain electrode of PMOS tube M [N-1] _ 1 connects
Meet the source electrode of PMOS tube M [N-1] _ 2, voltage output end OUT of the drain electrode of PMOS tube M [N-1] _ 2 as the N-1 driving unit
[N-1] connects the drain electrode of NMOS tube M [N-1] _ 3 and the input terminal of phase inverter N [N-1], while being grounded by capacitor C [N-1],
The output end of phase inverter N [N-1] connects the grid of the PMOS tube M [N-2] _ 2 and NMOS tube M [N-2] _ 4 of the N-2 driving unit
Pole, the drain electrode of source electrode connection NMOS tube M [N-1] _ 4 of NMOS tube M [N-1] _ 3 and the drain electrode of NMOS tube M [N-1] _ 5, NMOS tube M
The source level of [N-1] _ 4, M [N-1] _ 5 are grounded.The grounded-grid of PMOS tube M [N-1] _ 2 and NMOS tube M [N-1] _ 4.
0th driving unit, including PMOS tube M [0] _ 0, M [0] _ 1, M [0] _ 2, NMOS tube M [0] _ 3, M [0] _ 4, M
[0] _ 5, capacitor C [0], phase inverter N [0]；The leakage of source electrode the connection power supply, PMOS tube M [0] _ 0 of PMOS tube M [0] _ 0, M [n] _ 1
Pole connects the drain electrode of PMOS tube M [0] _ 1 and the source electrode of PMOS tube M [0] _ 2, and the drain electrode of PMOS tube M [0] _ 2 drives as the 0th
The voltage output end OUT [0] of unit connects the drain electrode of NMOS tube M [0] _ 3 and the input terminal of phase inverter N [0], while passing through electricity
Hold C [0] ground connection, the drain electrode of source electrode connection NMOS tube M [0] _ 4 of NMOS tube M [0] _ 3 and the drain electrode of NMOS tube M [0] _ 5, reverse phase
The output end of device N [0] connects the grid of the 1st driving unit PMOS tube M [1] _ 1 and NMOS tube M [1] _ 3, NMOS tube M [0] _ 4,
The source level of M [0] _ 5 is grounded, and PMOS tube M [0] _ 1 and NMOS tube M [0] _ 3 grid connect power supply.
The source level of PMOS tube M_1 connects power supply, one end of drain electrode connection current source I_1, another termination of current source I_1
Ground., the grid of grid connection PMOS tube M [0] _ 0~M [N-1] _ 0；The open and close of current source I_1 are controlled by UP signal,
When UP signal is high, current source I_1 is opened, when UP signal is low, current source I_1 shutdown.
The one end current source I_2 connects power supply, and the other end connects the drain electrode of NMOS tube M_2, and the source electrode of NMOS tube M_2 is grounded,
The grid of grid connection NMOS tube M [0] _ 5~M [N-1] _ 5 of NMOS tube M_2.The open and close of current source I_2 pass through DOWN
Signal control, when DOWN signal is high, current source I_2 is opened, when DOWN signal is low, current source I_2 shutdown.
There are four types of operating modes for each subelement.By taking Cell [n] as an example, M [n] _ 1 and M [n] _ 3 are controlled by signal X [n], M
[n] _ 2 and M [n] _ 4 are controlled by signal X [n+2].
Mode 1:X [n] and X [n+2] is logical zero.M [n] _ 1 and M [n] _ 2 conducting, M [n] _ 3 and M [n] _ 4 shutdown, IUP
It persistently charges to capacitor C [n]；
Mode 2:X [n] is that 0, X [n+2] is logic 1.M [n] _ 1 and M [n] _ 4 conducting, M [n] _ 2 and M [n] _ 3 shutdown.It is defeated
Current state is kept out；
Mode 3:X [n] is that 1, X [n+2] is logical zero.M [n] _ 2 and M [n] _ 3 conducting, M [n] _ 1 and M [n] _ 4 shutdown.It is defeated
It is connected with Iup and Idown out.Output state determines the charge and discharge of capacitor C [n] by Idown-Iup's；
Mode 4:X [n] and X [n+2] is logic 1.M [n] _ 1 and M [n] _ 2 shutdown, M [n] _ 3 and M [n] _ 4 conducting,
IDOWNTo capacitor C [n] continuous discharge.
Circuit specific works situation are as follows: when powering on, output OUT [19:0] is reset to high level, and Cell [19:1] locates
In 1 state of mode, it is shown in fig. 5 1. to correspond to timing；For Cell [0], X [0] meets VDD, and X [2] is low level, Cell [0]
In mode 3, OUT [0] determines the charge and discharge of capacitor by Idown-Iup.Phaselocked loop is in acquisition phase, Idown- at this time
Iup discharges to capacitor, and when design can be designed as charge or discharge, and the present invention increases for discharging, and constantly, OUT [0]
Constantly discharged.When OUT [0] is lower than phase inverter threshold value, X [1] becomes high level, and Cell [1] enters mode 3, repeats Cell
The change of the process before [0], i.e. OUT [1] state determines the charge and discharge to capacitor by Idown-Iup, corresponds to timing diagram 5
Shown in 2..It is worth noting that, making X [2] become high level, Cell [0] if OUT [1] is pulled below phase inverter threshold value
Mode 4 can be entered, OUT [0] can accelerate discharge process, as shown in Figure 5 3..Work as phase lock loop locks, the control voltage of OUT [1] will
Stablize in fixed voltage, as shown in Figure 5 A 4., when phaselocked loop is still capturing, Cell [2] will be begun turning, the control of OUT [1]
Voltage stabilization is in low potential, B 4. as shown in Figure 5.The overall permanence of circuit can be summarized as: the overturning of previous subelement output
The variation of the latter subunit state can be triggered, the overturning of the latter subelement output can accelerate the variation of previous output.Directly
To phase lock loop locks, 20 groups of Cell stop overturning, and OUT [19:0] exports 20 groups of stable control voltages.
From the description above it will be seen that self-adaptive driving circuit can be by Idown-Iup in acquisition procedure to electricity
The accumulation situation of the charge and discharge of appearance i.e. input clock and output clock phase difference is converted into control voltage OUT [19:0], this
Sample realization automatically configures.
The signal of the OUT [19:0] of adaptive driving output, into first voltage-current converter 104, as shown in fig. 6,
The module is the current source of 20 groups of PMOS composition, the control voltage OUT [19:0] generated by self-adaptive driving circuit, control 20
The electric current I that a current source is formedCPSize.
First voltage-current converter includes PMOS tube M2_ [0]~M2_ [N-1], PMOS tube M2_ [0]~M2_ [N-1]
Sources connected in parallel be connected on power supply, PMOS tube M2_ [0]~M2_ [N-1] grid is respectively connected to the electricity of adaptive driver
It presses output end OUT [0]~OUT [N-1], PMOS tube M2_ [0]~M2_ [N-1] drain electrode is connected in parallel, output coarse adjustment control
Electric current Icp.
Charge pump 105 is as a charge switch, the voltage pulse " UP " detected according to phase frequency detector and " DOWN "
Decision is charge to be pumped into loop filter or pump out charge from loop filter.It is the reverse phase letter of UP signal
Number,It is the inversion signal of DOWN signal.The charge pump circuit figure that the present invention uses is as shown with 7.
The charge pump includes NMOS tube N1_1, N1_2, PMOS tube P1_1, P1_2, capacitor C1_1, amplifier A1_1, electricity
Stream source I_3, I_4；The grid of PMOS tube P1_1 and the grid of PMOS tube P1_2 are separately connected phase signalAnd UP；NMOS
The grid of pipe N1_1 and the grid of NMOS tube N1_2 be separately connected phase signal DOWN andThe source of PMOS tube P1_1
The source electrode of pole and PMOS tube P1_2 connect current source I_3 jointly；The source electrode of NMOS tube N1_1 and the source electrode of NMOS tube N1_2 are common
Connect current source I_4；The drain electrode of PMOS tube P1_1 and draining with NMOS tube N1_1 is grounded by capacitor C1_1, while being connected to electricity
The output end of lotus pump and the electrode input end of amplifier A1_1；The negative input of amplifier A1_1 is connected to amplifier A1_1's
Output end；The output end of amplifier A1_1 is connected to the drain electrode of PMOS tube P1_2 simultaneously and drains with NMOS tube N1_2.
“UP”、" DOWN " andControl switch pipe P1_2, P1_1, N1_1 and N1_2 are opened respectively
It opens and turns off.First voltage-current converter output ICPReference current as current source in charge pump.Current source I_3 and
It is electrically operated to carry out charge and discharge to loop filter C1_1 for the I_4 mirror image reference current.The structure is a kind of differential charge pump, is compared
In single-ended charge pump, differential charge pump is stronger to power supply and substrate noise rejection ability, this is for paying attention to noise inhibiting ability
It is significant for phaselocked loop.In order to reduce the mismatch of pull-up current and pull-down current, unity gain amplifier A1_1 pincers is used
Position output node VCTRLWith mirror nodes VEVoltage, reduce charge share effect.
The voltage V of loop filter outputCTRLThe control voltage OUT [19:0] generated with self-adaptive driving circuit is by the
Two voltage-current converters 106 are converted to the control electric current I of ring oscillatorCTRL, Voltage to current transducer -2 was as shown in figure 8, should
Module includes PMOS tube M3_ [0]~M3_ [N-1], M4_ [0]~M4_ [N-1], M5_ [0]~M5_ [N-1]；
PMOS tube M3_ [0]~M3_ [N-1], M5_ [0]~M5_ [N-1] sources connected in parallel are connected on power supply, M5_ [0]
The drain electrode of~M5_ [N-1] is connected to M4_ [0]~M4_ [N-1] source electrode, PMOS tube M3_ [0]~M3_ [N-1] grid difference
It is connected to voltage output end OUT [0]~OUT [N-1] of adaptive driver, M4_ [0]~M4_ [N-1] grid and PMOS tube
M3_ [0]~M3_ [N-1] gate connected in parallel is connected to voltage output end OUT [0]~OUT [N-1] of adaptive driver；M5_
[0] the gate connected in parallel connection control voltage signal V of~M5_ [N-1]CTRL, PMOS tube M3_ [0]~M3_ [N-1], M4_ [0]~
The drain electrode of M4_ [N-1] is connected in parallel, output control electric current ICTRLTo ring oscillator.
Ring oscillator 107 generates output clock signal, for analog-digital converter, wherein the phaselocked loop requirement being embedded in
There is bigger tuning range, need wider frequency band, and requires have very high integrated level, therefore ring oscillator is more preferable
Selection.The annular ring oscillator that the present invention is constituted using the constrained phase inverter of tertiary current, as figure 9.The module includes
NMOS tube M7_ [0]~M7_ [2] and M9, PMOS tube M6_ [0]~M6_ [2] and M8, capacitor C2_1, resistance R_1, phase inverter N2_
1.PMOS tube M6_ [0]~M6_ [2] drain electrode now connects with NMOS tube M7_ [0]~M7_ [2] drain electrode respectively, the leakage of M6_ [0] with
The grid of M6_ [1] are connected, and the leakage of M6_ [1] is connected with the grid of M6_ [2], and the leakage of M6_ [2] is connected with the grid of M6_ [0], NMOS tube
M7_ [0]~M7_ [2] source grounding, PMOS tube M6_ [0]~M6_ [2] sources connected in parallel links together, by ICTRLNote
Enter electric current.One end of capacitor C2_1 is connected with the leakage of M6_ [2], and one end is connected with resistance R_1.The source electrode of PMOS tube M8 connects power supply,
Drain electrode connects the drain electrode of NMOS tube M9, the source electrode ground connection of M9, and the grid of M9 is connected with the grid of M8, capacitor C2_1 and resistance R_1.M8
Drain electrode be connected with the input terminal of resistance R_1 and phase inverter N2_1.
Ring oscillator passes through ICTRLThe size of current of current limited type phase inverter is controlled, and then controls ring oscillator
Frequency of oscillation.The DC component of capacitor C2_1 isolation annular oscillator.The input and output parallel connection one for the phase inverter that M8 and M9 is constituted
The resistance R_1 of a big resistance value, when AC signal is not added in the inverter input, due to the threshold voltage V of M8TPWith the threshold value of M9
Voltage VTNSymmetrically, and absolute value is equal, this resistance makes the DC component of input AC clock be pulled to the threshold point of phase inverter,
That is VDD/2, and this is a unique stable state.When input terminal addition AC signal, linearly put since phase inverter is biased in
The center of great Qu, the amplification of phase inverter can make exchange clock become the digital dock of full swing, and buffer by output
Device N2_1 stablizes output clock CLKOUT。
The basic functional principle of phase-locked loop circuit of the invention is: frequency divider refers to input by different frequency division coefficients
Clock CLKINWith output clock CLKOUTFrequency dividing, the clock after frequency dividing are respectively CLK2 and CLK1, phase frequency detector compare CLK2 and
Phase difference between CLK1 signal exports to indicate that output clock still lags behind the phase signal " UP " of input clock in advance
" DOWN "." UP " and " DOWN " input adaptive driving circuit controls current mirror reference electricity above and below in self-adaptive driving circuit
The presence or absence of the on-off of stream, and then control electric current Iup and Idown.Self-adaptive driving circuit is by input clock in acquisition procedure and defeated
The accumulation situation of clock skew out is converted into accordingly controlling voltage OUT [19:0].Adaptively it is driven through coarse adjustment and fine tuning two
Quick lock in and adaptive bandwidth are realized in road.Coarse adjustment access: control voltage OUT [19:0] is by second voltage-electric current conversion
Device generates control electric current ICTRLDirectly control the frequency of oscillation of ring oscillator；Fine tuning access: control voltage OUT [19:0] warp
First voltage-current converter is crossed, electric current I is generatedCPControlled the size of current of charge pump.Charge pump is defeated according to phase frequency detector
Phase signal " UP " out and " DOWN " decision are charge to be pumped into loop filter or by charge from loop filter
It pumps out.First voltage-current converter output ICPAs the reference current of charge pump current mirror, the charge and discharge of charge pump are controlled
Size of current.The voltage V of loop filter outputCTRLPass through with the control voltage OUT [19:0] that self-adaptive driving circuit generates
Second voltage-current converter is converted to the control electric current I of ring oscillatorCTRL, ring oscillator is according to control electric current ICTRLIt is real
Existing different frequency of oscillation.Finally holding phase difference is between two signals of phase frequency detector input terminal in the state of ideal
Zero.
It should be noted that, although to related specific clock circuit and composition mould in a specific embodiment of the invention
Block is described, but the description carried out to these physical circuits is intended merely to illustrate the contents of the present invention.This is not being departed from
Under the premise of inventive principle, various effective change and modification can also be made to example of the invention, but its modification will all be fallen
Within the scope of the invention as claimed.Therefore the present invention is extensive.
Unaccomplished matter of the present invention belongs to techniques well known.
Claims (10)
1. a kind of adaptive wideband phase-locked loop circuit, it is characterised in that: including phase frequency detector (102), adaptive driver
(103), first voltage-current converter (104), charge pump (105), loop filter (108), voltage controlled oscillator, in which:
Adaptive driver (103) is believed according to the lagging phase difference signal of phase frequency detector (102) output and leading phase potential difference
Number, the phase difference that phaselocked loop exports clock and reference clock is accumulated, obtains coarse adjustment control voltage, and coarse adjustment control voltage is defeated
Out to first voltage-current converter (104)；
Coarse adjustment control voltage is converted into coarse adjustment control electric current by first voltage-current converter (104)；
Charge pump, using the image current of coarse adjustment control electric current as current source, according to leading phase difference signal " UP " and lag
Charge is pumped into loop filter or pumps out charge from loop filter, exports voltage-controlled vibration by phase signal " DOWN "
Swing the control voltage signal V of deviceCTRL；
Voltage controlled oscillator, in control voltage signal VCTRLControl under export clock signal, while using the clock signal as locking phase
The output clock feedback of ring is to phase frequency detector (102) input terminal.
2. a kind of adaptive wideband phase-locked loop circuit according to claim 1, it is characterised in that: the voltage controlled oscillator packet
Include second voltage-current converter (106) and ring oscillator (107)；
Second voltage-current converter (106), the control voltage signal V that loop filter is exportedCTRLBe converted to control electric current
Signal ICTRLIt exports to ring oscillator；
Ring oscillator, in control current signal ICTRLControl under export clock signal, while using the clock signal as locking phase
The output clock value of ring feeds back to phase frequency detector (102) input terminal.
3. a kind of adaptive wideband phase-locked loop circuit according to claim 2, it is characterised in that: adaptive driver
(103) coarse adjustment is also controlled into voltage output to second voltage-current converter (106), second voltage-current converter (106)
Coarse adjustment control voltage is converted into coarse adjustment control electric current, while coarse adjustment being controlled to the control voltage of voltage and loop filter output
Signal VCTRLGate voltage signal as cascode current source generates fine tuning control electric current, then coarse adjustment control electric current and fine tuning are controlled
Electric current superposition processed, by the control electric current I after superpositionCTRLIt exports to ring oscillator.
4. a kind of adaptive wideband phase-locked loop circuit according to claim 2, it is characterised in that: it further include frequency divider, point
Frequency device carries out scaling down processing to the output clock of externally input reference clock and phaselocked loop respectively, by the output clock after frequency dividing
CLK1 is sent to phase frequency detector (102) with the reference clock CLK2 after frequency dividing, output clock and reference clock tool after frequency dividing
There is identical frequency；
Phase frequency detector (102), the phase between the reference clock CLK2 after output clock CLK1 and frequency dividing after detecting frequency dividing
Difference, and export the lagging phase difference signal " DOWN " and table of the reference clock that the output clock after indicating frequency dividing lags behind after frequency dividing
Output clock after showing frequency dividing is ahead of the leading phase difference signal " UP " of the reference clock after frequency dividing.；
Voltage controlled oscillator exports clock signal under the control of control voltage signal, while using the clock signal as phaselocked loop
Output clock feedback to frequency divider input terminal.
5. a kind of adaptive wideband phase-locked loop circuit according to claim 4, it is characterised in that: the frequency divider is not using
Same frequency division coefficient carries out scaling down processing, the frequency dividing system to the output clock of externally input reference clock and phaselocked loop respectively
Number can be arranged by external control signal.
6. a kind of adaptive wideband phase-locked loop circuit according to claim 1, it is characterised in that: the adaptive driver
It (103) include N number of driving unit, current source I_1, current source I_2, PMOS tube M_1, NMOS tube M_2, in which:
N-th of driving unit, including PMOS tube M [n] _ 0, M [n] _ 1, M [n] _ 2, NMOS tube M [n] _ 3, M [n] _ 4, M [n] _ 5,
Capacitor C [n], phase inverter N [n]；The drain electrode connection of the source electrode connection power supply, PMOS tube M [n] _ 0 of PMOS tube M [n] _ 0, M [n] _ 1
The drain electrode of PMOS tube M [n] _ 1 and the source electrode of PMOS tube M [n] _ 2, the drain electrode of PMOS tube M [n] _ 2 is as n-th driving unit
Voltage output end OUT [n] connects the drain electrode of NMOS tube M [n] _ 3 and the input terminal of phase inverter N [n], while passing through capacitor C [n]
Ground connection, the drain electrode of source electrode connection NMOS tube M [n] _ 4 of NMOS tube M [n] _ 3 and the drain electrode of NMOS tube M [n] _ 5, NMOS tube M [n] _
4, the source level ground connection of M [n] _ 5.The output end of phase inverter N [n] connects (n+1)th driving unit PMOS tube M [n+1] _ 1 and NMOS
The grid of the PMOS tube M [n-1] _ 2 and NMOS tube M [n-1] _ 4 of the grid of pipe M [n+1] _ 3 and (n-1)th driving unit, n=1
~N-2.
The N-1 driving unit includes PMOS tube M [N-1] _ 0, M [N-1] _ 1, M [N-1] _ 2, NMOS tube M [N-1] _ 3, M [N-
1] _ 4, M [N-1] _ 5, capacitor C [N-1], phase inverter N [N-1]；The source electrode of PMOS tube M [N-1] _ 0 and the source electrode of M [N-1] _ 1 connect
Connect the drain electrode of drain electrode connection PMOS tube M [N-1] _ 1 of power supply, PMOS tube M [N-1] _ 0, the drain electrode connection of PMOS tube M [N-1] _ 1
The source electrode of PMOS tube M [N-1] _ 2, voltage output end OUT of the drain electrode of PMOS tube M [N-1] _ 2 as the N-1 driving unit
[N-1] connects the drain electrode of NMOS tube M [N-1] _ 3 and the input terminal of phase inverter N [N-1], while being grounded by capacitor C [N-1],
The output end of phase inverter N [N-1] connects the grid of the PMOS tube M [N-2] _ 2 and NMOS tube M [N-2] _ 4 of the N-2 driving unit
Pole, the drain electrode of source electrode connection NMOS tube M [N-1] _ 4 of NMOS tube M [N-1] _ 3 and the drain electrode of NMOS tube M [N-1] _ 5, NMOS tube M
The source level of [N-1] _ 4, M [N-1] _ 5 are grounded.The grounded-grid of PMOS tube M [N-1] _ 2 and NMOS tube M [N-1] _ 4.
0th driving unit, including PMOS tube M [0] _ 0, M [0] _ 1, M [0] _ 2, NMOS tube M [0] _ 3, M [0] _ 4, M [0] _ 5,
Capacitor C [0], phase inverter N [0]；The drain electrode connection of the source electrode connection power supply, PMOS tube M [0] _ 0 of PMOS tube M [0] _ 0, M [n] _ 1
The drain electrode of PMOS tube M [0] _ 1 and the source electrode of PMOS tube M [0] _ 2, the drain electrode of PMOS tube M [0] _ 2 is as the 0th driving unit
Voltage output end OUT [0] connects the drain electrode of NMOS tube M [0] _ 3 and the input terminal of phase inverter N [0], while passing through capacitor C [0]
Ground connection, the drain electrode of source electrode connection NMOS tube M [0] _ 4 of NMOS tube M [0] _ 3 and the drain electrode of NMOS tube M [0] _ 5, phase inverter N [0]
Output end connect the grid of the 1st driving unit PMOS tube M [1] _ 1 and NMOS tube M [1] _ 3, NMOS tube M [0] _ 4, M [0] _ 5
Source level ground connection, PMOS tube M [0] _ 1 and NMOS tube M [0] _ 3 grid connect power supply.
The source level of PMOS tube M_1 connects power supply, one end of drain electrode connection current source I_1, the other end ground connection of current source I_1, grid
Pole connects the grid of PMOS tube M [0] _ 0~M [N-1] _ 0；The open and close of current source I_1 are controlled by UP signal, when UP believes
Number for it is high when, current source I_1 open, when UP signal be it is low when, current source I_1 shutdown.
The one end current source I_2 connects power supply, and the other end connects the drain electrode of NMOS tube M_2, the source electrode ground connection of NMOS tube M_2, NMOS
The grid of grid connection NMOS tube M [0] _ 5~M [N-1] _ 5 of pipe M_2.The open and close of current source I_2 pass through DOWN signal
Control, when DOWN signal is high, current source I_2 is opened, when DOWN signal is low, current source I_2 shutdown.
7. a kind of adaptive wideband phase-locked loop circuit according to claim 1, it is characterised in that: the first voltage-electricity
Stream transformer (104) includes PMOS tube M2_ [0]~M2_ [N-1], the connection of PMOS tube M2_ [0]~M2_ [N-1] sources connected in parallel
On power supply, PMOS tube M2_ [0]~M2_ [N-1] grid is respectively connected to the voltage output end OUT [0] of adaptive driver
~OUT [N-1], PMOS tube M2_ [0]~M2_ [N-1] drain electrode are connected in parallel, and output coarse adjustment controls electric current Icp.
8. a kind of adaptive wideband phase-locked loop circuit according to claim 2, it is characterised in that: the second voltage-electricity
Stream transformer (106) includes PMOS tube M3_ [0]~M3_ [N-1], M4_ [0]~M4_ [N-1], M5_ [0]~M5_ [N-1]；
PMOS tube M3_ [0]~M3_ [N-1], M5_ [0]~M5_ [N-1] sources connected in parallel are connected on power supply, M5_ [0]~M5_
The drain electrode of [N-1] is connected to M4_ [0]~M4_ [N-1] source electrode, and PMOS tube M3_ [0]~M3_ [N-1] grid is separately connected
To voltage output end OUT [0]~OUT [N-1] of adaptive driver, M4_ [0]~M4_ [N-1] grid and PMOS tube M3_
[0] gate connected in parallel of~M3_ [N-1] is connected to voltage output end OUT [0]~OUT [N-1] of adaptive driver；M5_[0]
The gate connected in parallel connection control voltage signal V of~M5_ [N-1]CTRL, PMOS tube M3_ [0]~M3_ [N-1], M4_ [0]~M4_
The drain electrode of [N-1] is connected in parallel, output control electric current ICTRLTo ring oscillator.
9. a kind of adaptive wideband phase-locked loop circuit according to claim 2, it is characterised in that: the charge pump includes
NMOS tube N1_1, N1_2, PMOS tube P1_1, P1_2, capacitor C1_1, amplifier A1_1, current source I_3, I_4；
The grid of NMOS tube N1_1 and the grid of NMOS tube N1_2 are separately connected leading phase difference signal and leading phase difference signal
Inversion signal；The grid of PMOS tube P1_1 and the grid of PMOS tube P1_2 are separately connected the inversion signal of lagging phase difference signal
With lagging phase difference signal；The source electrode of PMOS tube P1_1 and the source electrode of PMOS tube P1_2 connect current source I_3 jointly；NMOS tube
The source electrode of N1_1 and the source electrode of NMOS tube N1_2 connect current source I_4 jointly；The drain electrode of PMOS tube P1_1 and with NMOS tube N1_1
Drain electrode is grounded by capacitor C1_1, while being connected to the output end of charge pump and the electrode input end of amplifier A1_1；Amplifier
The negative input of A1_1 is connected to the output end of amplifier A1_1；The output end of amplifier A1_1 is connected to PMOS tube simultaneously
The drain electrode of P1_2 and with NMOS tube N1_2 drain.
10. a kind of adaptive wideband phase-locked loop circuit according to claim 1, it is characterised in that: the reference clock frequency
Rate range is 1GHz to 4GHz, duty ratio 50%.
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111682875A (en) * | 2020-04-23 | 2020-09-18 | 西安电子科技大学 | Self-adaptive correction circuit for non-uniformity of APD array |
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| US11742864B2 (en) * | 2019-04-23 | 2023-08-29 | Microsoft Technology Licensing, Llc | Adaptive phase lock loop that adjusts its phase difference target |
| US20220393689A1 (en) * | 2019-04-23 | 2022-12-08 | Microsoft Technology Licensing, Llc | Adaptive phase lock loop that adjusts its phase difference target |
| CN112311389A (en) * | 2019-10-09 | 2021-02-02 | 成都华微电子科技有限公司 | Charge pump current mismatch compensation circuit, charge pump and phase-locked loop |
| CN112311389B (en) * | 2019-10-09 | 2023-08-18 | 成都华微电子科技股份有限公司 | Charge pump current mismatch compensation circuit, charge pump and phase-locked loop |
| CN113054997B (en) * | 2019-12-26 | 2022-08-19 | 吉林大学 | Quick locking delay phase-locked loop |
| CN113054997A (en) * | 2019-12-26 | 2021-06-29 | 吉林大学 | Quick locking delay phase-locked loop |
| CN113315512A (en) * | 2020-02-27 | 2021-08-27 | 精工爱普生株式会社 | Charge pump circuit, PLL circuit, and oscillator |
| CN113315512B (en) * | 2020-02-27 | 2023-06-20 | 精工爱普生株式会社 | Charge pump circuit, PLL circuit, and oscillator |
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| CN111682875A (en) * | 2020-04-23 | 2020-09-18 | 西安电子科技大学 | Self-adaptive correction circuit for non-uniformity of APD array |
| CN113949263A (en) * | 2020-07-15 | 2022-01-18 | 上海江波龙微电子技术有限公司 | Charge pump, clock generation circuit thereof and memory |
| CN113949263B (en) * | 2020-07-15 | 2024-02-20 | 上海江波龙微电子技术有限公司 | Charge pump, clock generation circuit thereof and memory |
| CN112383304B (en) * | 2020-10-13 | 2021-06-08 | 华南理工大学 | Charge pump phase-locked loop based on unipolar thin film transistor, chip and method |
| CN112383304A (en) * | 2020-10-13 | 2021-02-19 | 华南理工大学 | Charge pump phase-locked loop based on unipolar thin film transistor, chip and method |
| WO2023202087A1 (en) * | 2022-04-18 | 2023-10-26 | 加特兰微电子科技(上海)有限公司 | Phase lock loop device, locking method for phase lock loop device and radar system |
| CN115220512A (en) * | 2022-08-10 | 2022-10-21 | 山东大学 | Automatic phase-locking constant current source circuit and method for driving tunable laser |
| CN115220512B (en) * | 2022-08-10 | 2023-10-17 | 山东大学 | Automatic phase-locking constant current source circuit and method for driving tunable laser |
| CN116979959A (en) * | 2023-09-21 | 2023-10-31 | 深圳市九天睿芯科技有限公司 | Phase-locked loop, chip and electronic equipment |
| CN116979959B (en) * | 2023-09-21 | 2024-01-30 | 深圳市九天睿芯科技有限公司 | Phase-locked loop, chip and electronic equipment |
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