CN102136840A - Automatic biasing phase-locked loop - Google Patents

Abstract

The invention discloses an automatic biasing phase-locked loop which comprises a phase-frequency detector, a charge pump, a loop filter, a bias generator, a voltage-controlled oscillator, a frequency divider and a reference voltage generator, wherein the reference voltage generator generates a reference voltage corresponding to the bias current of the voltage-controlled oscillator and provides the reference voltage to the charge pump, the charge pump regulates the output current according to the reference voltage, the output current of the charge pump is equal to the ratio of the bias current generated by the voltage-controlled oscillator to the value two times of the frequency dividing number of the frequency divider, the loop filter at least comprises a loop filter resistor and a loop filter capacitor which are connected in series, a switching capacitor is adopted as the loop filter resistor, and the switching frequency of the switching capacitor is equal to the frequency of input signals. The ratio of the loop bandwidth of the automatic biasing phase-locked loop to the input frequency and a damping factor are maintained the same all the time, and the circuit is simple.

Description

Self-biased phase-locked loop

Technical field

The present invention relates to the phase-locked loop circuit designing technique, particularly the self-biased phase-locked loop technology.

Background technology

Along with the development of contemporary microelectric technique, microprocessor and PC/ workstation system dominant frequency and performance improve, and the clock forming circuit design of system has been proposed more and more higher requirement.And phase-locked loop (PLL, PhaseLocked Loop) is widely used in the system level chip (SOC, System on Chip) as a kind of designing technique commonly used, to constitute clock forming circuit.

Fig. 1 is a kind of basic structure of phase-locked loop, and phase frequency detector (PFD, Phase FrequencyDetector) 10 detects input signal F _RefWith feedback signal F _FbFrequency difference and differ, produce pulse control signal UP, DN and send into charge pump (CP, charge pump) 20; In charge pump 20, pulse control signal UP, DN are converted into electric current I _pCapacitor C to loop filter (LP, Loop Filter) 30 _pDischarge and recharge, loop filter 30 produces control voltage V _CtrlSend into voltage controlled oscillator (VCO, Voltage ControlOscillator) 40; Voltage controlled oscillator 40 is at control voltage V _CtrlAccelerate frequency of oscillation during rising, at control voltage V _CtrlFrequency of oscillation slows down during reduction.The output signal F of voltage controlled oscillator 40 _OutProduce feedback signal F through frequency divider 50 _Fb, whole phase-locked loop structures forms a reponse system, output signal F _OutFrequency and phase place be locked into fixed frequency and phase place.

The damping factor of the loop of phase-locked loop shown in Figure 1 (damping factor) ξ is by formula (1) expression, loop bandwidth ω _nRepresent by formula (2):

$\mathrm{\ξ}=\frac{R_p}{2}\sqrt{\frac{I_p{K}_v{C}_p}{2\mathrm{\ΠN}}}---\left(1\right)$

${\mathrm{\ω}}_n=\sqrt{\frac{I_p{K}_v}{2\mathrm{\Π}{\mathrm{NC}}_p}}---\left(2\right)$

Wherein, C _pBe the electric capacity of loop filter 30, R _pBe the resistance of loop filter 30, I _pFor to capacitor C _pCarry out the electric current (being the charge or discharge electric current of charge pump 20 outputs) of charge or discharge, K _vBe the gain of voltage controlled oscillator 40, N is the divider ratio of frequency divider (Divider) 50.

As previously mentioned, the clock forming circuit design to system has at present proposed more and more higher requirement, thereby also need have high-performance as the phase-locked loop of clock forming circuit.The high-performance phase-locked loop need have following characteristics: be not subject to the influence that technology, voltage and temperature (PVT) change; Bandwidth; Locking back phase jitter (jitter) and frequency change are little; The monolithic integrated filter; Circuit low in energy consumption.But the phase-locked loop that reaches these requirements simultaneously is to be difficult to design, and a typical phase-locked loop is based on voltage controlled oscillator, its phase jitter is caused by power supply and substrate noise, loop is a low pass filter for noise, and loop bandwidth is narrow more, and shake is just more little; On the other hand, because single chip integrated requirement, the electric capacity of filter can not be done very greatly, and bandwidth is subjected to the restriction of loop stability condition simultaneously again, and these restrictive conditions make that the phase-locked loop operation frequency band of design is narrow, and jitter performance is also bad.

A kind ofly can improve the method that bandwidth can obtain low jitter again, be the bandwidth that changes phase-locked loop, the operating frequency that enables to follow the tracks of phase-locked loop.In each operating state, the smaller bandwidth of loop is shaken also for a short time, still, because the bandwidth of phase-locked loop changes, has in fact obtained the frequency range of non-constant width, and has reduced phase place and frequency jitter by the noise introducing.Automatic biasing a kind of method that comes to this adopts the phase-locked loop of automatic biasing method design, and the damping factor ξ of its loop is fixed value (damping factor is 1 usually).Damping factor ξ, loop bandwidth ω _nAngular frequency with input signal _Ref(be designated hereinafter simply as incoming frequency, ω _Ref=2 π F _Ref, F _RefFrequency for input signal) ratio is only determined by the relative value of electric capacity in the manufacturing process.

Technical literature " Low-Jitter Process-Independent DLL and PLL Based onSelf-Biased Techniques " (John G.Maneatis, IEEE JOURNAL OF SOLID-STATECIRCUITS, VOL.31, NO.11, NOVEMBER 1996) a kind of basic structure of self-biased phase-locked loop disclosed, as shown in Figure 2, capacitor C ₁Constitute loop filters 31 with biasing maker 60, that is to say, set up the resistance of loop filter 31 by biasing maker 60, at the bias voltage V of biasing maker 60 _BPOutput add the electric current of an extra charge pump 21 output, like this, 20 pairs of capacitor C of charge pump ₁Discharge and recharge, the resistance that 21 pairs of biasing makers of charge pump 60 are set up discharges and recharges.

Biasing maker 60 is used for from control voltage V _CTRLGenerate bias voltage V _BPAnd V _BN, so that the input voltage of voltage controlled oscillator 41 to be provided.As shown in Figure 3, biasing maker 60 comprises biasing initialization (Bias Init.) circuit 601, amplifier biasing (Amplifier Bias) circuit 602, difference amplification (Diff.Amplifier) circuit 603, half buffered copy (Half-Buffer Replica) circuit 604 and control voltage buffering (V _CTRLBuffer) circuit 605.Amplifier biasing circuit 602 provides biasing for differential amplifier circuit 603, and differential amplifier circuit 603 is regulated bias voltage V _BN, make half buffered copy circuit 604 and control voltage buffer circuit 605 will control voltage V _CTRLCopy to the bias voltage V of output _BP, i.e. V _BP=V _CTRL

The voltage controlled oscillator 40 of basic phase-locked loop shown in Figure 1 normally is made of the buffer stage of a plurality of differential configurations, and the voltage controlled oscillator 41 of self-biased phase-locked loop shown in Figure 2 is with the differential buffer delay stages of balanced load to constitute by n (n 〉=2), the voltage controlled oscillators 41 that the differential buffer delay stages 410 of 3 band balanced loads for example shown in Figure 4 constitutes.Bias voltage V _BNFor balanced load 411,412 provides bias current 2I _D(I _DFor flowing through the electric current of balanced load 411 or 412), the bias voltage V of balanced load 411,412 _BPEqual to control voltage V _CTRL, the equivalent resistance of balanced load 411,412 equals 1/2g _m, g _mBe transistorized mutual conductance in the balanced load, along with control voltage V _CTRLVariation, the resistance of balanced load 411,412 changes, the time-delay of buffer stage also changes, the frequency of the output signal of voltage controlled oscillator 41 (CK+ or CK-) changes.

If the electric current I of charge pump 20,21 outputs _pBias current 2I for voltage controlled oscillator 41 _DX doubly, i.e. I _p=x2I _D, the resistance R of establishing the loop filter 31 that balanced load 606 is set up in the biasing maker 60 _pEquivalent resistance R for the buffer stage 410 of voltage controlled oscillator 41 _oY doubly, i.e. R _p=yR _o=y/2g _mTherefore, the damping factor ξ of the loop of self-biased phase-locked loop shown in Figure 2 is by formula (3) expression, loop bandwidth ω _nWith incoming frequency ω _RefRatio represent by formula (4):

$\mathrm{\ξ}=\frac{y}{4}\sqrt{\frac{x}{N}}\sqrt{\frac{C_1}{C_B}}---\left(3\right)$

$\frac{{\mathrm{\ω}}_n}{{\mathrm{\ω}}_{\mathrm{ref}}}=\frac{\mathrm{xN}}{2\mathrm{\π}}\sqrt{\frac{C_B}{C_1}}---\left(4\right)$

Wherein, C _BIt is the parasitic capacitance of voltage controlled oscillator 41.

Like this, from ideal situation, if the ratio ω of ξ and loop bandwidth and incoming frequency _n/ ω _RefAll be constant, loop bandwidth can be followed the tracks of operating frequency all the time, and phase-locked loop for operating frequency just without limits.Yet, from formula (3) and (4), notice the ratio ω of damping factor ξ and loop bandwidth and incoming frequency _n/ ω _RefAlso there is relation with the ratio of the equivalent resistance of the buffer stage of ratio, loop filter resistance and the voltage controlled oscillator of divider ratio N, charge pump output current and the voltage controlled oscillator bias current of frequency divider in the phase-locked loop 50.Therefore, the ratio ω of the damping factor ξ of phase-locked loop and loop bandwidth and incoming frequency _n/ ω _RefCan't be only by capacitor C in the manufacturing process _B, C ₁Relative value decision.

In addition, prior art self-biased phase-locked loop as shown in Figure 2 need be provided with 2 charge pumps and respectively the resistance and the electric capacity of loop filter be discharged and recharged, and correspondingly, self-biased phase-locked realizes also more complicated.

Summary of the invention

The problem that the present invention solves is, a kind of self-biased phase-locked loop is provided, and simplifying circuit, and obtains the more stable damping factor and the ratio of loop bandwidth and incoming frequency, the performance of raising self-biased phase-locked loop.

For addressing the above problem, the invention provides a kind of self-biased phase-locked loop, comprising:

Phase frequency detector detects the frequency difference of input signal and feedback signal and differs the generation pulse control signal;

Charge pump is according to the pulse control signal generation charge or discharge electric current of described phase frequency detector output;

Loop filter is connected with charge pump, output control voltage, and when charge pump output charging current, described loop filter raises and controls voltage; When charge pump output discharging current, described loop filter reduces control voltage;

The biasing maker, the control voltage that produces from loop filter generates first bias voltage and second bias voltage;

Voltage controlled oscillator, comprise the oscillating unit of being with balanced load, described balanced load is controlled by first bias voltage, when raising, accelerates first bias voltage frequency of oscillation of output signal, the frequency of oscillation of the output signal that slows down when first bias voltage reduces, described voltage controlled oscillator also produce bias current according to second bias voltage;

Frequency divider carries out frequency division with the output signal of voltage controlled oscillator, produces the feedback signal of the described phase frequency detector of input,

Wherein, described self-biased phase-locked loop also comprises the reference voltage maker, is connected with charge pump with voltage controlled oscillator, and described reference voltage maker generates the reference voltage of the bias current of corresponding described voltage controlled oscillator; Described charge pump is regulated output current according to described reference voltage, and the output current of described charge pump equals the bias current of described voltage controlled oscillator and 2 times ratio of frequency divider divider ratio; Described loop filter comprises at least: the loop filter resistance and the loop filter capacitance of series connection, and described loop filter resistance is switching capacity, the switching frequency of described switching capacity equals the frequency of described input signal.

Compared with prior art, above-mentioned self-biased phase-locked loop has the following advantages: by the bias current of switching capacity and charge pump output current and voltage controlled oscillator is set, the relation of frequency divider divider ratio, cancellation divider ratio, the ratio of charge pump output current and voltage controlled oscillator bias current, the influence of the factors such as equivalent resistance of the buffer stage of loop filter resistance and voltage controlled oscillator, make the ratio and the damping factor of loop bandwidth and incoming frequency, all only the electric capacity with the parasitic capacitance of voltage controlled oscillator and loop filter is relevant, in case promptly manufacturing process has been determined the parasitic capacitance of voltage controlled oscillator and the electric capacity of loop filter, the ratio of loop bandwidth and incoming frequency and damping factor will remain fixed value.Therefore, the stability of self-biased phase-locked loop is better.

And, since with the switching capacity equivalent substitution resistance, then as the charge pump of loop filter front stage circuits, only needing provide one tunnel total charging and discharging currents to get final product to loop filter.Correspondingly, the front stage circuits of loop filter only needs a charge pump to get final product, thereby has simplified the circuit of phase-locked loop.

Description of drawings

Fig. 1 is the basic structure schematic diagram of a kind of phase-locked loop of prior art;

Fig. 2 is the basic structure schematic diagram of a kind of self-biased phase-locked loop of prior art;

Fig. 3 is the circuit diagram of the biasing maker of self-biased phase-locked loop shown in Figure 2;

Fig. 4 is the circuit diagram of the voltage controlled oscillator of self-biased phase-locked loop shown in Figure 2;

Fig. 5 is a kind of execution mode circuit diagram of self-biased phase-locked loop of the present invention;

Fig. 6 is a kind of embodiment circuit diagram of self-biased phase-locked loop intermediate ring road filter of the present invention;

Fig. 7 is the another kind of embodiment circuit diagram of self-biased phase-locked loop intermediate ring road filter of the present invention.

Embodiment

The present invention is intended to realize by the equivalence of resistance in the loop filter is replaced, and the relativeness of setting up the bias current and the divider ratio of charge pump output current, voltage controlled oscillator, with the ratio of the equivalent resistance of the buffer stage of ratio, loop filter resistance and the voltage controlled oscillator of cancellation divider ratio, charge pump output current and voltage controlled oscillator bias current.

Specifically, the present invention presses following formula foundation and the bias current of voltage controlled oscillator, the relation of frequency divider divider ratio with the output current of charge pump in the phase-locked loop:

$I_p=\frac{I_D}{2N}---\left(5\right)$

And known for those skilled in the art, the gain of voltage controlled oscillator is satisfied:

$K_v=\frac{k}{C_B}---\left(6\right)$

Wherein, k is the process factor of device in the voltage controlled oscillator.

Then, formula (5), (6) substitution formula (2) can be got

${\mathrm{\ω}}_n=\sqrt{\frac{I_d}{4\mathrm{\Π}{N}^2}*\frac{1}{C_p}*\frac{k}{C_B}}---\left(7\right)$

Formula (7) is carried out conversion to be got

${\mathrm{\ω}}_n=\sqrt{\frac{{2I}_D}{8\mathrm{\Π}{N}^2}*\frac{1}{C_p}*\frac{k}{C_B}}---\left(8\right)$

And known for those skilled in the art, the output frequency of voltage controlled oscillator satisfies:

$F_{\mathrm{VCO}}=\frac{\sqrt{2k{I}_D}}{C_B}---\left(9\right)$

Wherein, F _VCOOutput frequency for voltage controlled oscillator.

Conversion gets to formula (9)

$k=\frac{F_{\mathrm{VCO}}*F_{\mathrm{VCO}}*{C_B}^2}{2I_D}---\left(10\right)$

Formula (10) substitution formula (8) is got

${\mathrm{\ω}}_n=\sqrt{\frac{F_{\mathrm{VCO}}*F_{\mathrm{VCO}}}{8\mathrm{\Π}{N}^2}*\frac{C_B}{C_p}}---\left(11\right)$

And known for those skilled in the art, satisfy between the frequency input signal of the output frequency of voltage controlled oscillator and the divider ratio of frequency divider, phase-locked loop:

F _VCO＝NF _ref (12)

And the frequency of described input signal satisfies:

ω _ref＝2∏F _ref (13)

With formula (12), formula (13) substitution formula (11),

${\mathrm{\ω}}_n=\frac{{\mathrm{\ω}}_{\mathrm{ref}}}{2\mathrm{\Π}}\sqrt{\frac{C_B}{8\mathrm{\Π}{C}_p}}---\left(14\right)$

Then according to formula (14), the ratio of loop bandwidth and incoming frequency is

$\frac{{\mathrm{\ω}}_n}{{\mathrm{\ω}}_{\mathrm{ref}}}=\sqrt{\frac{C_B}{32{\mathrm{\Π}}^3{C}_p}}---\left(15\right)$

Particularly, the present invention also in loop filter with the resistance in the switching capacity equivalent substitution loop filter, then loop filter is resistor satisfied:

$R_p=\frac{1}{F_{\mathrm{ref}}*C_s}---\left(16\right)$

Wherein, C _sCapacitance for switching capacity.

With formula (16) substitution formula (1),

$\mathrm{\ξ}=\frac{1}{2F_{\mathrm{ref}}*C_s}\sqrt{\frac{I_p{K}_v{C}_p}{2\mathrm{\ΠN}}}---\left(17\right)$

With formula (5), formula (10), formula (12) substitution formula (17), get damping factor

$\mathrm{\ξ}=\frac{1}{4C_s}\sqrt{\frac{C_B*C_p}{2\mathrm{\Π}}}---\left(18\right)$

Thereby, by formula (15), formula (18) as can be seen, the ratio of loop bandwidth and incoming frequency and damping factor, all only with the parasitic capacitance C of voltage controlled oscillator _BCapacitor C with loop filter _pRelevant, in case promptly manufacturing process has been determined the parasitic capacitance C of voltage controlled oscillator _BCapacitor C with loop filter _p, the ratio of loop bandwidth and incoming frequency and damping factor will remain fixed value.Therefore, the stability of self-biased phase-locked loop is better.

And, since with the switching capacity equivalent substitution resistance, then as the charge pump of loop filter front stage circuits, only needing provide one tunnel total charging and discharging currents to get final product to loop filter.Correspondingly, the front stage circuits of loop filter only needs a charge pump to get final product, thereby has simplified the circuit of phase-locked loop.

Below specific embodiments of the present invention is described in detail by accompanying drawing and in conjunction with above-mentioned analysis.Fig. 5 is a kind of execution mode circuit diagram of self-biased phase-locked loop of the present invention.With reference to shown in Figure 5, described self-biased phase-locked loop comprises: phase frequency detector 1, charge pump 2, loop filter 3, biasing maker 4, voltage controlled oscillator 5, frequency divider 6 and reference voltage maker 7.

Phase frequency detector 1 detects input signal F _RefWith feedback signal F _FbFrequency difference and differ, produce pulse control signal UP, DN.For example, at feedback signal F _FbPhase place lag behind input signal F _RefThe time, the pulse duration of pulse control signal UP is greater than the pulse duration of pulse control signal DN; At feedback signal F _FbPhase place be ahead of input signal F _RefThe time, the pulse duration of pulse control signal UP is less than the pulse duration of pulse control signal DN.The circuit of phase frequency detector 10 is well known to those skilled in the art, and does not launch explanation at this.

Charge pump 2 is according to pulse control signal UP, the DN generation charge or discharge electric current I of phase frequency detector 1 output _pWherein, at feedback signal F _FbPhase place lag behind input signal F _RefThe time, the pulse duration of pulse control signal UP is greater than the pulse duration of pulse control signal DN, and charge pump 2 is exported charging current I _pAt feedback signal F _FbPhase place be ahead of input signal F _RefThe time, the pulse duration of pulse control signal UP is less than the pulse duration of pulse control signal DN, and charge pump 2 is exported discharging current I _pThe reference voltage V that described charge pump 2 provides according to reference voltage maker 7 _RefRegulate the charging current of output or the size of discharging current, the size of described charging current or discharging current satisfies formula (5).

Loop filter 3 is connected with charge pump 2, output control voltage V _Ctr, loop filter 3 comprises the differential switch electric capacity and the loop filter capacitance C of series connection _pWherein, described differential switch electric capacity comprises: be controlled by first capacitor C 10 of first K switch 10, and second capacitor C, 12, two electric capacity, one end that is controlled by second switch K12 is connected in the output of charge pump 2, the other end is connected in loop filter capacitance C _pFirst end.Loop filter capacitance C _pThe second end ground connection.Total capacitance value after described first capacitor C 10 and 12 parallel connections of second capacitor C is C _sDescribed first K switch 10 and second switch K12 all are controlled by switch clock ck.At charge pump 2 output charging current I _pThe time, described loop filter 3 raises and controls voltage V _CtrAt charge pump 2 output discharging current I _pThe time, described loop filter 3 reduces control voltage V _Ctr

Biasing maker 4 is from the control voltage V of loop filter 3 generations _CtrGenerate the first bias voltage V _BPWith the second bias voltage V _BN, so that the input voltage of voltage controlled oscillator 5 to be provided.The physical circuit of described biasing maker 4 is realized same as the prior art, can realize with reference to the circuit of Fig. 3.

Voltage controlled oscillator 5 comprises the oscillating unit of being with balanced load, the second bias voltage V _BNFor balanced load provides bias current 2I _D(I _DFor flowing through the electric current of balanced load), the first bias voltage V of balanced load _BPEqual to control voltage V _Ctr, the equivalent resistance of balanced load equals 1/2g _m, g _mBe transistorized mutual conductance in the balanced load, along with control voltage V _CtrVariation, the first bias voltage V _BPAlso change, the resistance of balanced load changes, the output signal F of voltage controlled oscillator 5 _VcoFrequency change.Particularly, when raising, accelerates first bias voltage output signal F _VcoFrequency of oscillation, output signal F slows down when first bias voltage reduces _VcoFrequency of oscillation.

Reference voltage maker 7 generates the reference voltage V of the bias current that corresponding voltage controlled oscillator 5 produces _RefAnd offer charge pump 2, the I in the size of described reference voltage and the formula (5) _pCorresponding.

The output signal F of voltage controlled oscillator 4 _VcoProduce feedback signal F through frequency divider 6 _Fb, i.e. F _Fb=F _Out/ N, N are the divider ratio of frequency divider 6, and whole system forms a reponse system, output signal F _VcoFrequency and phase place be locked into fixed frequency and phase place.

Fig. 6 is a kind of embodiment circuit diagram of self-biased phase-locked loop intermediate ring road filter of the present invention.With reference to shown in Figure 6, described loop filter comprises: the first transmission gate TG1, the second transmission gate TG2, the 3rd transmission gate TG3 and the 4th transmission gate TG4, first capacitor C 10, second capacitor C 12 and a NMOS pipe MN1, the 2nd NMOS manage MN2.

The described first transmission gate TG1, the described second transmission gate TG2 are respectively as the switch of controlling described first capacitor C 10, described second capacitor C 12.Two control ends of the described first transmission gate TG1 receive the first switching signal F respectively ₁With the first switch complementary signal F _1B, two outputs are connected to first end and second end of described first capacitor C 10.Two control ends of the described second transmission gate TG2 receive second switch signal F respectively ₀With second switch complementary signal F _0B, two outputs are connected to first end and second end of described second capacitor C 12.

Two control ends of the 3rd transmission gate TG3 receive second switch signal F respectively ₀With second switch complementary signal F _0B, two control ends of the 4th transmission gate TG4 receive the first switching signal F respectively ₁With the first switch complementary signal F _1BFirst output of the 3rd transmission gate TG3 and the 4th transmission gate TG4 links to each other, and be connected in the electric charge delivery side of pump, second output of the 3rd transmission gate TG3 and the 4th transmission gate TG4 is connected to first end of first capacitor C 10 and first end of second capacitor C 12.The described first switching signal F ₁With second switch signal F ₀Complementary signal, and frequency each other and input signal F _RefFrequency identical.The 3rd transmission gate TG3 and the 4th transmission gate TG4 constitute differential configuration herein, to improve the noiseproof feature of described loop filter.

In the specific embodiment of above-mentioned transmission gate, transmission gate comprises that the source leaks corresponding PMOS pipe and the NMOS that connects and manage, and the breadth length ratio of described PMOS pipe is 2 times of breadth length ratio of NMOS pipe.

The grid of the one NMOS pipe MN1 and the 2nd NMOS pipe MN2 all is connected in second end of first capacitor C 10, second capacitor C 12, and the equal ground connection of source electrode, drain electrode and substrate is to connect into capacitive form.

Analyze circuit shown in Figure 6, by above-mentioned each switching signal control, make win capacitor C 10 and second capacitor C 12 in parallel and be connected in the grid of described NMOS pipe MN1 and the 2nd NMOS pipe MN2 with a fixed frequency, according to formula (16), but the function of the capacitive reactance equivalent substitution resistance that then forms after first capacitor C 10 and 12 parallel connections of second capacitor C this moment.

In the another kind of execution mode of self-biased phase-locked loop of the present invention, described loop filter has also increased by the 3rd electric capacity with respect to structure shown in Figure 5, and an end of described the 3rd electric capacity is connected in second end that the electric charge delivery side of pump other end is connected in loop filter capacitance.Increase by the 3rd electric capacity and realized further filtering, can further increase the ability that described loop filter suppresses high-frequency noise.

Fig. 7 is a kind of embodiment circuit diagram of the loop filter of corresponding described another kind of execution mode.With reference to Fig. 6 and shown in Figure 7, with respect to the loop filter structure of Fig. 6, Fig. 7 has only increased the 3rd NMOS pipe MN3.The grid of described the 3rd NMOS pipe MN3 is connected in the electric charge delivery side of pump, and the equal ground connection of source electrode, drain electrode and substrate is to connect into capacitive form.

In sum, the present invention passes through with switching capacity equivalent substitution resistance, and set up charge pump output current, with the bias current of voltage controlled oscillator, the relation of frequency divider divider ratio, thereby make the loop bandwidth of self-biased phase-locked loop and the ratio and the damping factor of incoming frequency, all only the electric capacity with the parasitic capacitance of voltage controlled oscillator and loop filter is relevant, and has simplified circuit.

More than disclose many aspects of the present invention and execution mode, it will be understood by those skilled in the art that others of the present invention and execution mode.Disclosed many aspects and execution mode just are used to illustrate among the present invention, are not to be limitation of the invention, and real protection range of the present invention and spirit should be as the criterion with claims.

Claims (9)

1. self-biased phase-locked loop comprises:

Phase frequency detector detects the frequency difference of input signal and feedback signal and differs the generation pulse control signal;

Charge pump is according to the pulse control signal generation charge or discharge electric current of described phase frequency detector output;

Loop filter is connected with charge pump, output control voltage, and when charge pump output charging current, described loop filter raises and controls voltage; When charge pump output discharging current, described loop filter reduces control voltage;

The biasing maker, the control voltage that produces from loop filter generates first bias voltage and second bias voltage;

Voltage controlled oscillator, comprise the oscillating unit of being with balanced load, described balanced load is controlled by first bias voltage, when raising, accelerates first bias voltage frequency of oscillation of output signal, the frequency of oscillation of the output signal that slows down when first bias voltage reduces, described voltage controlled oscillator also produce bias current according to second bias voltage;

Frequency divider carries out frequency division with the output signal of voltage controlled oscillator, produces the feedback signal of the described phase frequency detector of input,

It is characterized in that described self-biased phase-locked loop also comprises the reference voltage maker, be connected with charge pump that described reference voltage maker generates the reference voltage of the bias current of corresponding described voltage controlled oscillator with voltage controlled oscillator; Described charge pump is regulated output current according to described reference voltage, and the output current of described charge pump equals the bias current of described voltage controlled oscillator and 2 times ratio of frequency divider divider ratio; Described loop filter comprises at least: the loop filter resistance and the loop filter capacitance of series connection, and described loop filter resistance is switching capacity, the switching frequency of described switching capacity equals the frequency of described input signal.

2. self-biased phase-locked loop as claimed in claim 1 is characterized in that, described switching capacity comprises: first transmission gate, second transmission gate, the 3rd transmission gate and the 4th transmission gate, first electric capacity, second electric capacity, wherein,

Described first transmission gate, described second transmission gate are respectively as the switch of controlling described first electric capacity, described second electric capacity, two control ends of described first transmission gate receive first switching signal and the first switch complementary signal respectively, two outputs are connected to first end and second end of described first electric capacity, two control ends of described second transmission gate receive second switch signal and second switch complementary signal respectively, and two outputs are connected to first end and second end of described second electric capacity; Second end of described first electric capacity, second end of second electric capacity all are connected in first end of described loop filter capacitance;

Two control ends of the 3rd transmission gate receive second switch signal and second switch complementary signal respectively, two control ends of the 4th transmission gate receive first switching signal and the first switch complementary signal respectively, first output of the 3rd transmission gate and the 4th transmission gate links to each other, and be connected in the electric charge delivery side of pump, second output of the 3rd transmission gate and the 4th transmission gate is connected to first end of first electric capacity and first end of second electric capacity;

Described first switching signal and second switch signal be complementary signal each other, and frequency is identical with the frequency of input signal.

3. self-biased phase-locked loop as claimed in claim 2, it is characterized in that, described loop filter capacitance comprises NMOS pipe and the 2nd NMOS pipe, and the grid of NMOS pipe and the 2nd NMOS pipe all is connected in second end of first electric capacity, second electric capacity, the equal ground connection of source electrode, drain electrode and substrate.

4. as claim 2 or 3 described self-biased phase-locked loops, it is characterized in that described loop filter also comprises the 3rd electric capacity, an end of described the 3rd electric capacity is connected in second end that the electric charge delivery side of pump other end is connected in loop filter capacitance.

5. self-biased phase-locked loop as claimed in claim 4 is characterized in that, described the 3rd electric capacity comprises the 3rd NMOS pipe, and the grid of described the 3rd NMOS pipe is connected in the electric charge delivery side of pump, the equal ground connection of source electrode, drain electrode and substrate.

6. self-biased phase-locked loop as claimed in claim 1 is characterized in that, described biasing maker comprises biasing initializing circuit, amplifier biasing circuit, differential amplifier circuit, half buffered copy circuit and the control voltage buffer circuit that connects successively.

7. self-biased phase-locked loop as claimed in claim 1 is characterized in that, described first bias voltage equals described control voltage.

8. self-biased phase-locked loop as claimed in claim 1 is characterized in that, the oscillating unit of band balanced load is the differential buffer delay circuit of band balanced load.

9. self-biased phase-locked loop as claimed in claim 8 is characterized in that, described voltage controlled oscillator comprises the differential buffer delay circuit of 3 band balanced loads.

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