CN102722218A - Universal serial bus (USB) clock circuit - Google Patents
Universal serial bus (USB) clock circuit Download PDFInfo
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- CN102722218A CN102722218A CN2012101614798A CN201210161479A CN102722218A CN 102722218 A CN102722218 A CN 102722218A CN 2012101614798 A CN2012101614798 A CN 2012101614798A CN 201210161479 A CN201210161479 A CN 201210161479A CN 102722218 A CN102722218 A CN 102722218A
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Abstract
The invention discloses a universal serial bus (USB) clock circuit. The clock circuit comprises a USB interface and parallel interface switching circuit and a clock generation circuit which are electrically connected, wherein the clock generation circuit comprises an oscillating circuit, a current and voltage control circuit, a frequency dividing circuit and a processing circuit; the current and voltage control circuit, the oscillating circuit and the frequency dividing circuit are electrically connected in sequence; the processing circuit is connected between the frequency dividing circuit and the current and voltage control circuit; and the oscillating circuit is connected with a compensating circuit. Through the mode, the USB clock circuit can improve a transmission rate, is small in code quantity and has a simple and novel structure.
Description
Technical field
The present invention relates to electronic circuit field, particularly relate to a kind of USB clock circuit.
Background technology
Along with the miniaturization of the manufacturing process of SIC (semiconductor integrated circuit), the number of transistors that can install simultaneously sharply increases.Thus, can reduce number of parts, realize the decline of cost through the multifunction of circuit.Man-hour existing design circuit to be installed once more in order to reduce design.Also to install and to meet the circuit that unified specification moves with CF.And then, from through move purposes such as reducing power consumption with lower low speed, must realize being equipped with the SIC (semiconductor integrated circuit) of the circuit that moves with various frequencies.USB (Universial Serial Bus) is a kind of USB; Because it has the support hot plug; Data transmission is quick, reliable, the cost performance advantages of higher; USB has become application one of PC peripheral hardware expansion interface the most widely gradually; Thereby it is the ideal interface that realizes carrying out between electronic system and the PC data transmission; Software package after data transmission between electronic system and the PC also makes electronic system will upgrade easily through PC download in the electronic system system of realization upgrading, can also make the terminal user of product from the configurable functionality software package that manufacturer provides, select suitable software package to download to the personalization of realization product in the product, hommization simultaneously according to oneself needs.And the prior USB interface circuit exists the high-speed transfer pattern of much not supporting, transfer rate is little, and the microcontroller of USB interface performs mathematical calculations, the problem such as limited in one's ability of signal Processing.
Summary of the invention
The technical matters that the present invention mainly solves provides a kind of USB clock circuit, can improve transfer rate, and size of code is little, and is simple in structure, novel.
For solving the problems of the technologies described above; The technical scheme that the present invention adopts is: a kind of USB clock circuit is provided; Comprise: USB interface parallel port change-over circuit and clock generating circuit; Said USB interface parallel port change-over circuit and clock generating circuit electrically connect, and said clock generating circuit comprises oscillatory circuit, current/voltage control circuit, frequency dividing circuit and treatment circuit, and said current/voltage control circuit, oscillatory circuit and frequency dividing circuit electrically connect successively; Said treatment circuit is connected between frequency dividing circuit and the current/voltage control circuit, is connected with correcting circuit on the said oscillatory circuit.
In preferred embodiment of the present invention; Said current/voltage control circuit comprises frequency discrimination phase discriminator, charge pump circuit, voltage offset electric circuit and current biasing circuit; Said frequency discrimination phase discriminator and charge pump circuit electrically connect, and said voltage offset electric circuit and current biasing circuit are connected between charge pump circuit and the oscillatory circuit.
In preferred embodiment of the present invention, said treatment circuit comprises the DSP embedded processor.
In preferred embodiment of the present invention, said oscillatory circuit comprises voltage controlled oscillator.
In preferred embodiment of the present invention, said frequency dividing circuit comprises 8 frequency dividers.
The invention has the beneficial effects as follows: USB clock circuit of the present invention can improve transfer rate, and size of code is little, and is simple in structure, novel.
Description of drawings
Fig. 1 is the structural representation of USB clock circuit one preferred embodiment of the present invention;
The mark of each parts is following in the accompanying drawing: 1, USB interface parallel port change-over circuit, 2, clock generating circuit, 3, oscillatory circuit; 4, current/voltage control circuit, 5, frequency dividing circuit, 6, treatment circuit; 7, correcting circuit, 8, the frequency discrimination phase discriminator, 9, charge pump circuit; 10, voltage offset electric circuit, 11, current biasing circuit.
Embodiment
Below in conjunction with accompanying drawing preferred embodiment of the present invention is set forth in detail, thereby protection scope of the present invention is made more explicit defining so that advantage of the present invention and characteristic can be easier to it will be appreciated by those skilled in the art that.
See also Fig. 1; A kind of USB clock circuit; Comprise: USB interface parallel port change-over circuit 1 and clock generating circuit 2; Said USB interface parallel port change-over circuit 1 electrically connects with clock generating circuit 2, and said clock generating circuit 1 comprises oscillatory circuit 3, current/voltage control circuit 4, frequency dividing circuit 5 and treatment circuit 6, and said current/voltage control circuit 4, oscillatory circuit 3 electrically connect with frequency dividing circuit 5 successively; Said treatment circuit 6 is connected frequency dividing circuit 5 and current/voltage is controlled between 4 circuit, is connected with correcting circuit 7 on the said oscillatory circuit 3.
In addition; Said current/voltage control circuit 4 comprises frequency discrimination phase discriminator 8, charge pump circuit 9, voltage offset electric circuit 10 and current biasing circuit 11; Said frequency discrimination phase discriminator 8 electrically connects with charge pump circuit 9; Said voltage offset electric circuit 10 and current biasing circuit 11 are connected between charge pump circuit 9 and the oscillatory circuit 3, and this circuit converts the reference offset current replication into two-way current/voltage biasing charging and discharging circuit, makes charging and discharging currents mate fully.
In addition, said treatment circuit 6 comprises the DSP embedded processor.
In addition, said oscillatory circuit 3 comprises voltage controlled oscillator.
In addition, said frequency dividing circuit 5 comprises 8 frequency dividers.
Be different from prior art, USB clock circuit of the present invention can improve transfer rate, and size of code is little, and is simple in structure, novel.
The above is merely embodiments of the invention; Be not so limit claim of the present invention; Every equivalent structure or equivalent flow process conversion that utilizes instructions of the present invention and accompanying drawing content to be done; Or directly or indirectly be used in other relevant technical fields, all in like manner be included in the scope of patent protection of the present invention.
Claims (5)
1. USB clock circuit; It is characterized in that; Comprise: USB interface parallel port change-over circuit and clock generating circuit; Said USB interface parallel port change-over circuit and clock generating circuit electrically connect, and said clock generating circuit comprises oscillatory circuit, current/voltage control circuit, frequency dividing circuit and treatment circuit, and said current/voltage control circuit, oscillatory circuit and frequency dividing circuit electrically connect successively; Said treatment circuit is connected between frequency dividing circuit and the current/voltage control circuit, is connected with correcting circuit on the said oscillatory circuit.
2. USB clock circuit according to claim 1; It is characterized in that; Said current/voltage control circuit comprises frequency discrimination phase discriminator, charge pump circuit, voltage offset electric circuit and current biasing circuit; Said frequency discrimination phase discriminator and charge pump circuit electrically connect, and said voltage offset electric circuit and current biasing circuit are connected between charge pump circuit and the oscillatory circuit.
3. USB clock circuit according to claim 1 is characterized in that said treatment circuit comprises the DSP embedded processor.
4. USB clock circuit according to claim 1 is characterized in that said oscillatory circuit comprises voltage controlled oscillator.
5. USB clock circuit according to claim 1 is characterized in that, said frequency dividing circuit comprises 8 frequency dividers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012101614798A CN102722218A (en) | 2012-05-23 | 2012-05-23 | Universal serial bus (USB) clock circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012101614798A CN102722218A (en) | 2012-05-23 | 2012-05-23 | Universal serial bus (USB) clock circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102722218A true CN102722218A (en) | 2012-10-10 |
Family
ID=46948018
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012101614798A Pending CN102722218A (en) | 2012-05-23 | 2012-05-23 | Universal serial bus (USB) clock circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102722218A (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050057317A1 (en) * | 2003-09-17 | 2005-03-17 | Yong-Sup Kim | High speed voltage controlled oscillator and method thereof |
| CN1677309A (en) * | 2004-03-29 | 2005-10-05 | 三星电子株式会社 | Clock signal generator circuit for serial bus communication |
| CN1770634A (en) * | 2004-10-26 | 2006-05-10 | 大唐移动通信设备有限公司 | Clock phase-locked loop apparatus |
| JP2007081935A (en) * | 2005-09-15 | 2007-03-29 | Fujitsu Ltd | Clock generation circuit and method |
| CN1940808A (en) * | 2005-09-30 | 2007-04-04 | 恩益禧电子股份有限公司 | Compensated-clock generating circuit and usb device having same |
| CN101588178A (en) * | 2008-05-23 | 2009-11-25 | 中芯国际集成电路制造(上海)有限公司 | Self-biased phase-locked loop |
| CN201853230U (en) * | 2010-11-23 | 2011-06-01 | 东莞市创丰科技发展有限公司 | USB (Universal Serial Bus) to IO (Input Output) module |
| CN102136840A (en) * | 2011-04-22 | 2011-07-27 | 上海宏力半导体制造有限公司 | Automatic biasing phase-locked loop |
| CN202650540U (en) * | 2012-05-23 | 2013-01-02 | 常州芯奇微电子科技有限公司 | USB (Universal Serial Bus) clock circuit |
-
2012
- 2012-05-23 CN CN2012101614798A patent/CN102722218A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050057317A1 (en) * | 2003-09-17 | 2005-03-17 | Yong-Sup Kim | High speed voltage controlled oscillator and method thereof |
| CN1677309A (en) * | 2004-03-29 | 2005-10-05 | 三星电子株式会社 | Clock signal generator circuit for serial bus communication |
| CN1770634A (en) * | 2004-10-26 | 2006-05-10 | 大唐移动通信设备有限公司 | Clock phase-locked loop apparatus |
| JP2007081935A (en) * | 2005-09-15 | 2007-03-29 | Fujitsu Ltd | Clock generation circuit and method |
| CN1940808A (en) * | 2005-09-30 | 2007-04-04 | 恩益禧电子股份有限公司 | Compensated-clock generating circuit and usb device having same |
| CN101588178A (en) * | 2008-05-23 | 2009-11-25 | 中芯国际集成电路制造(上海)有限公司 | Self-biased phase-locked loop |
| CN201853230U (en) * | 2010-11-23 | 2011-06-01 | 东莞市创丰科技发展有限公司 | USB (Universal Serial Bus) to IO (Input Output) module |
| CN102136840A (en) * | 2011-04-22 | 2011-07-27 | 上海宏力半导体制造有限公司 | Automatic biasing phase-locked loop |
| CN202650540U (en) * | 2012-05-23 | 2013-01-02 | 常州芯奇微电子科技有限公司 | USB (Universal Serial Bus) clock circuit |
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| PB01 | Publication | ||
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| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20121010 |