CN202650540U - USB (Universal Serial Bus) clock circuit - Google Patents
USB (Universal Serial Bus) clock circuit Download PDFInfo
- Publication number
- CN202650540U CN202650540U CN 201220233383 CN201220233383U CN202650540U CN 202650540 U CN202650540 U CN 202650540U CN 201220233383 CN201220233383 CN 201220233383 CN 201220233383 U CN201220233383 U CN 201220233383U CN 202650540 U CN202650540 U CN 202650540U
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- voltage control
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Abstract
The utility model discloses a USB (Universal Serial Bus) clock circuit. The clock circuit comprises a USB interface parallel port switching circuit and a clock generating circuit which are electrically connected, wherein the clock generating circuit comprises an oscillating circuit, a current and voltage control circuit, a frequency dividing circuit and a processing circuit; the current and voltage control circuit, the oscillating circuit and the frequency dividing circuit are sequentially connected in sequence; the processing circuit is connected between the frequency dividing circuit and the current and voltage control circuit; and the oscillating circuit is connected with a correcting circuit. With the adoption of the USB (Universal Serial Bus) clock circuit disclosed by the utility model, transmission rate can be improved; and the clock circuit is small in the amount of codes and simple and novel in structure.
Description
Technical field
The utility model relates to electronic circuit field, particularly relates to a kind of USB clock circuit.
Background technology
Along with the miniaturization of the manufacturing process of SIC (semiconductor integrated circuit), the number of transistors that can install simultaneously sharply increases.Thus, can reduce number of spare parts by the multifunction of circuit, realize the decline of cost.Man-hour existing design circuit to be installed again in order to reduce design.Also to install and to meet the circuit that unified specification moves with characteristic frequency.And then, from by move to reduce the purposes such as power consumption with lower low speed, must realize being equipped with the SIC (semiconductor integrated circuit) of the circuit that moves with various frequencies.USB (Universial Serial Bus) is a kind of USB (universal serial bus), because it has the support hot plug, data transmission is quick, reliably, the cost performance advantages of higher, USB has become one of PC peripheral hardware expansion interface that is most widely used gradually, thereby it is the ideal interface that realizes carrying out between electronic system and the PC data transmission, data transmission between electronic system and the PC also so that the software package of electronic system after can will upgrading easily by PC download to realize in the electronic system system upgrading, can also make simultaneously the terminal user of product from the configurable functionality software package that manufacturer provides, select suitable software package to download to the personalization that realizes product in the product, hommization according to the needs of oneself.The problems such as and existing usb circuit exists the high-speed transfer pattern of much not supporting, transfer rate is little, and it is limited in one's ability that the microcontroller of USB interface performs mathematical calculations, signal is processed.
The utility model content
The technical matters that the utility model mainly solves provides a kind of USB clock circuit, can improve transfer rate, and size of code is little, and is simple in structure, novel.
For solving the problems of the technologies described above, the technical scheme that the utility model adopts is: a kind of USB clock circuit is provided, comprise: USB interface parallel port change-over circuit and clock generating circuit, described USB interface parallel port change-over circuit and clock generating circuit are electrically connected, described clock generating circuit comprises oscillatory circuit, the current/voltage control circuit, frequency dividing circuit and treatment circuit, described current/voltage control circuit, oscillatory circuit and frequency dividing circuit are electrically connected successively, described treatment circuit is connected between frequency dividing circuit and the current/voltage control circuit, is connected with correcting circuit on the described oscillatory circuit.
In preferred embodiment of the utility model, described current/voltage control circuit comprises frequency and phase discrimination circuit, charge pump circuit, voltage offset electric circuit and current biasing circuit, described frequency and phase discrimination circuit and charge pump circuit are electrically connected, and described voltage offset electric circuit and current biasing circuit are connected between charge pump circuit and the oscillatory circuit.
In preferred embodiment of the utility model, described treatment circuit comprises the DSP embedded processor.
In preferred embodiment of the utility model, described oscillatory circuit comprises voltage controlled oscillator.
In preferred embodiment of the utility model, described frequency dividing circuit comprises 8 frequency dividers.
The beneficial effects of the utility model are: the utility model USB clock circuit can improve transfer rate, and size of code is little, and is simple in structure, novel.
Description of drawings
Fig. 1 is the structural representation of the utility model USB clock circuit one preferred embodiment;
The mark of each parts is as follows in the accompanying drawing: 1, USB interface parallel port change-over circuit, 2, clock generating circuit, 3, oscillatory circuit, 4, the current/voltage control circuit, 5, frequency dividing circuit, 6, treatment circuit, 7, correcting circuit, 8, the frequency and phase discrimination circuit, 9, charge pump circuit, 10, voltage offset electric circuit, 11, current biasing circuit.
Embodiment
Below in conjunction with accompanying drawing preferred embodiment of the present utility model is described in detail, thereby so that advantage of the present utility model and feature can be easier to be it will be appreciated by those skilled in the art that protection domain of the present utility model is made more explicit defining.
See also Fig. 1, a kind of USB clock circuit, comprise: USB interface parallel port change-over circuit 1 and clock generating circuit 2, described USB interface parallel port change-over circuit 1 and clock generating circuit 2 are electrically connected, described clock generating circuit 1 comprises oscillatory circuit 3, current/voltage control circuit 4, frequency dividing circuit 5 and treatment circuit 6, described current/voltage control circuit 4, oscillatory circuit 3 are electrically connected successively with frequency dividing circuit 5, described treatment circuit 6 is connected to frequency dividing circuit 5 and current/voltage is controlled between 4 circuit, is connected with correcting circuit 7 on the described oscillatory circuit 3.
In addition, described current/voltage control circuit 4 comprises frequency and phase discrimination circuit 8, charge pump circuit 9, voltage offset electric circuit 10 and current biasing circuit 11, described frequency and phase discrimination circuit 8 is electrically connected with charge pump circuit 9, described voltage offset electric circuit 10 and current biasing circuit 11 are connected between charge pump circuit 9 and the oscillatory circuit 3, this circuit is converted to two-way current/voltage biasing charging and discharging circuit with the reference offset current replication, so that charging and discharging currents mates fully.
In addition, described treatment circuit 6 comprises the DSP embedded processor.
In addition, described oscillatory circuit 3 comprises voltage controlled oscillator.
In addition, described frequency dividing circuit 5 comprises 8 frequency dividers.
Be different from prior art, the utility model USB clock circuit can improve transfer rate, and size of code is little, and is simple in structure, novel.
The above only is embodiment of the present utility model; be not so limit claim of the present utility model; every equivalent structure or equivalent flow process conversion that utilizes the utility model instructions and accompanying drawing content to do; or directly or indirectly be used in other relevant technical fields, all in like manner be included in the scope of patent protection of the present utility model.
Claims (5)
1. USB clock circuit, it is characterized in that, comprise: USB interface parallel port change-over circuit and clock generating circuit, described USB interface parallel port change-over circuit and clock generating circuit are electrically connected, described clock generating circuit comprises oscillatory circuit, current/voltage control circuit, frequency dividing circuit and treatment circuit, described current/voltage control circuit, oscillatory circuit and frequency dividing circuit are electrically connected successively, described treatment circuit is connected between frequency dividing circuit and the current/voltage control circuit, is connected with correcting circuit on the described oscillatory circuit.
2. USB clock circuit according to claim 1, it is characterized in that, described current/voltage control circuit comprises frequency and phase discrimination circuit, charge pump circuit, voltage offset electric circuit and current biasing circuit, described frequency and phase discrimination circuit and charge pump circuit are electrically connected, and described voltage offset electric circuit and current biasing circuit are connected between charge pump circuit and the oscillatory circuit.
3. USB clock circuit according to claim 1 is characterized in that, described treatment circuit comprises the DSP embedded processor.
4. USB clock circuit according to claim 1 is characterized in that, described oscillatory circuit comprises voltage controlled oscillator.
5. USB clock circuit according to claim 1 is characterized in that, described frequency dividing circuit comprises 8 frequency dividers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220233383 CN202650540U (en) | 2012-05-23 | 2012-05-23 | USB (Universal Serial Bus) clock circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220233383 CN202650540U (en) | 2012-05-23 | 2012-05-23 | USB (Universal Serial Bus) clock circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202650540U true CN202650540U (en) | 2013-01-02 |
Family
ID=47419608
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220233383 Expired - Fee Related CN202650540U (en) | 2012-05-23 | 2012-05-23 | USB (Universal Serial Bus) clock circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202650540U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102722218A (en) * | 2012-05-23 | 2012-10-10 | 常州芯奇微电子科技有限公司 | Universal serial bus (USB) clock circuit |
-
2012
- 2012-05-23 CN CN 201220233383 patent/CN202650540U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102722218A (en) * | 2012-05-23 | 2012-10-10 | 常州芯奇微电子科技有限公司 | Universal serial bus (USB) clock circuit |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130102 Termination date: 20140523 |