CN203800047U - Distribution structure enabling addition of capacitors in chip - Google Patents
Distribution structure enabling addition of capacitors in chip Download PDFInfo
- Publication number
- CN203800047U CN203800047U CN201420149627.9U CN201420149627U CN203800047U CN 203800047 U CN203800047 U CN 203800047U CN 201420149627 U CN201420149627 U CN 201420149627U CN 203800047 U CN203800047 U CN 203800047U
- Authority
- CN
- China
- Prior art keywords
- electric capacity
- circuit
- chip
- speed
- capacitors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn - After Issue
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
The utility model relates to a distribution structure enabling addition of capacitors in a chip. A plurality of capacitors are distributed in vacant positions between each circuit modules of the chip; the circuit modules are differently defined as high-speed circuits and low-speed circuits according to working frequency, and are differently defined as high-power consumption circuits and low-power consumption circuits according to working power consumption; the plurality of capacitors are differently defined as high-speed capacitors and low-speed capacitor according to reaction speed, and are differently defined as capacitors with larger unit capacitance values and capacitors with smaller unit capacitance values according to unit area capacitance values; the high-speed capacitors are adjacent to the peripheries of the high-speed circuits; the capacitors with larger unit capacitance values are adjacent to the peripheries of the high-power consumption circuits; and the rest of capacitors are arranged at remaining vacant positions of the chip. With the distribution structure enabling addition of capacitors in the chip of the utility model adopted, the stability of the chip can be improved, and abnormal working of the high-speed circuits which is caused by the fluctuation of a power source can be avoided, and the stability of a working power source can be improved, and the fluctuation of the power source can be reduced.
Description
Technical field
The utility model relates to the distributed architecture that adds electric capacity in a kind of chip.
Background technology
As shown in Figure 1, the module containing CAP character in figure represents electric capacity, represents circuit containing the module of Circuit character.In the design of chip and producing, according to circumstances conventionally can insert electric capacity in the space between circuit, mainly use as filter capacitor to various different electrical power in chip circuit.Ordinary circumstance, a termination power of electric capacity, other end ground connection.
Because the type difference of electric capacity, its minimum dimension can be had any different.We find, on current chip, add filter capacitor mostly just between the space of circuit according to the size in space, the ground of not making any distinction between arbitrarily adds electric capacity, and the type of electric capacity and circuit is not distinguished and treated.Have thus following shortcoming: some high speed circuit in chip or high power consumption circuit are very high to the stability requirement of power supply, the fluctuation that power supply is very little all can affect the normal work of these circuit; If what add on high speed circuit side is the very slow electric capacity of speed, in the time that power supply is received interference, can not filter the interference that power supply is subject to because electric capacity can not react in time, and cause these high speed circuit job insecurities, even make mistakes.When the other capacitor's capacity of placing of high power digital circuit module is inadequate, have very large power-supply fluctuation.
Utility model content
In order to solve problems such as adding the power-supply fluctuation that electric capacity causes is large, high speed circuit job insecurity in traditional scheme chip, the utility model proposes the distributed architecture that adds electric capacity in a kind of new chip.
Basic scheme thinking of the present utility model is: by the differentiation of classifying of the circuit module in chip, be mainly to classify according to the operating frequency of circuit module and power consumption; The electric capacity that then will add is by the differentiation of classifying of capacitance, the reaction speed etc. of unit are; Finally, determine the matching relationship of electric capacity and circuit module, electric capacity is placed on around corresponding circuit module.
This method of adding electric capacity in chip, specifically comprises the following steps:
(1) according to operating frequency (speed) and power consumption to the differentiation of classifying of the circuit module in chip
1.1) divide circuit according to operating frequency
The circuit that in chip, operating frequency is relatively high is defined as high speed circuit, and the relatively low circuit of operating frequency is defined as low-speed circuits;
1.2) divide circuit according to work power consumption
The circuit that the power consumption of working in chip is relatively high is defined as high power digital circuit, and the relatively low circuit of work power consumption is defined as low consumption circuit;
(2) according to the capacitance of reaction speed, unit are to the electric capacity that will the add differentiation of classifying
2.1) divide electric capacity according to reaction speed
In available electric capacity, the comparatively faster electric capacity of reaction speed is defined as high speed electric capacity, and the relatively slow electric capacity of reaction speed is defined as low speed electric capacity;
2.2) divide electric capacity according to unit-area capacitance value
In available electric capacity, the relatively little electric capacity of electric capacity, unit capacitance that the unit's of marking off capacitance is relatively large;
(3) sorted electric capacity is joined in circuit
3.1) High-speed Electric is held and is placed on next-door neighbour's high speed circuit around;
3.2) electric capacity relatively large unit capacitance is placed on to the high power digital circuit of next-door neighbour around;
If certain circuit both as high speed circuit also as high power digital circuit, but do not have concurrently at a high speed and the relatively large electric capacity of unit capacitance, pay the utmost attention to and meet high speed circuit, employing high speed electric capacity;
3.3) other electric capacity is placed on to remaining vacant locations on chip;
(4) electric capacity placing is connected respectively to the power and ground of corresponding module.
The distributed architecture of the interpolation electric capacity that employing said method obtains, the vacant locations on chip between each circuit module distributes and is provided with several electric capacity; Its special character is: these circuit modules are distinguished and are defined as high speed circuit and low-speed circuits according to operating frequency, distinguishes and is defined as high power digital circuit and low consumption circuit according to work power consumption; Several electric capacity are distinguished and are defined as high speed electric capacity and low speed electric capacity according to reaction speed, distinguish relatively large electric capacity and the relatively little electric capacity of unit capacitance of the unit's of being defined as capacitance according to unit-area capacitance value; Described High-speed Electric appearance is placed on next-door neighbour's high speed circuit around, and the relatively large electric capacity of unit capacitance is placed on the high power digital circuit of next-door neighbour around, and other electric capacity is placed on remaining vacant locations on chip.
For example, for certain class chip (dram chip), above-mentioned high speed circuit can be thought delay locked-loop circuit and/or clock tree circuit, and described high power digital circuit can be thought I/O circuit.
For example, for certain class chip (dram chip), above-mentioned high speed electric capacity can be thought N trap NMOS pipe electric capacity, and the relatively large electric capacity of described unit capacitance can be thought stack capacitor and/or channel capacitor.
Advantage of the present utility model:
The utility model provides the distributed architecture with the visibly different interpolation electric capacity of traditional scheme, and the peripheral capacitance profile of especially high power digital circuit has embodied the distinguishing feature of chip components and parts distributed architectures intuitively.
Adopt scheme of the present utility model, can improve the stability of chip, avoid high speed circuit because the fluctuation of power supply causes circuit working undesired; Can improve the stability of working power, reduce the fluctuation of power supply; And more effectively and targetedly add electric capacity.
Brief description of the drawings
Fig. 1 is the schematic diagram of traditional scheme.
Fig. 2 is an embodiment schematic diagram of the present utility model.
Embodiment
Below with reference to Fig. 2, the utility model is further elaborated.In chip, add the method for electric capacity, specifically can carry out according to following steps:
1. the differentiation of the circuit module in chip being classified, classifies according to the operating frequency of circuit module (speed) and power consumption
1.1 divide circuit according to operating frequency
For example DLL(Delay Lock Loop) delay locked-loop circuit, CLK Tree(Clock Tree) clock tree circuit (also can be understood as clock driver circuit or clock treatment circuit), can be defined as high speed circuit;
The relatively low circuit of other operating frequency is defined as low-speed circuits;
1.2 divide circuit according to work power consumption
For example I/O(Input/output) circuit (imput output circuit) can be defined as high power digital circuit conventionally;
Here for example OCD(Off Chip Driver of I/O circuit concrete form) circuit (output driving circuit on sheet) and RCV(Receiver) circuit (receiving circuit);
The relatively low circuit of other work power consumption is defined as low consumption circuit;
2. the electric capacity that will add is distinguished by the classification such as capacitance, reaction speed of unit are
2.1 divide electric capacity according to operating rate
The fast electric capacity of reaction speed is defined as high speed electric capacity, for example Ncapnwell metal-oxide-semiconductor electric capacity (the effective electric capacity of doing of N trap NMOS), because the NMOS pipe in N trap is operated in accumulation area, its reaction speed is very fast;
The relatively slow electric capacity of other reaction speed is defined as low speed electric capacity;
2.2 divide electric capacity according to unit-area capacitance value
For example SC Cap(Stack capacitance) (stack capacitor), Trench Cap(channel capacitor), can be considered as the electric capacity that unit-area capacitance value is large;
The electric capacity that other unit capacitance is general;
3. sorted electric capacity is joined in circuit
3.1 hold that High-speed Electric be placed on next-door neighbour's high speed circuit around;
3.2 are placed on the high power digital circuit of next-door neighbour around by electric capacity large unit-area capacitance value;
If certain circuit both as high speed circuit also as high power digital circuit, but do not have concurrently at a high speed and the large electric capacity of unit-area capacitance value, pay the utmost attention to and meet high speed circuit, employing high speed electric capacity;
Other electric capacity is placed on remaining vacant locations by 3.3;
4. the electric capacity placing is connected respectively to the power and ground of corresponding module.
In Fig. 2, shown the placement relation of simple high speed, low-speed circuits electric capacity, in like manner, the circuit capacitance of high low-power consumption and height unit are capacitance is placed relation to similar shown in Fig. 2.
The electric capacity that above-described high speed, high power digital circuit and reaction speed are fast, unit-area capacitance value is large is relative concept.Be not limited in the particular type of mentioning in above-described embodiment.
For example, in the design of some chip, do not have the circuit of this several types that above embodiment mentions, for example only have decoding circuit and frequency dividing circuit, the relatively high circuit of operating frequency in chip can be defined as to high speed circuit so, the relatively high circuit of power consumption in chip is defined as to high power digital circuit.
In the manufacturing process of some chip, available electric capacity only has metal-oxide-semiconductor and metal capacitance, because reaction speed and the unit capacitance of metal-oxide-semiconductor are all better than metal capacitance conventionally, therefore, thick grid metal-oxide-semiconductor or thin grid metal-oxide-semiconductor all can be defined as to high speed electric capacity, metal-oxide-semiconductor is also defined as the electric capacity that unit-area capacitance value is large simultaneously.
Claims (3)
1. in chip, add a distributed architecture for electric capacity, the vacant locations on chip between each circuit module distributes and is provided with several electric capacity; It is characterized in that: these circuit modules are distinguished and are defined as high speed circuit and low-speed circuits according to operating frequency, distinguish and be defined as high power digital circuit and low consumption circuit according to work power consumption; Several electric capacity are distinguished and are defined as high speed electric capacity and low speed electric capacity according to reaction speed, distinguish relatively large electric capacity and the relatively little electric capacity of unit capacitance of the unit's of being defined as capacitance according to unit-area capacitance value; Described High-speed Electric appearance is placed on next-door neighbour's high speed circuit around, and the relatively large electric capacity of unit capacitance is placed on the high power digital circuit of next-door neighbour around, and other electric capacity is placed on remaining vacant locations on chip.
2. the distributed architecture that adds electric capacity in chip according to claim 1, is characterized in that: described high speed circuit is delay locked-loop circuit and/or clock tree circuit, and described high power digital circuit is I/O circuit.
3. the distributed architecture that adds electric capacity in chip according to claim 1, is characterized in that: described high speed electric capacity is N trap NMOS pipe electric capacity, and the relatively large electric capacity of described unit capacitance is stack capacitor and/or channel capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420149627.9U CN203800047U (en) | 2014-03-28 | 2014-03-28 | Distribution structure enabling addition of capacitors in chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420149627.9U CN203800047U (en) | 2014-03-28 | 2014-03-28 | Distribution structure enabling addition of capacitors in chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203800047U true CN203800047U (en) | 2014-08-27 |
Family
ID=51382241
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420149627.9U Withdrawn - After Issue CN203800047U (en) | 2014-03-28 | 2014-03-28 | Distribution structure enabling addition of capacitors in chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203800047U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103915383A (en) * | 2014-03-28 | 2014-07-09 | 西安华芯半导体有限公司 | Method for adding capacitors in chip and distribution structure of added capacitors |
-
2014
- 2014-03-28 CN CN201420149627.9U patent/CN203800047U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103915383A (en) * | 2014-03-28 | 2014-07-09 | 西安华芯半导体有限公司 | Method for adding capacitors in chip and distribution structure of added capacitors |
| CN103915383B (en) * | 2014-03-28 | 2016-10-05 | 西安紫光国芯半导体有限公司 | A kind of method adding electric capacity in the chips and the distributed architecture of interpolation electric capacity |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107346170A (en) | A kind of FPGA Heterogeneous Computings acceleration system and method | |
| CN102404625B (en) | Set-top box and standby control method thereof | |
| CN203206212U (en) | Clock frequency division circuit, clock generation network and chip | |
| CN103838284A (en) | Parallel LDO delay starting circuit | |
| CN202889340U (en) | Low-power short-distance wireless data transmission module | |
| CN203800047U (en) | Distribution structure enabling addition of capacitors in chip | |
| CN104793723A (en) | Low-power-consumption control circuit based on level detection | |
| CN202721661U (en) | UART level switching circuit | |
| CN103915383B (en) | A kind of method adding electric capacity in the chips and the distributed architecture of interpolation electric capacity | |
| CN203027231U (en) | Circuit for avoiding simultaneous start of parallel LDOs (Low Dropout Regulators) | |
| CN205210574U (en) | Two obs core control modules based on microcontroller realizes FPGA data configuration | |
| CN204425181U (en) | A kind of multi-channel portable D.C. regulated power supply | |
| CN105516477A (en) | Power saving method based on application frequency | |
| CN103870865A (en) | Radio frequency circuit used for non-contact IC card | |
| CN203574843U (en) | Energy-saving digital microphone system | |
| CN104375619A (en) | Low-power-consumption design method for single chip microcomputer systems | |
| CN105046178A (en) | High-speed card reader realization method through frequency reduction of STM32 | |
| CN202049512U (en) | Electronic authentication main control chip | |
| CN204858971U (en) | Built -in ADC control unit's control integrated circuit that steps up in step | |
| CN110120805A (en) | Logic function block, logic circuit, integrated circuit and electronic device | |
| CN203015131U (en) | Two-stage wireless network platform | |
| CN209028796U (en) | Wireless data acquisition equipment | |
| CN105045338A (en) | Multiple-peripheral-equipment and low-energy-consumption computer architecture and control method | |
| CN202798647U (en) | Receiving circuit for high-speed input and output interface | |
| CN202472509U (en) | Embedded type main board based on AT91SAM9263 processor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20140827 Effective date of abandoning: 20161005 |
|
| C25 | Abandonment of patent right or utility model to avoid double patenting |