CN202798647U - Receiving circuit for high-speed input and output interface - Google Patents
Receiving circuit for high-speed input and output interface Download PDFInfo
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- CN202798647U CN202798647U CN 201220361034 CN201220361034U CN202798647U CN 202798647 U CN202798647 U CN 202798647U CN 201220361034 CN201220361034 CN 201220361034 CN 201220361034 U CN201220361034 U CN 201220361034U CN 202798647 U CN202798647 U CN 202798647U
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- clock signal
- frequency
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- clock
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Abstract
The utility model discloses a receiving circuit for a high-speed input and output interface and the receiving circuit comprises a local-clock generating circuit, a clock recovery circuit, a data recovery circuit and a frequency-spectrum pulse-width clock-control pulse generator, wherein the local-clock generating circuit is used for generating local clock signals based on adjusting clock control pulse of frequency-spectrum pulse width, the clock recovery circuit is used for recovering to obtain recovery clock signals according to input data and the local clock signals, the data recovery circuit is used for recovering to obtain output data signals according to the input data and the recovery clock signals, and the frequency-spectrum pulse-width clock-control pulse generator determines whether the frequency difference between the local clock signals and the recovery clock signals is larger than a preset value. If the frequency difference is larger than the preset value, frequency-spectrum widening-clock control pulse is adjusted in order to change the frequencies of the local clock signals, so that the frequencies are close to the frequencies of the recovery clock signals. If the frequency difference isn't larger than the preset value, adjustment isn't performed. Because the local clock signals are changed, the frequencies of the local clock signals are close to the frequencies of the recovery clock signals. The performance of a data recovery circuit of the receiving circuit is improved and increased energy consumption is reduced.
Description
Technical field
The utility model relates to the high-speed interface field, relates in particular to the receiving circuit of a kind of high speed input/output interface (I/O).
Background technology
At present, require super speed signal (5Gbps) must support video stretching (Spread Spectrum Communication is called for short SSC) function in the USB3.0 standard, to reach the effect that reduces electromagnetic interference (EMI).This video stretching function can make the data bit-rate of transmitting-receiving periodically change, and the variation peak-to-peak value is 5000ppm.Like this, data recovery circuit is when recovering with the data of SSC frequency deviation, and data recovery circuit correctly recovers the limited in one's ability of data, sometimes needs to increase a high speed frequency discriminator.
The utility model content
For problems of the prior art, the utility model proposes a kind of receiving circuit of high speed input/output interface, it has improved the performance of the data recovery circuit of receiving circuit, and the power consumption that increases is seldom.
According to an aspect of the present utility model, the utility model proposes a kind of receiving circuit of high speed input/output interface, it comprises: local clock produces circuit, is used for producing the local clock signal based on video stretching clock control pulse; Clock recovery circuitry is used for recovering to be restored clock signal according to input data and local clock signal; Data recovery circuit is used for recovering to obtain outputting data signals according to input data and described recovered clock signal; Frequency spectrum pulsewidth clock control pulse generator, whether its difference on the frequency of determining described local clock signal and described recovered clock signal is greater than predetermined value, if, then adjust described video stretching clock control pulse to change the frequency of described local clock signal, make it near the frequency of described recovered clock signal, if not, then do not adjust.
Further, described frequency spectrum pulsewidth clock control pulse generator comprises the first accumulator, the second accumulator and comparator.In scheduled time slot, the first accumulator counts to get the first count value to the cycle of described local clock signal, and the second accumulator counts to get the second count value to the cycle of described recovered clock signal, reset afterwards the first accumulator and the second accumulator.Whether described comparator compares the difference of two count values greater than predetermined threshold, if, then described frequency spectrum pulsewidth clock control pulse generator is adjusted described video stretching clock control pulse to change the frequency of described local clock signal, make it near the frequency of described recovered clock signal, if not, then do not adjust.
Compared with prior art, frequency spectrum pulsewidth clock control pulse generator in the utility model has increased the function of frequency-tracking, and it can adjust the local clock frequency automatically, thereby improved the performance of the data recovery circuit of receiving circuit, and the power consumption that increases seldom.
Description of drawings
Fig. 1 is the receiving circuit structural representation in one embodiment of the high speed input/output interface in the utility model;
Fig. 2 is the frequency spectrum pulsewidth clock control pulse generator structural representation in one embodiment among Fig. 1;
Fig. 3 is the sampling eye schematic diagram of data recovery circuit of the prior art; With
Fig. 4 is the sampling eye schematic diagram of the data recovery circuit among Fig. 1.
Embodiment
Below in conjunction with accompanying drawing the utility model is elaborated.
Fig. 1 is the topology example figure of the receiving circuit 100 of the high speed input/output interface in the utility model.As shown in Figure 1, the receiving circuit of described high speed input/output interface, it comprises that data recovery circuit 110, clock recovery circuitry 120, local clock produce circuit 130 and frequency spectrum pulsewidth clock control pulse generator 140.
Described local clock produces circuit 130 and is used for producing local clock signal CLK_loc based on the video stretching clock control pulse SSC_cont that frequency spectrum pulsewidth clock control pulse generator 140 produces.
Frequency spectrum pulsewidth clock control pulse generator 140 determines that whether the difference on the frequency of described local clock signal CLK_loc and described recovered clock signal CLK_rec is greater than predetermined value, if, then adjust described video stretching clock control pulse SSC_cont to change the frequency of described local clock signal CLK_loc, make it near the frequency of described recovered clock signal CLK_rec, to reduce the difference on the frequency of local clock signal CLK_loc and described recovered clock signal CLK_rec, if not, then do not adjust.
Described video stretching clock control pulse SSC_cont can control the frequency dividing ratio in the described local clock generation circuit 130, and then can adjust described local clock signal CLK_loc.
Fig. 2 is frequency spectrum pulsewidth clock control pulse generator 140 structural representation in one embodiment among Fig. 1.Described frequency spectrum pulsewidth clock control pulse generator 140 comprises the first accumulator 141, the second accumulator 142 and comparator 143.
Within one period predetermined period, the cycle of 141 couples of described local clock signal CLK_loc of the first accumulator counts to get the first count value, the second accumulator counts to get the second count value to the cycle of described recovered clock signal CLK_rec, reset afterwards the first accumulator 141 and the second accumulator 142.
Whether described comparator 143 compares the difference of the first count value and the second count value greater than predetermined threshold, if, then described frequency spectrum pulsewidth clock control pulse generator 140 is adjusted described video stretching clock control pulse SSC_cont to change the frequency of described local clock signal CLK_loc, make it near the frequency of described recovered clock signal CLK_rec, if not, then do not adjust.
Through constantly adjusting, finally can make being controlled in the very little scope that the frequency difference of described local clock signal CLK_loc and described recovered clock signal CLK_rec can be stable, offset the rear adverse effect to receiving circuit of spread spectrum (SSC) with this, thereby can improve the performance of described data recovery circuit 110.
Fig. 3 is the sampling eye schematic diagram of data recovery circuit of the prior art, and Fig. 4 is the sampling eye schematic diagram of the data recovery circuit among Fig. 1.Can see, the settling time of the data recovery circuit among Fig. 3, (setup time) was too short, be about 6ps, sample error occurs easily, increased the settling time of the data recovery circuit among Fig. 4 (setup time) a lot, be about 40ps, be difficult for sample error occurs, the data recovery capability improves.
In sum, in the utility model, the frequency-tracking function is integrated in video stretching clock (SSC) the control impuls generator, automatically adjust the local clock frequency, improve the performance of the data recovery circuit of receiving circuit, realize by totally digital circuit, the power consumption of increase again seldom.
Although described the utility model by embodiment, those of ordinary skills know, the utility model has many distortion and variation and does not break away from spirit of the present utility model, wishes that appended claim comprises these distortion and variation and do not break away from spirit of the present utility model.
Claims (2)
1. the receiving circuit of a high speed input/output interface is characterized in that, it comprises:
Local clock produces circuit, is used for producing the local clock signal based on video stretching clock control pulse;
Clock recovery circuitry is used for recovering to be restored clock signal according to input data and local clock signal;
Data recovery circuit is used for recovering to obtain outputting data signals according to input data and described recovered clock signal; With
Frequency spectrum pulsewidth clock control pulse generator, whether its difference on the frequency of determining described local clock signal and described recovered clock signal is greater than predetermined value, if, then adjust described video stretching clock control pulse to change the frequency of described local clock signal, make it near the frequency of described recovered clock signal, if not, then do not adjust.
2. receiving circuit according to claim 1 is characterized in that, described frequency spectrum pulsewidth clock control pulse generator comprises the first accumulator, the second accumulator and comparator,
In scheduled time slot, the first accumulator counts to get the first count value to the cycle of described local clock signal, and the second accumulator counts to get the second count value to the cycle of described recovered clock signal, reset afterwards the first accumulator and the second accumulator;
Whether described comparator compares the difference of two count values greater than predetermined threshold, if, then described frequency spectrum pulsewidth clock control pulse generator is adjusted described video stretching clock control pulse to change the frequency of described local clock signal, make it near the frequency of described recovered clock signal, if not, then do not adjust.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220361034 CN202798647U (en) | 2012-07-25 | 2012-07-25 | Receiving circuit for high-speed input and output interface |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220361034 CN202798647U (en) | 2012-07-25 | 2012-07-25 | Receiving circuit for high-speed input and output interface |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202798647U true CN202798647U (en) | 2013-03-13 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220361034 Expired - Lifetime CN202798647U (en) | 2012-07-25 | 2012-07-25 | Receiving circuit for high-speed input and output interface |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102801411A (en) * | 2012-07-25 | 2012-11-28 | 苏州亮智科技有限公司 | Receiving circuit of high-speed input and output interface |
-
2012
- 2012-07-25 CN CN 201220361034 patent/CN202798647U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102801411A (en) * | 2012-07-25 | 2012-11-28 | 苏州亮智科技有限公司 | Receiving circuit of high-speed input and output interface |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20170323 Address after: Pudong New Area Zhangjiang hi tech road 201203 Shanghai City No. 1158 Zhang No. 2 Building 7 floor Patentee after: BRITE SEMICONDUCTOR (SHANGHAI) Corp. Address before: Suzhou City, Jiangsu province 215021 international science and Technology Park No. 1355 Jinji Lake Avenue Suzhou industrial park two D102-2 Patentee before: SUZHOU LIANGZHI TECHNOLOGY Co.,Ltd. |
|
| TR01 | Transfer of patent right | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 201203 7th floor, building 2, 1158 Zhangdong Road, Zhangjiang hi tech, Pudong New Area, Shanghai Patentee after: Canxin semiconductor (Shanghai) Co.,Ltd. Address before: 201203 7th floor, building 2, 1158 Zhangdong Road, Zhangjiang hi tech, Pudong New Area, Shanghai Patentee before: BRITE SEMICONDUCTOR (SHANGHAI) Corp. |
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| CP01 | Change in the name or title of a patent holder | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130313 |
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| CX01 | Expiry of patent term |