CN102624382A - Clock synchronization method, device and radio frequency chip circuit with same device - Google Patents
Clock synchronization method, device and radio frequency chip circuit with same device Download PDFInfo
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- CN102624382A CN102624382A CN2012100900059A CN201210090005A CN102624382A CN 102624382 A CN102624382 A CN 102624382A CN 2012100900059 A CN2012100900059 A CN 2012100900059A CN 201210090005 A CN201210090005 A CN 201210090005A CN 102624382 A CN102624382 A CN 102624382A
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Abstract
The invention discloses a clock synchronization method and device, and a radio frequency chip circuit with the device. The method comprises the following steps: resetting a counter with a phase processing function when a radio frequency chip is reset and a transmission circuit does not work, and generating a synchronous clock at zero level, thereby reducing the power consumption of the radio frequency chip; while receiving an internal clock synchronous pulse by the synchronous clock, adjusting the phase of the synchronous clock according to a rising edge of an internal clock; while receiving an external clock synchronous pulse by the synchronous clock, adjusting the phase of the synchronous clock according to the rising edge of an external clock; and meanwhile, adopting a multiplexing PLL (Phase Locked Loop) circuit for causing the counter with the phase processing function to generate a phase-adjustable generated synchronous clock under the condition of receiving no internal or external clock synchronous pulse. The phase relation of the clock edge and data is ensured by the phase adjustment, so that the radio frequency chip can correctly receive to-be-transmitted data. According to the method disclosed by the invention, the purposes of low dependency, low cost and low power consumption are achieved.
Description
Technical field
The invention belongs to the digital circuit technique field, relate in particular to a kind of clock synchronizing method, install and have the radio frequency chip circuit of this device.
Background technology
Radio frequency chip is the radio transceiver chip especially, need receive and send data in the course of the work, wherein, need receive the clock and the data of baseband chip when sending data.
In the prior art, the inner work clock of radio frequency chip all utilizes the clock signal of external chip to provide.Mainly comprise dual mode: first kind of mode is for directly utilizing the internal work clock of the external clock of external chip as radio frequency chip.But adopt this kind method to have following shortcoming, one of which, when external clock different with data in the time-delay of interface, can't be synchronous, then can destroy the phase relation of clock edge and data, thereby cause radio frequency chip can't correctly receive data; Its two, when the external clock driving force maybe be not enough, drive buffering if increase, may destroy former clock and synchronization of data and concern, can cause radio frequency chip can't correctly receive data equally; Its three, the operating state of this external clock is in input state always, when radio frequency chip is not worked, can not shield this external clock, has increased the power consumption of radio frequency chip.
The second way is sent data for the mode that adopts FIFO (First In First Out, first in first out data buffer) to carry out data handshakes.But adopt this kind mode still to have following shortcoming, one of which, FIFO device area is bigger, and it is more to take the radio frequency chip area; Its two, this kind mode must be utilized the internal work clock of external clock as radio frequency chip equally, when the problem in above-mentioned first kind of mode appears in external clock, can't make radio frequency chip correctly receive data equally.
From the above, dual mode of the prior art all must adopt the clock signal of external chip to radio frequency chip work clock to be provided, and has generally speaking that dependence is strong, cost is high and the shortcoming of waste power consumption.Especially when external chip did not provide clock, radio frequency chip then can't operate as normal.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of clock synchronizing method, install and have the radio frequency chip circuit of this device, the dependence that exists in the prior art is strong, cost is high and the problem of waste power consumption to overcome.
A kind of method of clock synchronization comprises:
When radio frequency chip is in reset mode or corresponding module and is non operating state, make the counter O reset of band Phase Processing;
When the counter of said band Phase Processing receives the signal of startup work; The counter of said band Phase Processing carries out frequency division to the high frequency clock that the phase-locked loop pll circuit that receives generates; And the adjustment initial phase, generate first synchronised clock as required synchronised clock output;
Whether the counter of the said band Phase Processing of real-time judge receives the internal clocking lock-out pulse in the course of the work;
If the counter of said band Phase Processing is that benchmark carries out the phase place adjustment with the rising edge of internal clocking then, generates second synchronised clock and exports as required synchronised clock;
If not; Whether the counter of judging said band Phase Processing receives the external clock lock-out pulse; If the counter of said band Phase Processing then carries out the phase place adjustment according to the rising edge of detected external clock, generates the 3rd synchronizing clock signals and exports as required synchronised clock.
Preferably, the counter of said band Phase Processing is that benchmark carries out the phase place adjustment with the rising edge of internal clocking, generates second synchronised clock and comprises as the detailed process of synchronised clock output:
The counter of said band Phase Processing receives the current count value of the internal clocking of cycle counter transmission;
Deduct at the current count value of said internal clocking on the basis of required synchronous two clocks, increase phase value adjustment phase place, the rising edge that obtains with said internal clocking is second synchronised clock of benchmark adjustment; Said second synchronised clock is exported as required synchronised clock;
Wherein, said phase value can be on the occasion of or negative value, maximum is the half the of the said PLL circuit target frequency cycle when producing high frequency clock, the said target frequency cycle is the high frequency clock frequency that produces of said PLL and the ratio of target frequency.
Preferably, the counter of said band Phase Processing carries out the phase place adjustment according to the rising edge of detected external clock, generates the 3rd synchronised clock and comprises as the detailed process of required synchronised clock output:
The counter of said band Phase Processing receives the outside external clock that sends, and detects the rising edge that synchronizer detects external clock via the edge;
The target frequency cycle when obtaining said PLL circuit and producing high frequency clock;
Deduct on the numerical value basis of high frequency clock required in the synchronizing process at said target frequency cycle numerical value, increase phase value adjustment phase place, the rising edge that obtains with said external clock is the 3rd synchronised clock of benchmark adjustment;
Said the 3rd synchronised clock is exported as required synchronised clock;
Wherein, the said target frequency cycle is the frequency of the clock that produces of said PLL circuit and the ratio of target frequency; Said phase value can be on the occasion of or negative value, maximum is the half the of said target frequency cycle; The numerical value of required high frequency clock is 4 in the synchronizing process.
Preferably, it is benchmark when carrying out the phase place adjustment that the counter of said band Phase Processing need not rising edge with the rising edge of internal clocking or external clock, generates first synchronised clock and comprises as the detailed process of required synchronised clock output:
The target frequency cycle when obtaining said PLL and producing high frequency clock;
On the basis of said target frequency cycle numerical value, increase phase value adjustment phase place, obtain first synchronised clock;
Said first synchronised clock is exported as required synchronised clock.
Preferably, the high frequency clock that said PLL circuit generates, its frequency is higher than required synchronised clock N clock doubly; Wherein, N is more than or equal to 3;
Perhaps, the frequency of the high frequency clock of said PLL circuit generation is the common multiple of the frequency of required synchronised clock.
A kind of clock synchronization apparatus comprises: the counter of band Phase Processing, and the cycle counter that is connected with the counter of said band Phase Processing, and connect the counter of said band Phase Processing and the phase-locked loop pll circuit of said cycle counter;
Said PLL circuit is used to produce high frequency clock;
Said cycle counter is used for the high frequency clock that the said PLL circuit that receives produces is carried out frequency division, generates internal clocking; And the phase meter numerical value of internal clocking is provided to the counter of band Phase Processing;
The counter of said band Phase Processing is used for when radio frequency chip is in reset mode or corresponding module and is in non operating state, quitting work; When receiving the signal of startup work, the high frequency clock that the phase-locked loop pll circuit that receives is generated carries out frequency division, and initial phase is adjustable, generates first synchronised clock as required synchronised clock output; And whether real-time judge receives the internal clocking lock-out pulse in the course of the work;
If then the rising edge with internal clocking is that benchmark carries out the phase place adjustment, the rising edge that generates with said internal clocking is that second synchronised clock that benchmark is adjusted is exported as required synchronised clock;
If not; Judge whether to receive the external clock lock-out pulse again; If then the rising edge according to detected external clock carries out the phase place adjustment, the rising edge that generates with said external clock is that the 3rd synchronised clock that benchmark is adjusted is exported as required synchronised clock.
Preferably, when the counter of said band Phase Processing receives the internal clocking lock-out pulse:
The counter of said band Phase Processing; Be used to receive the current count value of the internal clocking that cycle counter sends; Current count value at said internal clocking deducts on the basis of required two clocks synchronously; Increasing phase value adjustment phase place, is that second synchronised clock that benchmark is adjusted is exported as required synchronised clock with the rising edge that obtains with said internal clocking;
Wherein, said phase value can be on the occasion of or negative value, maximum is the half the of the said PLL circuit target frequency cycle when producing high frequency clock, the said target frequency cycle is the high frequency clock frequency that produces of said PLL and the ratio of target frequency.
Preferably, when the counter of said band Phase Processing receives the external clock lock-out pulse:
The counter of said band Phase Processing, the target frequency cycle when being used to obtain said PLL circuit and producing high frequency clock; Deducting on the numerical value basis of high frequency clock required in the synchronizing process at said target frequency cycle numerical value, increase phase value adjustment phase place, is that the 3rd synchronised clock that benchmark is adjusted is exported as required synchronised clock with what obtain with said external clock rising edge;
Wherein, the rising edge information of said external clock is obtained via edge detection synchronizer; The said target frequency cycle is the frequency of the clock that produces of said PLL circuit and the ratio of target frequency; Said phase value can be on the occasion of or negative value, maximum is the half the of said target frequency cycle; The numerical value of required high frequency clock is 4 in the synchronizing process;
Perhaps, said second synchronised clock is postponed one and clap the back as required synchronised clock output.
Preferably, the high frequency clock that said PLL circuit generates, it is required synchronised clock N clock doubly for frequency is higher than; Wherein, N is more than or equal to 3;
Perhaps, the frequency of the high frequency clock of said PLL circuit generation is the common multiple of the frequency of required synchronised clock.
A kind of radio frequency chip circuit comprises: clock synchronization apparatus and edge detect synchronizer;
Said clock synchronization apparatus is above-mentioned disclosed any clock synchronization apparatus;
Said edge detects synchronizer, is used for detecting the rising edge of external clock when carrying out external clock when synchronous, and then generation external clock lock-out pulse; When carrying out internal clocking when synchronous, detect the rising edge of internal clocking, and then generate the internal clocking lock-out pulse.
Because the embodiment of the invention provides a kind of clock synchronizing method, installed and has had the radio frequency chip circuit of this device.The present invention through reset at radio frequency chip or the idle situation of corresponding module under, the counter O reset of band Phase Processing is promptly quit work, generating synchronizing clock signals is that 0 level is to reduce the power consumption of radio frequency chip; Generate synchronizing clock signals when receiving the internal clocking lock-out pulse, its phase place can be adjusted according to the internal clocking rising edge; This synchronised clock is when receiving the external clock lock-out pulse, and its phase place can be adjusted according to the external clock rising edge; Simultaneously; Under the situation that does not receive internal clocking lock-out pulse and external clock lock-out pulse; Promptly do not rely on inside, do not rely under the situation of external reference clock yet, can make the counter of band Phase Processing generate the adjustable generation synchronizing clock signals of phase place through multiplexing PLL circuit.Phase place is adjustable has guaranteed the phase relation of clock edge and data, makes the data that radio frequency chip can correctly receive needs emission, can realize the purpose of low dependence, low cost and low-power consumption through the invention described above disclosed method.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously, the accompanying drawing in describing below is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the structural representation of a kind of clock synchronization apparatus disclosed by the invention;
Fig. 2 is the structural representation that edge disclosed by the invention detects synchronizer;
Fig. 3 is the method flow diagram of a kind of clock synchronization disclosed by the invention.
Embodiment
A kind of clock synchronizing method that the embodiment of the invention provides, install and have the radio frequency chip circuit of this device; Receive the internal clocking lock-out pulse through being directed against; Perhaps to receiving the external clock lock-out pulse; Perhaps, adjust phase place as the case may be and generate required synchronised clock, can realize the purpose of low dependence, low cost and low-power consumption to not receiving under the situation of internal clocking lock-out pulse and external clock lock-out pulse.
For the purpose, technical scheme and the advantage that make the embodiment of the invention clearer; To combine the accompanying drawing in the embodiment of the invention below; Technical scheme in the embodiment of the invention is carried out clear, intactly description; Obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
Embodiment one
As shown in Figure 1, be the disclosed a kind of clock synchronization apparatus of this embodiment of the invention, mainly comprise: the counter 13 of PLL (phase-locked loop) circuit 11, cycle counter 12 and band Phase Processing.
Wherein, cycle counter 12 with the band Phase Processing counter 13 between be connected; PLL circuit 11 connects the counter 13 of cycle counter 12 and band Phase Processing simultaneously.
This PLL circuit 11 is used to produce high frequency clock H_clk.
This cycle counter 12 is used for the high frequency clock H_clk that the PLL circuit that receives produces is carried out frequency division, generates internal clocking M_clk.12 pairs of this cycle counters should internal clocking the count value counter 13 that can be used as the band Phase Processing carry out internal clocking synchronization basic standard phase place.In addition, the frequency of this internal clocking M_clk can be used as the target frequency of high frequency clock H_clk.
The counter 13 of this band Phase Processing is used for carrying out zero clearing when radio frequency chip is in when reset mode or corresponding module are in non operating state, promptly quits work.Above-mentioned corresponding module refers to the radiating circuit module generally speaking.(being the phase value of internal clocking)
When the counter 13 of this band Phase Processing receives the signal of startup work; The high frequency clock H_clk that the PLL circuit 11 that 13 pairs in the counter of this band Phase Processing receives generates carries out frequency division; Initial phase is adjustable, generates first synchronised clock as required synchronised clock L_clk output.
In the process of concrete work; Whether the counter of this band Phase Processing of real-time judge receives the internal clocking lock-out pulse; If then the rising edge with internal clocking is that benchmark carries out the phase place adjustment, generates second synchronised clock and exports as required synchronised clock L_clk.
If not, judge then whether the counter 13 of this band Phase Processing receives the external clock lock-out pulse, if then the rising edge according to detected external clock carries out the phase place adjustment, generates the 3rd synchronised clock and exports as required synchronised clock L_clk.
Need to prove, the high frequency clock H_clk that above-mentioned PLL circuit 11 generates, it is required synchronised clock L_clkN clock doubly for frequency is higher than; Wherein, N is more than or equal to 3.
Perhaps, the frequency of the high frequency clock H_clk of these PLL circuit 11 generations is the common multiple of the frequency of required synchronised clock L_clk.
One of which receives the internal clocking lock-out pulse.
This embodiment of the invention is being carried out based on disclosed clock synchronization apparatus in the process of clock synchronization; When the counter 13 of this band Phase Processing receives the internal clocking lock-out pulse; The counter 13 of this band Phase Processing is mainly used in and receives the internal clocking M_clk that cycle counter 12 sends; In fact receive for the current count value of internal clocking M_clk; It is the phase value of internal clocking; And deduct on the basis of required synchronous two clocks (these two clocks are actually the numerical value of high frequency clock required in the synchronizing process) (Mclk_cnt-2) at said internal clocking phase value Mclk_cnt, increase phase value adjustment phase place, be that second synchronised clock of reference phase adjustment is exported as required synchronised clock L_clk with what obtain with the internal clocking rising edge.
Wherein, the phase value of increase can be on the occasion of or negative value, maximum is the half the of the PLL circuit 11 target frequency cycle when producing high frequency clock H_clk, the said target frequency cycle is the high frequency clock frequency that produces of said PLL and the ratio of target frequency.For example; The clock frequency of the high frequency clock H_clk that PLL circuit 11 is produced is 491.52MHz; Target frequency is 3.84MHz; Then a target frequency has 128 pll clock cycles in the cycle, and half target frequency cycle then is 64, and the phase number maximum of required adjustment can be positive 64 or negative 64 (in the process of carrying out cycle count, utilizing highest order to represent sign).
Its two, receive the external clock lock-out pulse.
When the counter 13 of said band Phase Processing received the external clock lock-out pulse, the counter 13 of this band Phase Processing was mainly used in the target frequency cycle when obtaining PLL circuit 11 generation high frequency clock H_clk; Deduct on the numerical value basis of required high frequency clock in the synchronizing process at this target frequency cycle numerical value; Increase needs phase value (offset_delay) the adjustment phase place of adjustment, is that the 3rd synchronised clock that benchmark is adjusted is exported as required synchronised clock L_clk with what obtain with said external clock rising edge.
Wherein, the rising edge information of said external clock is obtained via edge detection synchronizer; The said target frequency cycle is the high frequency clock frequency of these PLL circuit 11 generations and the ratio of target frequency; Said phase value can be on the occasion of or negative value, maximum is the half the of said target frequency cycle; The numerical value of required high frequency clock H_clk is 4 in the synchronizing process.
Carry out the synchronous process of external clock when receiving the external clock lock-out pulse to the counter 13 of above-mentioned band Phase Processing; The clock frequency of the high frequency clock H_clk that is produced when PLL circuit 11 is 491.52MHz; Target frequency is 3.84MHz; Then a target frequency has 128 pll clock cycles (being expressed as 0～127) in the cycle; Half target frequency cycle then is 64, and the phase number maximum of required adjustment can be positive 64 or negative 64 (in the process of carrying out cycle count, utilizing highest order to represent sign).Concrete phase place is adjusted into (127-4+offset_delay).
As shown in Figure 2, the structural representation for the disclosed edge detection of embodiment of the invention synchronizer mainly comprises: the D register of three cascades (D1, D2, D3), a not gate F1 and one and a door Y1.
Concrete structure is that D1, D2, D3 carry out cascade through in-phase output end and D input successively, and the input of D1 is imported the clock G_clk of required detection, and the input end of clock of each D register is then imported H_clk respectively; The in-phase output end of D3 passes through not gate F1 and is connected with the input of door Y1; Should with another input of door Y1 then with the D register of cascade second level output be connected; Promptly be connected, at last through this output output G_clk_pos with door Y1 with the in-phase output end of D2.Wherein, when current required detection be external clock the time, G_clk is external clock F_clk, final output be the actual F_clk_pos of being of G_clk_pos; When current required detection be internal clocking the time, G_clk is internal clocking M_clk, the G_clk_pos of final output is actual to be M_clk_pos.
This edge detects synchronizer and the disclosed clock synchronization apparatus of the invention described above embodiment can be arranged in the radio frequency chip circuit simultaneously, and wherein PLL circuit in the clock synchronization apparatus and cycle counter adopt multiplexing mode to use.
Carry out external clock when receiving the external clock lock-out pulse when synchronous at the counter 13 of band Phase Processing, for example, the high-frequency clock H_clk that PLL circuit 11 generates, its frequency is required synchronised clock L_clk*N, wherein N is greater than 3.When the frequency of the high-frequency clock H_clk that adopts was 491.52MHz, at this moment, optional synchronised clock L_clk was the requirement of satisfying LTE, is chosen as 61.44MHz, 46.08MHz, 23.04MHz, 30.72MHz, 3.84MHz etc.
Can know that from Fig. 2 synchronous needed H_clk is 3 clocks.The generation of synchronised clock L_clk has used d type flip flop to postpone a bat in the practical application, so total synchronised clock is 4 H_clk clocks.In the time of synchronously, target frequency cycle numerical value is deducted the numerical value of the high frequency clock in the synchronizing process, and then add the numerical value (offset_delay) that needs the adjustment phase place, thereby obtain the initial phase of required synchronised clock L_clk.
According to the synchronised clock L_clk that the result of the counter of band Phase Processing generates, this synchronised clock can directly generate or with one bat of D register delay.
Its three, do not receive internal clocking lock-out pulse and external clock lock-out pulse.
Need to prove that above-mentioned edge detects synchronizer carrying out external clock when synchronous, detects the rising edge of external clock, and then generates the external clock lock-out pulse; Carry out internal clocking when synchronous, detecting the rising edge of internal clocking, and then generating the internal clocking lock-out pulse.
Disclosed clock synchronization apparatus of the invention described above embodiment and radio frequency chip circuit reset and/or corresponding module is under the situation of inoperative at radio frequency chip, and the counter O reset of band Phase Processing promptly quits work, to reduce the power consumption of radio frequency chip; Under the situation that receives internal clocking lock-out pulse or external clock lock-out pulse; Rising edge with inside or external clock is a benchmark adjustment phase place as the case may be; Generate required synchronised clock; To obtain the correct clock edge and the phase relation of data, make radio frequency chip can correctly receive data.
Simultaneously; Under the situation that does not receive internal clocking lock-out pulse and external clock lock-out pulse; Promptly do not rely under the situation of inside and outside reference clock; Make the counter of band Phase Processing generate required synchronised clock through multiplexing PLL circuit, thereby realize the purpose of low dependence, low cost and low-power consumption.
Embodiment two
On the basis of disclosed clock synchronization apparatus of the invention described above embodiment and radio frequency chip circuit, as shown in Figure 3, the also corresponding method that discloses a kind of clock synchronization of the embodiment of the invention mainly may further comprise the steps:
Step S101 powers on, and judges whether current radio frequency chip is in reset mode, if then make the counter O reset of band Phase Processing; If deny, then execution in step S102.
Step S102 judges whether corresponding module is in non operating state, if then make the counter O reset of band Phase Processing; If deny, then execution in step S103.Wherein, corresponding module generally is meant the transmitter module in the radio frequency chip.
Step S103; Judge whether the counter of said band Phase Processing receives the pulse signal of startup work, if the counter of said band Phase Processing carries out frequency division to the high frequency clock that the phase-locked loop pll circuit that receives generates; Adjust initial phase simultaneously; Generate first synchronised clock as the output of required synchronised clock, wherein, carry out the initial phase adjustment excessively in; The phase value tx_cnt assignment that need is generated clock L_clk is phase adjustment value offset1, and offset1 carries out the adjustment of initial phase according to this phase adjustment value.If, then do not carry out S104.
Step S104 judges whether the counter of said band Phase Processing receives the internal clocking lock-out pulse; If; The counter of then said band Phase Processing is that benchmark carries out the phase place adjustment with the rising edge of internal clocking then; Generating second synchronised clock exports as required synchronised clock; Wherein, the process of carrying out phase place adjustment does, the phase value tx_cnt assignment that need are generated clock L_clk is that the phase value mclk_cnt of internal clocking deducts required two synchronous H_clk clocks and adds phase adjustment value offset_2; If deny, then execution in step S105.
Step S105; Whether the counter of judging said band Phase Processing receives the external clock lock-out pulse, if the counter of then said band Phase Processing then carries out the phase place adjustment according to the rising edge of detected external clock; Generating the 3rd synchronised clock exports as required synchronised clock; The process of wherein, carrying out phase place adjustment is that the phase value tx_cnt assignment that need is generated clock L_clk is 127-4+offset_delay; If deny, then execution in step S106.
Step S106, the counter of said band Phase Processing carries out cycle count.Be specially: the rising edge of the high frequency clock H_clk that generates with the PLL circuit that receives is that benchmark subtracts 1 computing to tx_cnt.The result of tx_cnt is used to generate required synchronised clock L_clk.
In the disclosed step S101 of the invention described above embodiment～step S106, the clock frequency of high-frequency clock H_clk is N a times of synchronised clock L_clk, and this N is more than or equal to 3; Perhaps, the clock frequency of high-frequency clock H_clk is the common multiple of the synchronised clock L_clk of generation.
Need to prove that the detailed process of above-mentioned steps S104 comprises:
At first, the counter of said band Phase Processing receives the phase value of the internal work benchmark M_clk clock that cycle counter sends.
Be specially: cycle counter receives the high frequency clock signal H_clk that the PLL circuit sends, and it is carried out frequency division, generates internal clocking M_clk; With the phase value of its count value mclk_cnt as internal clocking M_clk.
Secondly, on the basis that deducts two required H_clk clocks of synchronous rising edge on the phase value basis of said internal clocking M_clk (mclk_cnt-2), increase phase value adjustment phase place, obtain the initial phase of required synchronised clock;
Second synchronised clock that at last, will carry out the adjusted generation of initial phase is exported as required synchronizing clock signals L_clk.
Wherein, said phase value can be on the occasion of or negative value, maximum is the half the of the said PLL circuit target frequency cycle when producing high frequency clock signal H_clk, the said target frequency cycle is the high frequency clock frequency that produces of said PLL and the ratio of target frequency.
The detailed process of above-mentioned steps S105 is:
At first, the counter of said band Phase Processing receives the outside external clock F_clk that sends, and detects the rising edge that synchronizer detects said external clock F_clk via the edge.
The target frequency cycle when secondly, obtaining said PLL circuit and produce high frequency clock signal H_clk.
Secondly, deduct on the basis of numerical value of high frequency clock H_clk required in the synchronizing process at said target frequency cycle numerical value, increase phase value adjustment phase place, obtaining with said external clock F_clk rising edge is the initial phase of the required synchronised clock of benchmark.
The 3rd synchronised clock that at last, will carry out initial phase adjustment back generation is exported as required synchronised clock L_clk.
Wherein, the said target frequency cycle is the frequency of the high frequency clock H_clk that produces of said PLL circuit and the ratio of target frequency; Said phase value can be on the occasion of or negative value, maximum is the half the of said target frequency cycle; The numerical value of required high frequency clock is 4 in the synchronizing process.
Among the step S106, can also comprise: the synchronised clock that said tx_cnt is generated postpones a bat back as required synchronised clock L_clk output.
Describe for example to said process, when the frequency of high-frequency clock H_clk is 491.52MHz, target frequency is 3.84MHz.The target frequency cycle is that 128 (be expressed as: 0～127), half target frequency cycle is 64.The phase value maximum adjustable is whole for+64 or-64.The frequency of optional synchronizing clock signals L_clk is 61.44MHz, 46.08MHz, 23.04MHz, 30.72MHz and 3.84MHz.Corresponding N value is respectively 8,12,6,16 and 128.
On the basis of the disclosed clock synchronizing method of the invention described above embodiment, the verilog descriptive statement of the counter phase adjustment of band Phase Processing can for:
The verilog descriptive statement of L_clk generative circuit is following:
Its hardware bearing part of the disclosed clock synchronizing method of this embodiment of the invention described above is above-mentioned disclosed clock synchronization apparatus, but the identical cross-references of both concrete implementations.
In practical application; The methods and apparatus disclosed are carried out in the process of clock synchronization among the disclosed embodiment of application the invention described above; Can select as required is that to carry out internal clocking synchronous; Still it is synchronous to carry out external clock, still outside and inside is not considered, independently generates synchronised clock.Need to prove that each application only can select a kind of situation to carry out clock synchronization.
In sum; The disclosed a kind of clock synchronizing method of the above embodiment of the present invention, install and have the radio frequency chip circuit of this device; Through reset at radio frequency chip and/or the idle situation of corresponding module under; The counter O reset of band Phase Processing is promptly quit work, to reduce the power consumption of radio frequency chip; Generate synchronizing clock signals when receiving the internal clocking lock-out pulse, its phase place can be adjusted according to internal clocking; This synchronised clock is when receiving the external clock lock-out pulse, and its phase place can be adjusted according to external clock; Simultaneously, under the situation that does not receive internal clocking lock-out pulse and external clock lock-out pulse, promptly do not rely on inside, do not rely under the situation of external reference clock yet, can generate the adjustable generation synchronised clock of phase place yet.Phase place is adjustable have been guaranteed the phase relation of clock edge and data to make radio frequency chip can correctly receive data.
Can realize the purpose of low dependence, low cost and low-power consumption through the invention described above disclosed method.
It below only is preferred implementation of the present invention; Should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; Can also make some improvement and retouching, these improvement and retouching also should be regarded as protection scope of the present invention.
The method of describing in conjunction with embodiment disclosed herein or the step of algorithm can be directly with the software modules of hardware, processor execution, and perhaps the combination of the two is implemented.Software module can place the storage medium of any other form known in random asccess memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or the technical field.
To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the present invention.Multiple modification to these embodiment will be conspicuous concerning those skilled in the art, and defined General Principle can realize under the situation that does not break away from the spirit or scope of the present invention in other embodiments among this paper.Therefore, the present invention will can not be restricted to these embodiment shown in this paper, but will meet and principle disclosed herein and features of novelty the wideest corresponding to scope.
Claims (10)
1. the method for a clock synchronization is characterized in that, comprising:
When radio frequency chip is in reset mode or corresponding module and is non operating state, make the counter O reset of band Phase Processing;
When the counter of said band Phase Processing receives the signal of startup work; The counter of said band Phase Processing carries out frequency division to the high frequency clock that the phase-locked loop pll circuit that receives generates; And the adjustment initial phase, generate first synchronised clock as required synchronised clock output;
Whether the counter of the said band Phase Processing of real-time judge receives the internal clocking lock-out pulse in the course of the work;
If the counter of said band Phase Processing is that benchmark carries out the phase place adjustment with the rising edge of internal clocking then, generates second synchronised clock and exports as required synchronised clock;
If not; Whether the counter of judging said band Phase Processing receives the external clock lock-out pulse; If the counter of said band Phase Processing then carries out the phase place adjustment according to the rising edge of detected external clock, generates the 3rd synchronizing clock signals and exports as required synchronised clock.
2. method according to claim 1 is characterized in that, the counter of said band Phase Processing is that benchmark carries out the phase place adjustment with the rising edge of internal clocking, generates second synchronised clock and comprises as the detailed process of synchronised clock output:
The counter of said band Phase Processing receives the current count value of the internal clocking of cycle counter transmission;
Deduct at the current count value of said internal clocking on the basis of required synchronous two clocks, increase phase value adjustment phase place, the rising edge that obtains with said internal clocking is second synchronised clock of benchmark adjustment; Said second synchronised clock is exported as required synchronised clock;
Wherein, said phase value can be on the occasion of or negative value, maximum is the half the of the said PLL circuit target frequency cycle when producing high frequency clock, the said target frequency cycle is the high frequency clock frequency that produces of said PLL and the ratio of target frequency.
3. circuit according to claim 1 is characterized in that, the counter of said band Phase Processing carries out the phase place adjustment according to the rising edge of detected external clock, generates the 3rd synchronised clock and comprises as the detailed process of required synchronised clock output:
The counter of said band Phase Processing receives the outside external clock that sends, and detects the rising edge that synchronizer detects external clock via the edge;
The target frequency cycle when obtaining said PLL circuit and producing high frequency clock;
Deduct on the numerical value basis of high frequency clock required in the synchronizing process at said target frequency cycle numerical value, increase phase value adjustment phase place, the rising edge that obtains with said external clock is the 3rd synchronised clock of benchmark adjustment;
Said the 3rd synchronised clock is exported as required synchronised clock;
Wherein, the said target frequency cycle is the frequency of the clock that produces of said PLL circuit and the ratio of target frequency; Said phase value can be on the occasion of or negative value, maximum is the half the of said target frequency cycle; The numerical value of required high frequency clock is 4 in the synchronizing process.
4. circuit according to claim 1; It is characterized in that; It is benchmark when carrying out the phase place adjustment that the counter of said band Phase Processing need not rising edge with the rising edge of internal clocking or external clock, generates first synchronised clock and comprises as the detailed process of required synchronised clock output:
The target frequency cycle when obtaining said PLL and producing high frequency clock;
On the basis of said target frequency cycle numerical value, increase phase value adjustment phase place, obtain first synchronised clock;
Said first synchronised clock is exported as required synchronised clock.
5. according to any described circuit in the claim 1～4, it is characterized in that, the high frequency clock that said PLL circuit generates, its frequency is higher than required synchronised clock N clock doubly; Wherein, N is more than or equal to 3;
Perhaps, the frequency of the high frequency clock of said PLL circuit generation is the common multiple of the frequency of required synchronised clock.
6. a clock synchronization apparatus is characterized in that, comprising: the counter of band Phase Processing, and the cycle counter that is connected with the counter of said band Phase Processing, and connect the counter of said band Phase Processing and the phase-locked loop pll circuit of said cycle counter;
Said PLL circuit is used to produce high frequency clock;
Said cycle counter is used for the high frequency clock that the said PLL circuit that receives produces is carried out frequency division, generates internal clocking; And the phase meter numerical value of internal clocking is provided to the counter of band Phase Processing;
The counter of said band Phase Processing is used for when radio frequency chip is in reset mode or corresponding module and is in non operating state, quitting work; When receiving the signal of startup work, the high frequency clock that the phase-locked loop pll circuit that receives is generated carries out frequency division, and initial phase is adjustable, generates first synchronised clock as required synchronised clock output; And whether real-time judge receives the internal clocking lock-out pulse in the course of the work;
If then the rising edge with internal clocking is that benchmark carries out the phase place adjustment, the rising edge that generates with said internal clocking is that second synchronised clock that benchmark is adjusted is exported as required synchronised clock;
If not; Judge whether to receive the external clock lock-out pulse again; If then the rising edge according to detected external clock carries out the phase place adjustment, the rising edge that generates with said external clock is that the 3rd synchronised clock that benchmark is adjusted is exported as required synchronised clock.
7. device according to claim 6 is characterized in that, when the counter of said band Phase Processing receives the internal clocking lock-out pulse:
The counter of said band Phase Processing; Be used to receive the current count value of the internal clocking that cycle counter sends; Current count value at said internal clocking deducts on the basis of required two clocks synchronously; Increasing phase value adjustment phase place, is that second synchronised clock that benchmark is adjusted is exported as required synchronised clock with the rising edge that obtains with said internal clocking;
Wherein, said phase value can be on the occasion of or negative value, maximum is the half the of the said PLL circuit target frequency cycle when producing high frequency clock, the said target frequency cycle is the high frequency clock frequency that produces of said PLL and the ratio of target frequency.
8. device according to claim 6 is characterized in that, when the counter of said band Phase Processing receives the external clock lock-out pulse:
The counter of said band Phase Processing, the target frequency cycle when being used to obtain said PLL circuit and producing high frequency clock; Deducting on the numerical value basis of high frequency clock required in the synchronizing process at said target frequency cycle numerical value, increase phase value adjustment phase place, is that the 3rd synchronised clock that benchmark is adjusted is exported as required synchronised clock with what obtain with said external clock rising edge;
Wherein, the rising edge information of said external clock is obtained via edge detection synchronizer; The said target frequency cycle is the frequency of the clock that produces of said PLL circuit and the ratio of target frequency; Said phase value can be on the occasion of or negative value, maximum is the half the of said target frequency cycle; The numerical value of required high frequency clock is 4 in the synchronizing process;
Perhaps, said second synchronised clock is postponed one and clap the back as required synchronised clock output.
9. device according to claim 6 is characterized in that, the high frequency clock that said PLL circuit generates, and it is required synchronised clock N clock doubly for frequency is higher than; Wherein, N is more than or equal to 3;
Perhaps, the frequency of the high frequency clock of said PLL circuit generation is the common multiple of the frequency of required synchronised clock.
10. a radio frequency chip circuit is characterized in that, comprising: clock synchronization apparatus and edge detect synchronizer;
Said clock synchronization apparatus is any described clock synchronization apparatus in the claim 6～9;
Said edge detects synchronizer, is used for detecting the rising edge of external clock when carrying out external clock when synchronous, and then generation external clock lock-out pulse; When carrying out internal clocking when synchronous, detect the rising edge of internal clocking, and then generate the internal clocking lock-out pulse.
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| CN201210090005.9A CN102624382B (en) | 2012-03-29 | 2012-03-29 | Clock synchronization method, device and radio frequency chip circuit with same device |
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| CN103855910A (en) * | 2012-11-28 | 2014-06-11 | 中国科学院微电子研究所 | Radiofrequency power source with adjustable radiofrequency signal phase |
| CN104280613A (en) * | 2014-10-15 | 2015-01-14 | 成都振芯科技股份有限公司 | On-chip signal phase detection and synchronization circuit and synchronization method thereof |
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| CN108155983A (en) * | 2016-12-05 | 2018-06-12 | 中兴通讯股份有限公司 | A kind of method and device of system disturbance offset power consumption fluctuation and introduced |
| CN109995346A (en) * | 2019-03-06 | 2019-07-09 | 杭州城芯科技有限公司 | A kind of high frequency clock synchronous circuit for swallowing circuit based on clock |
| CN110413399A (en) * | 2019-08-16 | 2019-11-05 | 紫光展锐(重庆)科技有限公司 | Operation method and arithmetic unit |
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| CN115378568A (en) * | 2022-08-19 | 2022-11-22 | 深圳市紫光同创电子有限公司 | Clock synchronization circuit and clock synchronization method |
| CN115378568B (en) * | 2022-08-19 | 2023-08-08 | 深圳市紫光同创电子有限公司 | Clock synchronization circuit and clock synchronization method |
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Address after: 510630 Guangdong city of Guangzhou province Panyu District Xiaoguwei Street West Outer Ring Road, room 629, 601-609 hall, Guangdong University of Technology, 100 Patentee after: Rising Micro Electronics Co., Ltd. Address before: Five mountain Wushan Square C620-641 room 510630 Guangdong science and technology city of Guangzhou province Tianhe District Patentee before: Rising Micro Electronics Co., Ltd. |
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