WO2018210277A1 - Clock synchronization method and device, and computer storage medium - Google Patents

Abstract

Disclosed are a clock synchronization method and device. The clock synchronization method comprises: a synchronizing end device generates a time stamp according to a receiving time and a transmitting time of a periodic code block over a predetermined channel; the synchronizing end device transmits a time information message to and receives a time information message from a synchronized end device, and determines a time difference with the synchronized end device according to time stamps of periodic code blocks matching the transmitting and receiving of time information messages; and the synchronizing end device adjusts the system clock according to the determined time difference. Embodiments of the present invention further provide a computer storage medium.

Description

Method and device for clock synchronization, computer storage medium

Cross-reference to related applications

The present disclosure is based on a Chinese patent application filed on Jan. 16, 2017, the entire disclosure of which is hereby incorporated by reference.

Technical field

The present invention relates to the field of communications, and in particular, to a method and apparatus for clock synchronization.

Background technique

Multi-lane (channel) interface pcs (Physical Code Sublayer) and pma (Physical Media Access) are partially distributed due to code blocks, data bit width conversion, and clock domain conversion. The implementation usually uses fifo (First Input First Output), gearbox (gearbox), etc., and the processing delay is not easy to determine. If you still use the time information packet header as the reference point and time stamp on the mac (Media Access Control) layer, the time jitter will be larger and the accuracy will be worse.

At present, improving the time stamping accuracy generally adopts a method of increasing the clock frequency of the time counter. This method reduces the time error to some extent, but due to problems such as the chip process, the clock frequency inside the chip cannot be increased without limitation. The internal frequency of most chips is 1G, that is, the sampling error is 1 ns (nanoseconds), the internal frequency of a few chips can reach 3G, and the sampling error is 300 ps (picoseconds).

Summary of the invention

One aspect of the disclosure provides a method and apparatus for clock synchronization.

Embodiments of the present disclosure provide the following technical solutions.

A method of clock synchronization, comprising:

The synchronization end device generates a timestamp according to the time of receiving and sending the periodic code block on the predetermined channel;

And receiving, by the synchronization end device, the time information packet between the device and the device to be synchronized, and determining the time deviation between the device and the device to be synchronized by using the time stamp of the periodic code block that matches the information of the received and sent time information packet ;

The sync device adjusts the system clock according to the determined time offset.

A clock synchronization device includes: a first processor and a first memory;

The first memory is configured to save a first time synchronization program;

The first processor is configured to execute the first time synchronization program to perform the following operations:

Generating a timestamp according to the time of receiving and sending the periodic code block on the predetermined channel;

And receiving and transmitting a time information packet with the device to be synchronized, and determining a time offset between the device and the device to be synchronized by using a timestamp of the periodic code block that matches the received and sent time information message;

The system clock is adjusted based on the determined time offset.

A clock synchronization device includes:

a timestamp generating module, configured to generate a timestamp according to a receiving and sending time of the periodic code block on the predetermined channel;

The determining module is configured to receive and send a time information message with the device to be synchronized, and determine a time offset between the device and the device to be synchronized by using a timestamp of the periodic code block that matches the received and sent time information message. ;

The adjustment module is configured to adjust the system clock based on the determined time offset.

Yet another aspect of the present disclosure provides a method and apparatus for clock synchronization that can solve errors caused by different clock domains in the case of multiple lane interfaces.

Embodiments of the present disclosure provide the following technical solutions.

A method of clock synchronization is applied to a device including a plurality of time counting systems, the plurality of time counting systems being divided into a master time counting system and a slave time counting system; the method comprising:

Obtaining a common divisor according to the clock of the time counting system according to the main time counting system, and creating a common-counter clock with the common number as a clock frequency;

Synchronizing the commons clock with the clock of the primary time counting system, and synchronizing the clock from the time counting system with the common number clock.

A clock synchronization device is applied to synchronization between a plurality of time counting systems in a device, the plurality of time counting systems being divided into a master time counting system and a slave time counting system; the device comprising: a second processor and Second memory

The second memory is configured to save a second time synchronization program;

The second processor is configured to execute the second time synchronization program to perform the following operations:

Obtaining a common divisor according to the clock of the time counting system according to the main time counting system, and creating a common-counter clock with the common number as a clock frequency;

Synchronizing the commons clock with the clock of the primary time counting system, and synchronizing the clock from the time counting system with the common number clock.

A clock synchronization apparatus is applied to synchronization between a plurality of time counting systems in a device, the plurality of time counting systems being divided into a master time counting system and a slave time counting system; the apparatus comprising:

Creating a module, configured to obtain a common number according to the clock of the time counting system according to the main time counting system, and create a common-counter clock with the common number as a clock frequency;

And a synchronization module configured to synchronize the common number clock with a clock of the primary time counting system, and synchronize the clock of the slave time counting system with the common number clock.

At least one embodiment of the present disclosure records time stamps with periodic locations, effectively avoiding unfixed delays caused by fifo or the like, and improving time synchronization accuracy. In an alternative of this embodiment, the time is counted by the same system clock as the parallel clock (the clock at the periodic code block), and the parallel clock and the system clock are phase-phased to compensate for the time stamp, which can improve the accuracy. .

At least one embodiment of the present disclosure can generate a common-counter clock by calculating a common-counter clock frequency in a case where different rate interfaces use different time counting systems, thereby synchronizing different time counting systems, thereby eliminating sampling caused by different clock domains. error.

Other features and advantages of the present disclosure will be set forth in the description which follows. The objectives and other advantages of the present disclosure can be realized and obtained by the structure particularly pointed out in the appended claims.

DRAWINGS

The drawings are intended to provide a further understanding of the embodiments of the present disclosure, and are intended to be illustrative of the embodiments of the present disclosure.

1 is a schematic flow chart of a method for providing clock synchronization according to an embodiment of the present invention.

FIG. 2 is a schematic flowchart diagram of a method for providing clock synchronization according to an embodiment of the present invention.

FIG. 3 is a block diagram of an implementation provided by Embodiment 1 of the present invention.

4 is a transceiver transmission direction data path provided by Embodiment 1 of the present invention.

FIG. 5 is a transceiver receiving direction data path provided by Embodiment 1 of the present invention.

6a is a block diagram showing an implementation of a 100G interface portion provided by Embodiment 2 of the present invention;

Figure 6b is a block diagram showing the implementation of the GE interface portion of Embodiment 2 of the present invention.

7 is a block diagram showing an implementation of a 100G interface portion of Embodiment 3 of the present invention.

FIG. 8 is a schematic structural diagram of an apparatus for providing clock synchronization according to an embodiment of the present invention; FIG.

FIG. 9 is a schematic structural diagram of an apparatus for providing clock synchronization according to Embodiment 7 of the present invention.

detailed description

The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments in the present disclosure and the features in the embodiments may be arbitrarily combined with each other without conflict.

The steps illustrated in the flowchart of the figures may be executed in a computer system such as a set of computer executable instructions. Also, although logical sequences are shown in the flowcharts, in some cases the steps shown or described may be performed in a different order than the ones described herein.

A method for clock synchronization in this embodiment, as shown in FIG. 1, includes steps S110-S120:

S110. The synchronization end device generates a timestamp according to the time of receiving and sending the aligned code block on the predetermined channel. The timestamp generated according to the receiving and sending time may include: a receiving timestamp generated according to the receiving time, and/or a transmission time stamp generated according to the transmission time;

S120. The time information packet is received and sent between the synchronization end device and the synchronized end device, and the time interval of the aligned code block matched by the receiving and sending time information packet is used to determine the time between the device and the synchronized device. deviation;

S130. The synchronization end device adjusts a system clock according to the determined time offset.

The synchronization device may refer to a device to be synchronized with the device to be synchronized, and the device to be synchronized may refer to a device whose clock is used as a reference standard for synchronization.

The time information packet may include a TP (Precision Timing Protocol) packet, a 1588 packet, and the like.

The periodic code block can be, but is not limited to, an aligned code block.

The periodic code block that matches the receiving and sending time information packet may be, but is not limited to, the sending and receiving time of the previous periodic code block where the time information header is located.

Wherein, the predetermined channel can be, but is not limited to, lane0.

Optionally, the determining, by using the timestamp of the aligned code block that matches the received and sent time information packet, before determining the time offset between the device and the device to be synchronized, may further include:

The synchronization end device performs phase discrimination on the clock used to generate the time stamp and the system clock to obtain a phase difference;

The sync device compensates for the generated timestamp using the phase difference.

In this alternative, the phase discrimination may be performed before or after the time stamp is generated; after the time stamp is generated, the phase difference obtained by phase discrimination may be immediately compensated, or may be compensated when the time offset needs to be calculated.

In this alternative, the clock (system clock) frequency of the time counting system used for time stamping is the same as the clock frequency of the interface parallel clock. For phase discrimination of the two clocks, the phase difference is compensated to the time stamp.

The phase discrimination accuracy determines the accuracy of the time stamping. For example, the phase clock accuracy of the same frequency clock can be up to 1 ps, and the theoretical time stamping accuracy can reach 1 ps.

Optionally, before the step S110, the method may further include:

Synchronizing the system clock of the sync device with the system clock of the device being synced.

Optionally, determining, by using a timestamp of the periodic code block that matches the received and sent time information packet, determining a time offset from the device to be synchronized may include:

Determining the time deviation between the synchronized device and the device according to T1, T2, T3, T4, TC1, TC2, TC3, TC4;

The T1 is the timestamp of the previous periodic code block M1 of the header of the received first time information message, and T2 is the previous period of the message header when the first time information message arrives at the device. The timestamp of the code block M2; T3 is the timestamp of the previous periodic code block M3 of the header of the transmitted second time information message; T4 is the device that the second time information message arrives at the synchronized end device Time stamp of the previous periodic code block M4 of the message header;

TC1 is the time delay between the recording time of the timestamp T1 and the time when the periodic code block M1 issues the device to be synchronized; TC2 is the time between the time when the periodic code block M2 enters the device and the time of recording the timestamp T2. TC3 is the delay between the time of recording of the timestamp T3 and the time when the periodic code block M3 issues the device; TC4 is between the time when the periodic code block M4 enters the device of the synchronized end to the time of recording of the timestamp T4 Delay.

Optionally, the step S130 may include:

The synchronization end device adjusts a value of a time counter in the main time counting system in the synchronization end device according to an integral multiple of a clock period in the time offset, and the remaining portion adjusts a phase of the main clock in the main time counting system .

Optionally, the step S130 may further include:

The synchronization end device obtains a common number according to the clock time of the time counting system of the main time counting system in the synchronous end device, and creates a common number clock with the common number as the clock frequency;

The synchronization end device synchronizes the common number clock with the clock of the main time counting system, and synchronizes the clock of the slave time counting system with the common number clock.

In this alternative, the main time counting system may be pre-designated or defaulted, or may be selected by the synchronizing end device from one of the plurality of time counting systems as the main time counting system according to the agreed rules, and the rest is used as the slave time counting system.

Optionally, the synchronizing the common number clock with the clock of the main time counting system, and synchronizing the clock of the time counting system with the common number clock may include:

a rising edge of the clock of the main time counting system when the rising edge of the common number clock is aligned to an integer multiple of m, so that the rising edge of the clock counting from the time counting system is an integer multiple of n and the common divisor Align the rising edge of the clock;

Where m is equal to the clock frequency of the master clock counting system divided by the common divisor; n is equal to the clock frequency of the slave clock counting system divided by the common divisor.

The embodiment provides a method for clock synchronization, which is applied to a device including multiple time counting systems, which are divided into a main time counting system and a slave time counting system; the method is as shown in FIG. 2 Including steps S210-S220:

S210. Obtain a common divisor according to the clock of the time counting system according to the main time counting system, and create a common-counter clock with the common number as a clock frequency;

S220. Synchronize the common number clock with the clock of the main time counting system, and synchronize the clock of the slave time counting system with the common number clock.

In this embodiment, the clock frequency of the time counting system used for time stamping is related to the interface rate, and the different rate interfaces correspond to time counting systems at different clock frequencies, and each time counting system uses the common number as the clock frequency clock for synchronization.

In this embodiment, the slave time counting system may first perform coarse synchronization with the master time counting system, and then perform fine synchronization according to the above method.

In this embodiment, the main time counting system in the plurality of time counting systems may be pre-designated or defaulted, or may be selected by the synchronizing end device from the plurality of time counting systems as the main time counting system according to the agreed rules, and the rest is taken as the slave time counting system. Time counting system.

Optionally, step S220 may include:

a rising edge of the clock of the main time counting system when the rising edge of the common number clock is aligned to an integer multiple of m, so that the rising edge of the clock counting from the time counting system is an integer multiple of n and the common divisor Align the rising edge of the clock;

Where m is equal to the clock frequency of the master clock counting system divided by the common divisor; n is equal to the clock frequency of the slave clock counting system divided by the common divisor.

Optionally, before the step S210, the method may further include:

Generating a timestamp according to the time of receiving and sending the periodic code block on the predetermined channel;

And receiving and transmitting a time information packet with the device to be synchronized, and determining a time offset between the device and the device to be synchronized by using a timestamp of the periodic code block that matches the received and sent time information message;

The clock of the master count time system is adjusted based on the determined time offset.

In this alternative, the device including multiple time counting systems may be regarded as a synchronous device.

Further implementation details of this alternative can be found in the previous embodiments.

In this embodiment, a clock synchronization method is used. In this embodiment, the periodic code block adopts an alignment code block AM. The process of clock synchronization includes the following steps S310-S370:

Step S310, frequency synchronization.

The synchronization end device is synchronized with the frequency of the system clock of the device being synchronized. .

In step S320, a time stamp is generated.

Detects the alignment code block AM of the specified lane in the sending and receiving direction, records the time of sending or arriving, and generates a timestamp.

The timestamp may be generated by a time counting system corresponding to the aligned code block; wherein the time counting system corresponding to the aligned code block may include an interface parallel clock (ie, a clock corresponding to the interface parallel data) and a time counter.

In step S330, the system clock and the interface parallel clock phase detector.

The system time of the sync device or the sync device is generated by the system clock; and the alignment block AM is processed under the interface parallel clock. The two clocks have a certain phase difference, which needs to be phased out to obtain a phase difference.

The generated time stamp is compensated using the phase difference.

Step S340, time information is transmitted.

First, the synchronization end sends a time information packet, and carries the timestamp T1 corresponding to the previous alignment code block of the packet header when the time information packet is sent, and the recording time of the timestamp T1 to the time when the alignment code block is sent to the device. The delay is TC1. After receiving the time information packet, the synchronization end parses the time information packet to obtain T1 and TC1. Recording the timestamp T2 of the previous alignment code block of the message header when the time information message arrives, and the delay TC2 between the time when the alignment code block enters the device and the recording time of the timestamp T2.

The synchronization end sends the time information message to the synchronized end, and records the timestamp T3 of the previous alignment code block of the message header when the time information message is sent, and the time of recording the timestamp T3 to the time when the alignment code block is sent by the device. The delay is TC3, TC3 is carried to the message, and T3 is saved to the local. The synchronization end receives the time information packet, parses the time information packet, and obtains TC3; records the timestamp T4 of the previous alignment code block of the packet header when the packet arrives, and the time-to-time stamp of the alignment code block entering the device. The delay between the recorded moments of T4 is TC4.

The T4 and TC34 (=TC3+TC4) are carried in the time information message by the synchronization end and sent to the synchronization end.

After the synchronization end receives, pair T4 and TC34 with T3, but it is not limited to pairing by the serial number of the time information message. In this way, the sync end gets two sets of time values:

1) T1, T2, TC21 (= TC1 + TC2);

2) T3, T4, TC34;

Among them, the values of TC1, TC2, TC3, and TC4 should be fixed or changed, for example, can be obtained through experiments or tests. Step S350, time stamp processing.

According to the two sets of time values obtained in step S340, the time deviation of the synchronization end with respect to the synchronized end is calculated. Calculated as follows:

T1+delay+offset+TC21=T2

T3+delay-offset+TC 34=T4

The delay is the length of time required for the interface of the time information message to be synchronized and the interface of the synchronization end. Offset is the time deviation of the synchronization end relative to the synchronization end. The specific values of delay and offset can be calculated by the above two formulas.

In step S360, the main time counting system is selected.

The master time counting system can be based on the interface used for time synchronization.

For example, the current time synchronization uses a 100G (4*25G) interface, and the 322.265625 MHz time counting system is the main time counting system. If the current time synchronization uses the GE interface, the 125 MHz time counting system is the master time counting system.

The master time counting system may include a master clock and a master time counter. The clock frequency and clock period of the main clock, that is, the clock frequency and clock period of the main time counting system, are also called the main clock frequency and the main clock period.

Step S370, clock adjustment.

The value of the main time counter is adjusted according to the integral part of the clock period in the time deviation, and the remaining part adjusts the main clock phase.

For example, the time deviation = S1 × T + S2, where T is the clock period of the main clock; then the value of the main time counter can be added to S1, and the main clock phase is added to S2.

S1 and S2 may be positive or negative.

Other time counting systems (also known as slave time counting systems) are synchronized with the master time system, wherein the slave time counting system can include a slave clock and a slave time counter. The clock frequency of the slave clock, the clock cycle, that is, the clock frequency of the system, and the clock cycle, also called the slave clock frequency, the slave clock cycle.

The synchronization method is as follows:

Assume that the clock frequency of the main time counting system is xHz (hertz), the clock period is 1/x second, the clock frequency of the slave time counting system is yHz, the clock period is 1/y second, and the clock frequency of the master and slave time counting system The common divisor is zHz. When the common divisor is used as the clock frequency, the clock period is 1/z second. The three clock frequencies have the following relationship:

Available from the above two formulas:

That is, one clock cycle of the common number clock is m main clock cycles or n slave clock cycles, that is, if the clock cycle is counted, the master clock counts m number of clocks, and the slave clock counts n times, The convention number clocks are equal in time.

To perform time synchronization between the master and slave time counting systems, first determine a common-counter clock with a common number as the clock frequency, so that the rising edge of the common-count clock is aligned with the rising edge of the master clock when the count is an integer multiple of m. The rising edge when the slave clock is counted as an integer multiple of n is aligned with the rising edge of the common-numbered clock, thereby synchronizing the master and slave time counting systems. Here, the rising edge of the slave clock may be first aligned with the rising edge of the common-counter clock, and the rising edge of the clock when the master clock is counted as an integer multiple of m is aligned with the rising edge of the common-numbered clock. To synchronize the master and slave time counting systems.

The slave time counting system may first perform coarse synchronization with the master time counting system, and then perform fine synchronization according to the above method.

The above embodiment will be described below using three embodiment examples. In the following embodiment, the alignment code block AM is used as the periodic code block as an example, and the actual application is not limited thereto.

Implementation example 1

This embodiment example is illustrated by taking a 100G (4*25G) interface as an example. Time synchronization is implemented by the 1588 protocol, that is, the time information packet is 1588. The block diagram of the synchronization device is shown in Figure 3. The packets received by the transceiver are bit-demultiplexed and then divided into multiple lanes. Each LANe performs block synchronization and AM detection respectively. When sending packets, timestamps are added. The AM detection is performed separately, and the bit is mixed and transmitted by the transceiver. Performs 1588 packet identification on the received packet, extracts and records the timestamp obtained by the AM detection (receiving and transmitting direction), and compensates by the result of the clock phase-detection; and receives and sends the 1588 packet and the matched AM time. Poke, perform offset calculation, adjust the 322.265625MHz time counter and clock according to the calculated offset.

The device to be synchronized can also adopt the structure shown in FIG. 3 to bypass the unnecessary modules.

This embodiment example includes the following steps 101 to 106.

101, data transmission and reception.

The transceiver (transceiver) transceiver direction bypasses the codec, buffer (buffer), gearbox and other modules. The data trend is shown in bold lines in Figures 4 and 5.

At the origin, Polarity is reached from the TX interface via multiple selectors; equivalent to bypassing the encoding module, gearbox, pattern generator, fifo, SATA (Serial Advanced Technology Attachmen) , Serial Advanced Technology Attachment) OOB (Out of Band), PCIe (peripheral component interconnect express) Beacon (beacon) and other modules.

At the receiving end, from the SIPO (serial in parallel) to Polarity, after passing through multiple selectors to reach the RX interface (receive interface); equivalent to bypassing decoding, Buffer, gearbox, Comma Detect and Align (character detection and Align) and other modules.

102, timestamp generation

In this implementation example, the timestamp of 1588 is based on the sending and receiving time of the aligned code block AM of any one of the 100G interfaces. For example, it can be the sending and receiving time of the previous AM where the 1588 packet header is located.

The AM timestamp matches the 1588 packet. The processing time delay of the AM timestamp to the 1588 identification is fixed. There is no jitter. Otherwise, a matching error occurs, and the probability of an error is uncertain. To solve this problem, there are two ways:

method one:

According to the interval for sending packets, you can set a special AM value. The timestamp is based on this special AM value.

Take the AM of the Lane0 as an example. When the packet sending rate is 16/s, a special AM is generated every 297 AMs. The AM of the Lane0 is normal. The value is {0xc1, 0x68, 0x21, BIP3. , 0x3e, 0x97, 0xde, BIP7}, the value of the special AM reverses the BIP7 byte by bit, and the other bytes have the same value as the normal AM.

Method Two:

Controls the time interval between the time information packet header and the AM. When the interval exceeds the threshold time, it waits for the next AM to resend the packet.

103, timestamp conversion

The clock frequency of the 100G (4*25G) interface alignment code block detection part is 322.265625MHz, and the time stamp is also used by the system 322.265625MHz time counting system. The 322.265625MHz time counter is 80bit, divided into two parts: 1) high 48bit is the second part; 2) low 32bit is 322.265625MHz clock cycle count value. When a timestamp is added to a message, the second part can be directly added to the second part of the message timestamp, and the clock cycle count value needs to be converted into a unit of nanoseconds, and then added to the nanosecond of the message timestamp. section. The clock cycle count value cnt_cycle is converted into a value of nnt_ns in nanoseconds, which is divided into two cases:

(1) When cnt_cycle is n times 165, cnt_ns is n times 512. Where n is an integer.

(2) When cnt_cycle is another value, use a divider, divide cnt_cycle by 165, and the quotient processing method is the same as (1), and get the cnt_ns_1; the remainder is recorded as the remainder, and the clock period of 322.265625M is 3.1030303... nanoseconds. Is an infinite loop decimal, can not get the exact value, take 7 decimal places, each add 1 for reminder, add 3.1030303 for cnt_ns_2, when the remainder is 164, the conversion accuracy is still sub-ps level. The cnt_ns corresponding to Cnt_cycle is cnt_ns_1 plus cnt_ns_2.

When cnt_cycle has a decimal, the integer part can be added to the timestamp and the fractional part added to the correction field.

104, time stamp compensation

Timestamp compensation is placed in the correction field, and the compensation content includes:

(1) The phase detection value of the recovery clock and the system clock is directly added to the correction domain.

(2) The fractional part of the timestamp conversion cnt_cycle_decimal. In the receiving direction, 0-cnt_cycle_decimal is added to the correction field, and the sending direction directly adds cnt_cycle_decimal to the correction field.

(3) The first bit of the special AM of lane0 is compensated for the p-th bit of the 16-bit data; p is a positive integer.

(4) The data in the receiving direction lane0 is not compensated in the first way after bit_demux.

105, time deviation offset calculation

The offset calculation can implement steps S340 and S350 in the foregoing embodiment, wherein the time information message adopts a 1588 message, and the calculation result includes a fractional part.

106, time counter and clock phase adjustment.

The unit of offset is nanosecond. To adjust the count of 322.265625MHz clock, it needs to be converted to the number of clock cycles offset_cycle and the remaining part offset_decimal. Offset_cycle adjusts the value of the time counter, offset_decimal adjusts the clock phase.

Implementation example 2

The device of this embodiment has both 100G and GE interfaces. The time counter of the 100G interface uses a clock of 322.265625 MHz, and the time counter of the GE interface uses a clock of 125 MHz. The time information packet includes a synchronization packet and a delayyeq packet. In this embodiment, the composition of the 100G interface part in the synchronous end device is as shown in FIG. 6a, and the time count value is obtained after the AM detection and the time stamp is converted (the time stamp conversion can also be performed in the implementation example 1). The composition of the GE interface section is shown in Figure 6b. The device to be synchronized can also use the structure shown in Figures 6a and 6b to bypass the modules that are not needed. "b" in Fig. 6a and Fig. 6b is an abbreviation for the word "bit", indicating a bit.

In this embodiment, the 322.226525 MHz clock is the main clock, and the 125 MHz clock is the slave clock; the offset calculation portion in FIG. 6b can be bypassed. If the case where the 125 MHz clock is the main clock, the offset calculation portion in Fig. 6a can be bypassed, and the offset calculation portion in Fig. 6b is also connected to the time stamp extraction/recording portion of Fig. 6a.

When the time is synchronized between the 100G interfaces, a similar method to the first embodiment is used to adjust the time system of 322.265625 MHz. The difference is in the timestamp location:

First, select a lane of the 100G interface arbitrarily. For example, if you select lane0, the sending direction generates a pulse at the position where the lane0 is inserted into the AM, and records the time value corresponding to the pulse. After receiving the code block boundary in the block_sync module, the receiving direction detects the AM position of lane0 and generates a pulse. The clock is counted by the time counting clock to record the time value.

Take the 1588E2E synchronization method as an example.

The device that is the master (that is, the device that is being synchronized) sends a sync (synchronization) message, and the AM detection module detects the value of the time counter of the 322.265625 MHz (ie, the time count value in the figure) at the time of AM, and performs timestamp conversion. Get the standard timestamp format, recorded as T1, added to the sync message. At the same time, the delay TC1 of the AM detection position to the device exit position is added to the CF field of the sync message.

The Slave device (ie, the sync device) detects the AM in the receive direction, records the time counter value at the AM time, and converts it into an ns value. The 1588 message identification module identifies the sync message, records the timestamp of the corresponding AM, and is T2, extracts the TC1 in the CF, adds the local compensation TC2, records it as TC21, and extracts T1 from the message, thereby obtaining T1, T2, and TC21. .

Delayreq message:

The 1588 sending module of the Slave device sends a delayeq message, and the AM detecting module detects the value of the 322.265625 MHz time counter at the time of AM (that is, the time count value in the figure) to perform timestamp conversion, and obtains a standard timestamp format, which is recorded as T3, and The serial number seqid is stored as an address, and the delay TC3 of the AM detection location to the device exit location is added to the CF field of the delayeqe message.

The receiving direction of the master device, the AM detecting module detects that the value of the 322.265625 MHz time counter at the time of AM is converted into a standard timestamp format, the 1588 message identifying module identifies the delayreq message record T4, extracts the TC3 in the CF, and compensates the TC4 for the TC34. , reply the delayresp message to the slave device.

The Master device 1588 sends a packet module to reply to the delayresp message, carrying T4 and TC34.

The Slave device receives the delayresp message, extracts seqid, T4 and TC34, reads T3 with seqid, and stores T3, T4 and TC34 to ram (random access memory) for cpu (central processing) reading.

The time synchronization between the GE interfaces adopts the traditional method of adding compensation. The time counter uses 125M clock, the time adjustment is also the deviation adjustment time counter value of 8 ns multiple, and the deviation of 8 ns or less adjusts the clock phase.

This embodiment has two time counting systems, and the two systems need to be synchronized, and can be accurate when switching or publishing time to downstream devices. Take the 125M time system synchronization 322.265625M time system as an example to describe the two time system synchronization methods, as follows:

First, generate a common clock frequency clock_common with a frequency of 1.953125MHz. This clock is homologous to the 125 MHz clock and the 322.265625 MHz clock and is phase aligned with the 322.626525 MHz clock.

201, clock_common and 322.265625MHz time system alignment.

From the equation (1) in the step S360 of the foregoing embodiment, the value of m is 165, a signal clk_322_div is defined, initialized to 0, and the clock count of 322.265625 MHz is counted to a multiple of 165 minus 1, and clk_322_div is inverted.

Detecting the time that clk_322_div lags with the rising edge of clock_common. If it is less than 3 nanoseconds, it considers clock_common to be synchronized with 322.265625MHz. Otherwise, adjust the phase of clock_common. If clock_common is still aligned with 322.265625MHz, make clk_322_div relative to clock_common. The rise lag time is less than 3 ns.

202, 125M time counting system and 322.265625MHz time counting system coarse alignment

The two time counting systems are coarsely aligned by adjusting the counter.

The 203, 125M time counting system is finely aligned with the clock_common.

First, the 125M clock is aligned with clock_common.

From the equation (2) in the step S360 of the foregoing embodiment, the value of m is 64, the signal clk_125_div is defined, and the initialization is 0. When the time count of 125 MHz is counted to a multiple of 64 minus 1, the clk_125_div is inverted.

The time when the clk_125_div is delayed relative to the rising edge of the clock_common is detected. If it is less than 8 nanoseconds, the 125 MHz time system is considered to be aligned with the clock_common, otherwise the count value of the 125 MHz time counting system is adjusted, so that the clk_125_div is delayed by less than 8 nanoseconds with respect to the rising edge of the clock_common.

Implementation example 3

This embodiment is similar to the implementation example 2. The composition of the 100G interface part in the synchronous device is as shown in FIG. 7 , and is basically similar to FIG. 6 a , except that the time count value is not converted; the composition of the GE interface part is as shown in FIG. 6 b . Show. The device to be synchronized can also adopt the structure shown in FIG. 7 to bypass the unnecessary modules.

In this embodiment, the 322.226525 MHz clock is the main clock, and the 125 MHz clock is the slave clock; the offset calculation portion in FIG. 6b can be bypassed. If the case where the 125 MHz clock is the main clock, the offset calculation portion in Fig. 7 can be bypassed, and the offset calculation portion in Fig. 6b is also connected to the time stamp extraction/recording portion of Fig. 7.

Due to the implementation example 2, when the 100G interface is synchronized, the timestamp conversion loses a part of the precision, and the implementation is complicated. This embodiment does not perform the conversion of the time count value to the nanosecond.

When the 100G interface is time synchronized, the lower 32 bits of the time stamp, that is, the nanosecond portion, is changed to the count value of the 322.265625 MHz clock cycle. The high 48bit is still the second part.

The embodiment provides a clock synchronization device, including: a first processor and a first memory;

The first memory is configured to save a first time synchronization program;

The first processor is configured to execute the first time synchronization program to perform the following operations:

Generating a timestamp according to the time of receiving and sending the periodic code block on the predetermined channel;

And receiving and transmitting a time information packet with the device to be synchronized, and determining a time offset between the device and the device to be synchronized by using a timestamp of the periodic code block that matches the received and sent time information message;

The system clock is adjusted based on the determined time offset.

The device of this embodiment may be disposed on the synchronization device.

Optionally, determining the time offset between the devices that are synchronized by the time interval of the received and transmitted time information message and the matched periodic code block may include:

Determining the time deviation between the synchronized device and the device according to T1, T2, T3, T4, TC1, TC2, TC3, TC4;

The T1 is the timestamp of the previous periodic code block M1 of the header of the received first time information message, and T2 is the previous period of the message header when the first time information message arrives at the device. The timestamp of the code block M2; T3 is the timestamp of the previous periodic code block M3 of the header of the transmitted second time information message; T4 is the device that the second time information message arrives at the synchronized end device Time stamp of the previous periodic code block M4 of the message header;

TC1 is the time delay between the recording time of the timestamp T1 and the time when the periodic code block M1 issues the device to be synchronized; TC2 is the time between the time when the periodic code block M2 enters the device and the time of recording the timestamp T2. TC3 is the delay between the time of recording of the timestamp T3 and the time when the periodic code block M3 issues the device; TC4 is between the time when the periodic code block M4 enters the device of the synchronized end to the time of recording of the timestamp T4 Delay.

Optionally, the adjusting the system clock according to the determined time offset may include:

Adjusting the main time counting system according to the time deviation; for example, but not limited to, adjusting the value of the time counter of the main time counting system in the synchronous end device according to the part of the clock period in the time interval, and adjusting the value of the time counter of the remaining time device Time counting the phase of the clock of the system;

According to the main time counting system, the common number is obtained from the clock frequency of the time counting system, and the common law clock with the common number as the clock frequency is created;

Synchronizing the commons clock with the clock of the primary time counting system, and synchronizing the clock from the time counting system with the common number clock.

When the apparatus of this embodiment is disposed on the synchronous end device, the master and slave time counting system refers to the master and slave time counting system in the synchronous end device.

Further implementation details can be found in the previous embodiments.

The embodiment provides a device for clock synchronization, which is applied to synchronization between multiple time counting systems in a device. The plurality of time counting systems are divided into a main time counting system and a slave time counting system; the device includes: a second processor and a second memory;

The second memory is configured to save a second time synchronization program;

The second processor is configured to execute the second time synchronization program to perform the following operations:

Obtaining a common divisor according to the clock of the time counting system according to the main time counting system, and creating a common-counter clock with the common number as a clock frequency;

Synchronizing the commons clock with the clock of the master time counting system to synchronize the clock of the slave time counting system with the commonsake clock.

The device of this embodiment may be disposed on the synchronization device.

Optionally, the obtaining the common divisor according to the clock frequency of the master and slave time counting systems may further include:

Generating a timestamp according to the time of receiving and sending the periodic code block on the predetermined channel;

And receiving and transmitting a time information packet with the device to be synchronized, and determining a time offset between the device and the device to be synchronized by using a timestamp of the periodic code block that matches the received and sent time information message;

Adjusting a clock of the primary counting time system according to the determined time offset; for example, but not limited to, adjusting a value of a time counter of the primary time counting system in the synchronous end device according to a portion that is an integer multiple of a clock period in the time offset, The remaining portion adjusts the phase of the clock of the master time counting system.

Other embodiments may implement the foregoing embodiments.

This embodiment provides a device for clock synchronization, as shown in FIG. 8, including:

The timestamp generating module 61 is configured to generate a timestamp according to the receiving and sending time of the periodic code block on the predetermined channel;

The determining module 62 is configured to receive and send a time information message with the device to be synchronized, and determine the time between the device and the device to be synchronized by using the timestamp of the periodic code block that matches the information of the received and sent time information. deviation;

The adjustment module 63 is configured to adjust the system clock based on the determined time offset.

The device of this embodiment may be disposed on the synchronization device.

Optionally, the determining, by using the timestamp of the periodic code block that matches the received and sent time information packet, determining the time offset between the device and the synchronized device may include:

The determining module determines, according to T1, T2, T3, T4, TC1, TC2, TC3, TC4, a time offset between the device and the synchronized device;

The T1 is the timestamp of the previous periodic code block M1 of the header of the received first time information message, and T2 is the previous period of the message header when the first time information message arrives at the device. The timestamp of the code block M2; T3 is the timestamp of the previous periodic code block M3 of the header of the transmitted second time information message; T4 is the device that the second time information message arrives at the synchronized end device Time stamp of the previous periodic code block M4 of the message header;

TC1 is the time delay between the recording time of the timestamp T1 and the time when the periodic code block M1 issues the device to be synchronized; TC2 is the time between the time when the periodic code block M2 enters the device and the time of recording the timestamp T2. TC3 is the delay between the time of recording of the timestamp T3 and the time when the periodic code block M3 issues the device; TC4 is between the time when the periodic code block M4 enters the device of the synchronized end to the time of recording of the timestamp T4 Delay.

Optionally, the adjusting module, according to the determined time offset, adjusting the system clock, may include:

The adjusting module adjusts the main time counting system according to the time deviation, such as but not limited to including adjusting a value of a time counter of the main time counting system in the synchronous end device according to a part of an integral multiple of a clock period in the time offset, and remaining Partially adjusting the phase of the clock of the main time counting system; obtaining a common divisor according to the clock of the time counting system according to the main time counting system, and creating a common-counter clock with the common number as the clock frequency; Synchronizing with the clock of the master time counting system, the clock from the time counting system is synchronized with the commonsake clock.

When the apparatus of this embodiment is disposed on the synchronous end device, the master and slave time counting system refers to the master and slave time counting system in the synchronous end device.

Further implementation details can be found in the previous embodiments.

In an example of the embodiment, the time synchronization device is disposed in the synchronization device, and may include:

The time information generating module includes a plurality of time counters, which are respectively operated under local clock domains of different frequencies. These clock frequencies correspond to each rate interface.

The timestamp generating module is configured to detect the position of the aligned code block for any one of the specified lanes, and record the timestamp of the time. Note that the send and receive direction record timestamp must use the same lane alignment block.

The determining module may include a message generating unit, a message parsing unit, a clock phase identifying unit, and a time stamp processing unit. among them:

The packet generating unit is configured to generate a packet carrying time information, and add a timestamp corresponding to the sending direction alignment code block to the time information packet.

The packet parsing unit is configured to parse the time information packet in the receiving direction and parse the timestamp carried by the packet.

The clock phase detecting unit is configured to phase-detect the parallel clock and the system clock to obtain a phase difference, and use the phase difference to compensate the generated time stamp.

The timestamp processing unit is configured to store a timestamp carried in the packet and a timestamp recorded in the receiving direction, and calculate a time offset.

The adjustment module is configured to adjust the value of the main time counter and the phase of the main clock according to the time deviation. It can also be used to synchronize the values of other time counters and the phase of the clock with the master time counting system.

The frequency synchronization module is configured to synchronize the clock frequency of the synchronization end device to be synchronized by the synchronization end device.

The embodiment provides a clock synchronization device, which is applied to synchronization between multiple time counting systems in a device. The multiple time counting systems are divided into a main time counting system and a slave time counting system; as shown in FIG. The device includes:

The creating module 71 is configured to obtain a common number according to the clock of the time counting system according to the main time counting system, and create a common number clock with the common number as a clock frequency;

The synchronization module 72 is configured to synchronize the common number clock with the clock of the primary time counting system, and synchronize the clock of the slave time counting system with the common number clock.

The device of this embodiment may be disposed on the synchronization device.

Optionally, the device may further include:

a timestamp generating module, configured to generate a timestamp according to a receiving and sending time of the periodic code block on the predetermined channel;

The determining module is configured to receive and send a time information message with the device to be synchronized, and determine a time offset between the device and the device to be synchronized by using a timestamp of the periodic code block that matches the received and sent time information message. ;

An adjustment module configured to adjust a clock of the primary time counting system according to the determined time offset; for example, but not limited to, including a part of an integer multiple of a clock period in the time offset, and adjusting a primary time counting system in the synchronous end device The value of the time counter, the remainder of which adjusts the phase of the clock of the master time counting system.

Other embodiments may implement the foregoing embodiments.

The present embodiment is a storage medium for storing computer-executable instructions. The computer-executable instructions may implement the time synchronization method provided by one or more embodiments of the foregoing embodiments, for example, 1 and / or the method shown in Figure 2.

The computer storage medium can be a non-transitory storage medium, such as a read-only storage medium, a flash memory, an optical disk, a mobile hard disk, a USB flash drive, or a magnetic tape. The embodiments disclosed in the present disclosure are as described above, but are merely used to facilitate the understanding of the present disclosure, and are not intended to limit the present disclosure. Any modification or variation in the form and details of the implementation may be made by those skilled in the art without departing from the spirit and scope of the disclosure. The scope defined by the appended claims shall prevail.

Industrial applicability

The embodiment of the present disclosure provides a method for clock synchronization, which effectively avoids the unfixed delay caused by fifo and the like, improves the time synchronization precision, has positive beneficial effects, and is simple to implement, and has the characteristics that can be widely used in the industry.

Claims (19)

1. A method of clock synchronization, comprising:

   The synchronization end device generates a timestamp according to the time of receiving and sending the periodic code block on the predetermined channel;

   And receiving, by the synchronization end device, the time information packet between the device and the device to be synchronized, and determining the time deviation between the device and the device to be synchronized by using the time stamp of the periodic code block that matches the information of the received and sent time information packet ;

   The sync device adjusts the system clock according to the determined time offset.
2. The method of claim 1, wherein the determining, by the timestamp of the periodic code block that matches the received and transmitted time information message, before determining the time offset from the device being synchronized, further comprises:

   The synchronization end device performs phase discrimination on the interface parallel clock and the system clock to obtain a phase difference;

   The generated time stamp is compensated using the phase difference.
3. The method of claim 1, wherein the determining a time offset from the device being synchronized by the time stamp of the periodic code block that matches the received and transmitted time information message comprises:

   Determining the time deviation between the synchronized device and the device according to T1, T2, T3, T4, TC1, TC2, TC3, TC4;

   The T1 is the timestamp of the previous periodic code block M1 of the header of the received first time information message, and T2 is the previous period of the message header when the first time information message arrives at the device. The timestamp of the code block M2; T3 is the timestamp of the previous periodic code block M3 of the header of the transmitted second time information message; T4 is the device that the second time information message arrives at the synchronized end device Time stamp of the previous periodic code block M4 of the message header;

   TC1 is the time delay between the recording time of the timestamp T1 and the time when the periodic code block M1 issues the device to be synchronized; TC2 is the time between the time when the periodic code block M2 enters the device and the time of recording the timestamp T2. TC3 is the delay between the time of recording of the timestamp T3 and the time when the periodic code block M3 issues the device; TC4 is between the time when the periodic code block M4 enters the device of the synchronized end to the time of recording of the timestamp T4 Delay.
4. The method of claim 1 wherein said synchronizing device adjusts a system clock based on said determined time offset comprises:

   The synchronization end device adjusts a value of a time counter in the main time counting system in the synchronization end device according to an integral multiple of a clock period in the time offset, and the remaining portion adjusts a phase of the main clock in the main time counting system .
5. The method of claim 4, wherein the adjusting the device to adjust the system clock according to the determined time offset further comprises:

   The synchronization end device obtains a common number according to the clock time of the time counting system according to the main time counting system in the synchronous end device, and creates a common number clock with the common number as the clock frequency;

   The synchronization end device synchronizes the common number clock with the clock of the main time counting system, and synchronizes the clock of the slave time counting system with the common number clock.
6. A method of clock synchronization is applied to a device including a plurality of time counting systems, the plurality of time counting systems being divided into a master time counting system and a slave time counting system; the method comprising:

   Obtaining a common divisor according to the clock of the time counting system according to the main time counting system, and creating a common-counter clock with the common number as a clock frequency;

   Synchronizing the commons clock with the clock of the primary time counting system, and synchronizing the clock from the time counting system with the common number clock.
7. The method of claim 6 wherein said synchronizing said commons-counter clock with a clock of a master time counting system, synchronizing a clock of said time counting system with said common-numbered clock comprises:

   a rising edge of the clock of the main time counting system when the rising edge of the common number clock is aligned to an integer multiple of m, so that the rising edge of the clock counting from the time counting system is an integer multiple of n and the common divisor Align the rising edge of the clock;

   Where m is equal to the clock frequency of the master clock counting system divided by the common divisor; n is equal to the clock frequency of the slave clock counting system divided by the common divisor.
8. The method of claim 6 wherein said prior to obtaining a common divisor from the clock frequency of the time counting system based on the primary time counting system further comprises:

   Generating a timestamp according to the time of receiving and sending the periodic code block on the predetermined channel;

   And receiving and transmitting a time information message with the device to be synchronized, and determining a time offset between the device and the device to be synchronized by using a time stamp of the periodic code block that matches the time information message of the receiving and transmitting time;

   The clock of the master count time system is adjusted based on the determined time offset.
9. A clock synchronization device includes: a first processor and a first memory;

   The first memory is configured to save a first time synchronization program;

   The first processor is configured to execute the first time synchronization program to perform the following operations:

   Generating a timestamp according to the time of receiving and sending the periodic code block on the predetermined channel;

   And receiving and transmitting a time information packet with the device to be synchronized, and determining a time offset between the device and the device to be synchronized by using a timestamp of the periodic code block that matches the received and sent time information message;

   The system clock is adjusted based on the determined time offset.
10. The apparatus of claim 9, wherein the determining, by the timestamp of the periodic code block that matches the received and transmitted time information message, determining a time offset from the device being synchronized includes:

    Determining the time deviation between the synchronized device and the device according to T1, T2, T3, T4, TC1, TC2, TC3, TC4;

    The T1 is the timestamp of the previous periodic code block M1 of the header of the received first time information message, and T2 is the previous period of the message header when the first time information message arrives at the device. The timestamp of the code block M2; T3 is the timestamp of the previous periodic code block M3 of the header of the transmitted second time information message; T4 is the device that the second time information message arrives at the synchronized end device Time stamp of the previous periodic code block M4 of the message header;

    TC1 is the time delay between the recording time of the timestamp T1 and the time when the periodic code block M1 issues the device to be synchronized; TC2 is the time between the time when the periodic code block M2 enters the device and the time of recording the timestamp T2. TC3 is the delay between the time of recording of the timestamp T3 and the time when the periodic code block M3 issues the device; TC4 is between the time when the periodic code block M4 enters the device of the synchronized end to the time of recording of the timestamp T4 Delay.
11. The apparatus of claim 9 wherein said adjusting said system clock based on said determined time offset comprises:

    Adjusting the main time counting system according to the time deviation;

    According to the main time counting system, the common number is obtained from the clock frequency of the time counting system, and a common-counter clock with the common number as the clock frequency is created;

    Synchronizing the commons clock with the clock of the primary time counting system, and synchronizing the clock from the time counting system with the common number clock.
12. A clock synchronization device is applied to synchronization between a plurality of time counting systems in a device, the plurality of time counting systems being divided into a master time counting system and a slave time counting system; the device comprising: a second processor and Second memory

    among them:

    The second memory is configured to save a second time synchronization program;

    The second processor is configured to execute the second time synchronization program to perform the following operations:

    Obtaining a common divisor according to the clock of the time counting system according to the main time counting system, and creating a common-counter clock with the common number as a clock frequency;

    Synchronizing the commons clock with the clock of the primary time counting system, and synchronizing the clock from the time counting system with the common number clock.
13. The apparatus of claim 12, wherein said obtaining a common divisor based on a clock frequency of the master and slave time counting systems further comprises:

    Generating a timestamp according to the time of receiving and sending the periodic code block on the predetermined channel;

    And receiving and transmitting a time information packet with the device to be synchronized, and determining a time offset between the device and the device to be synchronized by using a timestamp of the periodic code block that matches the received and sent time information message;

    The clock of the master count time system is adjusted based on the determined time offset.
14. A clock synchronization device includes:

    a timestamp generating module, configured to generate a timestamp according to a receiving and sending time of the periodic code block on the predetermined channel;

    The determining module is configured to receive and send a time information message with the device to be synchronized, and determine a time offset between the device and the device to be synchronized by using a timestamp of the periodic code block that matches the received and sent time information message. ;

    The adjustment module is configured to adjust the system clock based on the determined time offset.
15. The apparatus of claim 14, wherein the determining module determines the time offset from the device being synchronized by the time stamp of the periodic code block that matches the incoming and outgoing time information message, including:

    The determining module determines, according to T1, T2, T3, T4, TC1, TC2, TC3, TC4, a time offset between the device and the synchronized device;

    The T1 is the timestamp of the previous periodic code block M1 of the header of the received first time information message, and T2 is the previous period of the message header when the first time information message arrives at the device. The timestamp of the code block M2; T3 is the timestamp of the previous periodic code block M3 of the header of the transmitted second time information message; T4 is the device that the second time information message arrives at the synchronized end device Time stamp of the previous periodic code block M4 of the message header;

    TC1 is the time delay between the recording time of the timestamp T1 and the time when the periodic code block M1 issues the device to be synchronized; TC2 is the time between the time when the periodic code block M2 enters the device and the time of recording the timestamp T2. TC3 is the delay between the time of recording of the timestamp T3 and the time when the periodic code block M3 issues the device; TC4 is between the time when the periodic code block M4 enters the device of the synchronized end to the time of recording of the timestamp T4 Delay.
16. The apparatus of claim 14, wherein the adjusting module adjusts the system clock according to the determined time offset comprises:

    The adjusting module adjusts the main time counting system according to the time deviation; according to the main time counting system, obtains a common number from the clock frequency of the time counting system, and creates a common-counter clock with the common number as a clock frequency; The convention number clock is synchronized with the clock of the master time counting system to synchronize the clock of the time counting system with the common number clock.
17. A clock synchronization apparatus is applied to synchronization between a plurality of time counting systems in a device, the plurality of time counting systems being divided into a master time counting system and a slave time counting system; wherein the apparatus comprises:

    Creating a module, configured to obtain a common number according to the clock of the time counting system according to the main time counting system, and create a common-counter clock with the common number as a clock frequency;

    And a synchronization module configured to synchronize the common number clock with a clock of the primary time counting system, and synchronize the clock of the slave time counting system with the common number clock.
18. The apparatus of claim 17 further comprising:

    a timestamp generating module, configured to generate a timestamp according to a receiving and sending time of the periodic code block on the predetermined channel;

    The determining module is configured to receive and send a time information message with the device to be synchronized, and determine a time offset between the device and the device to be synchronized by using a timestamp of the periodic code block that matches the received and sent time information message. ;

    An adjustment module configured to adjust a clock of the primary count time system based on the determined time offset.
19. A computer storage medium storing computer executable instructions; the computer executable instructions being executable to implement the method of any one of claims 1 to 5 or 6 to 8.

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