CN113533815B - Multi-channel sampling synchronization method based on time stamps - Google Patents

Abstract

The invention discloses a multi-channel sampling synchronization method based on timestamps, which comprises the steps of firstly carrying out multi-ADC data synchronization and then carrying out multi-channel sampling synchronization; when the multiple ADC data are synchronized, the FPGA sends a synchronization pulse to the clock manager in three times to respectively complete clock synchronization, data transmission link establishment and timestamp marking, then the FPGA uses a kilomega transceiver to receive serial channel data streams sent by the multiple ADCs and converts the serial channel data streams into parallel data, then the parallel data of each channel is subjected to sequence adjustment and dynamic delay increasing, and finally a final user data stream is formed; when multi-channel sampling is synchronous, the ADC time sequence is adjusted, and then the delay between channels is measured and corrected.

Description

A Timestamp-Based Multi-Channel Sampling Synchronization Method

technical field

The invention belongs to the technical field of digital oscilloscopes, and more particularly, relates to a time stamp-based multi-channel sampling synchronization method.

Background technique

With the continuous improvement of scientific research level, people's demand for high sampling rate oscilloscopes continues to increase. In nuclear energy spectrum measurement, the identification of γ-ray pulse requires a sampling rate of at least 15 MSPS. When observing the surge current on the power transmission line, the duration of the surge is only a few hundred nanoseconds. The time accuracy of the micro-pulse signal of the high-energy accelerator is in Hundreds of picoseconds, in many scientific research scenarios, only a sufficiently high-speed data acquisition system can completely record the signal. Therefore, high-performance oscilloscopes or data acquisition systems have gradually begun to use new GSPSA ADCs (analog-to-digital converters). The biggest feature of this type of ADC is that it has evolved from the original parallel LVDS interface to a serial JESD204B interface. The JESD204B interface offers several benefits over the parallel LVDS interface: greater throughput, fewer transmission lines, smaller device packages, and more. However, when using multiple ADCs to build a high-speed data acquisition system, the data synchronization of multiple ADCs has also become a major problem.

The existing solution is to use the deterministic delay characteristics of the JESD204B protocol to achieve multi-chip synchronization. The JESD204B protocol divides two boundaries for the continuous data flow: frame and multi-frame, and the boundary of the multi-frame clock is determined by the LMFC (local multi-frame clock). At initialization, all channels of the transmitter send ILAS (Initial Channel Alignment Sequence), all channels of the receiver receive ILAS, and each channel contains an elastic buffer, as long as all channels of the receiver receive within the same multiframe boundary

ILAS releases elastic buffers at the same time to achieve channel data alignment. However, in the actual system, the ILAS of each channel often crosses a multi-frame clock boundary. To this end, it is necessary to adjust DTXLFMC (the delay from the effective edge of SYSREF to the LMFC of the receiving end) and DRXLMFC (the delay from the effective edge of SYSREF to the LMFC of the transmitting end) to make each channel ILAS arrives at the same LMFC.

There are three problems with the above method: 1. Adjusting DTXLMFC and DRXLMFC needs to obtain the maximum routing delay, the minimum routing delay, the output delay of the transmitter and the input delay of the receiver. These data are difficult to obtain under normal conditions. 2. For applications such as radar systems, hundreds of converters need to be used, and the computational difficulty increases linearly. 3. For applications that need to adjust the clock phase, adjusting the clock phase will destroy the timing relationship between the SYSREF signal and the device clock, and deterministic delays may cause uncertainty. 4. Only the JESD204B data transmission link can be aligned, and the analog channel cannot be aligned and the asynchrony caused by the sampling clock skew cannot be eliminated.

SUMMARY OF THE INVENTION

The purpose of the present invention is to overcome the deficiencies of the prior art and provide a multi-channel sampling synchronization method based on time stamp, which can not only align multiple JESD204B high-speed serial data links without additional hardware overhead, but also reduce the Channel-to-channel delay due to sample clock skew and analog channel inconsistencies.

In order to achieve the above object of the invention, a method for synchronizing multi-channel sampling based on time stamps of the present invention is characterized in that, it comprises the following steps:

(1), multi-ADC data synchronization;

(1.1), use the crystal oscillator to generate a low-frequency source clock signal and send it to the clock manager of the dual phase-locked loop;

(1.2) FPGA performs register initialization configuration on the clock manager through the SPI communication protocol; after the initialization configuration is completed, the clock manager locks and amplifies the low-frequency source clock signal in two stages, and then generates multi-channel sampling through the internal clock distribution network Clock SCLK and multiple reference clocks REFCLK, where the number of SCLK and REFCLK corresponds to the number of ADCs used by the system, SCLK is sent to each ADC, and REFCLK is sent to FPGA;

(1.3) Each piece of ADC samples the input analog signal under the drive of SCLK, and converts the analog signal into M-bit sampling point data; then, the serial channel mapping unit inside the ADC is the M-bit sampling point Add W bits of redundant control bits to the data to form M+W bits of serial channel data. By default, the value of the redundant control bits is 0;

(1.4), FPGA sends synchronization pulses to the clock manager three times to complete clock synchronization, data transmission link establishment and time stamping respectively;

After the synchronization pulse sent by the FPFA to the clock manager for the first time, the clock distribution network in the clock manager performs a reset operation to align the phases of the multi-channel sampling clock SCLK and the multi-channel reference clock REFCLK; then, the FPGA sends the clock to the clock. The manager sends SPI commands to shield the clock distribution network's response to the synchronization pulse on the one hand, and open the pulse distribution network's response to the synchronization pulse on the other hand. At the same time, the FPGA also sends SPI commands to the ADC to rewrite the ADC's default register data. Disable the default multi-frame clock alignment function in the ADC and turn on the timestamp function;

After the synchronization pulse sent by the FPFA for the second time to the clock manager, the pulse distribution network in the clock manager resets, generates the system reference pulse SYSREF, and feeds it back to the FPGA and all ADCs respectively; when the gigabit transceiver inside the FPGA After the module receives the reference pulse SYSREF, it sets high the SYNCB signal sent by the FPGA to each ADC. When the ADC receives the set SYNCB signal, it starts to transmit the serial channel data stream to the FPGA;

After the synchronization pulse sent by the FPFA for the third time to the clock manager, the pulse distribution network in the clock manager resets again, generates the system reference pulse SYSREF for the second time, and feeds it back to the FPGA and all ADCs respectively; when the ADC receives After the reference pulse SYSREF, mark the first sampling point data after the rising edge of the reference pulse SYSREF, and set a certain position in the redundant control bits of the corresponding serial channel data to 1, and the remaining bits are kept as 0, thus completion timestamp;

(1.5) The FPGA uses a gigabit transceiver to receive the serial channel data stream sent by multiple ADCs, and uses high-speed serial technology to deserialize, reduce the speed and increase the bit width of the serial channel data stream of each channel, and convert it into K channels of parallel data, and extract the data clock DCLK of the parallel data stream through clock recovery technology;

(1.6) Sequence the K channels of parallel data of each channel: check the position where the timestamp mark appears in the parallel data, denoted as L, 1≤L≤K; delay the first to L-1 channels of the original parallel data For two DCLK cycles, the L-th to K-th channels of the original parallel data are delayed by one DCLK cycle to form the delayed parallel data; finally, the delayed parallel data is divided into the L-th channel to the K-th channel, and the 1-th channel to the L-th channel. The order of the -1 channel is rearranged in order to form the parallel data after sequencing;

(1.7) Use multiple FIFOs to add dynamic delays to the parallel data sequenced for each channel. When the sequenced parallel data of a channel is detected to contain a timestamp flag bit "1", the corresponding channel's parallel data will be turned on. Write enable of FIFO; when parallel data after all channels are sequenced are detected to contain timestamp flag bit "1", the read enable of FIFO of all channels is turned on, and the write enable is kept on, and the read and write are kept on. Balance, the parallel data of each channel is dynamically increased with delay to form the final user data stream;

(2), multi-channel sampling synchronization;

(2.1), adjust the ADC timing;

Read back the internal register data of the ADC through the SPI communication protocol, and monitor the SYSREF setup/hold time window register of the ADC. If the readback value of the register is 1, it indicates a timing violation, that is, the valid edge of SYSREF appears in the window of the valid edge of SCLK, and SYSREF does not If the timing conditions of SCLK are met, the corresponding delay value of SYSREF sent to the ADC should be gradually increased until the timing violation is not displayed after re-initialization, that is, the readback value is 0;

(2.2), measure the delay between channels;

(2.2.1), select one channel as the reference channel, and the other channels as the channels to be tested;

(2.2.2) The signal source outputs a sinusoidal signal with a known frequency, and then inputs the sinusoidal signal to the reference channel and the channel to be measured through the power divider and equal-length transmission line;

(2.2.3), use the FPGA debugging tool ILA to collect the user data collected by the reference channel and the channel to be tested in the same time period;

(2.2.4), calculate the phase difference of the collected user data, denoted as θ;

(2.2.5), calculate the inter-channel delay Δt of the channel to be tested relative to the reference channel;

Among them, f is the frequency of the input sinusoidal signal;

(2.3), correct the delay between channels;

Increase the SCLK delay and SYSREF delay of the channel under test step by step, so that the increased delay is as close to the inter-channel delay value Δt as possible, until the absolute value of the difference between the increased delay and the measured inter-channel delay value is smaller than the clock chip Adjustable minimum step of delay;

(2.4) Repeat the above steps (2.1) to (2.3) until the inter-channel delay correction of all channels is completed.

The purpose of the invention of the present invention is achieved in this way:

The multi-channel sampling synchronization method based on the time stamp of the present invention first performs multi-ADC data synchronization, and then multi-channel sampling synchronization; when multi-ADC data is synchronized, the FPGA sends synchronization pulses to the clock manager in three times to complete the clock synchronization, The data transmission link is established and time stamped, and then the FPGA uses the gigabit transceiver to receive the serial channel data stream sent by the multi-chip ADC and convert it into parallel data, and then sequence the parallel data of each channel and increase the dynamic delay, and finally form The final user data stream; when multi-channel sampling is synchronized, the ADC timing is adjusted first, then the inter-channel delay is measured and corrected.

Meanwhile, the multi-channel sampling synchronization method based on timestamp of the present invention also has the following beneficial effects:

(1) By deploying the time stamp function under the JESD204B framework, the alignment of multiple JESD204B high-speed serial data links can be achieved without additional hardware overhead;

(2) Compared with the traditional method of realizing multi-chip synchronization by using the deterministic delay characteristics of the JESD204B protocol, the multi-channel sampling synchronization method based on timestamp breaks through the fact that it can only align the JESD204B data transmission link, and cannot align and align the analog channels. Eliminate the limitation of asynchronous caused by sampling clock skew;

(3) In the multi-ADC data synchronization, the parallel data sequencing technology and the increasing dynamic delay technology are used to efficiently realize the synchronization of multi-sub-module waveform data storage and transmission.

(4) In the multi-channel sampling synchronization, by monitoring the SYSREF setup/hold time window register of the ADC, the delay value of the SYSREF signal sent to the ADC is dynamically increased to ensure that there is no timing violation between the SYSREF signal and the ADC clock signal. Because the existing method will destroy the timing relationship between the SYSREF signal and the device clock when adjusting the clock phase, the deterministic delay may cause the problem of uncertainty.

Description of drawings

1 is an architecture diagram of a specific implementation of a timestamp-based multi-channel sampling synchronization system of the present invention;

2 is an architecture diagram of a specific implementation manner of a clock manager;

Fig. 3 is the structural schematic diagram of serial channel data;

Fig. 4 is a schematic diagram of adding a time stamp to a sample point;

Figure 5 is a schematic diagram of sampling point sequence adjustment;

Figure 6 is a schematic diagram of using FIFO to increase dynamic delay;

Fig. 7 is the data flow chart in FPGA;

Figure 8 is a schematic diagram of the timing violation of the effective edge of SYSREF monitored through the register;

Detailed ways

The specific embodiments of the present invention are described below with reference to the accompanying drawings, so that those skilled in the art can better understand the present invention. It should be noted that, in the following description, when the detailed description of known functions and designs may dilute the main content of the present invention, these descriptions will be omitted here.

Example

FIG. 1 is an architecture diagram of a specific implementation manner of a timestamp-based multi-channel sampling synchronization system according to the present invention.

In this embodiment, a timestamp-based multi-channel sampling synchronization method of the present invention mainly includes two steps of multi-ADC data synchronization and multi-channel sampling synchronization. We will describe each step in detail below, as follows:

S1, multiple ADC data synchronization;

In this embodiment, as shown in Figure 1, we use 4 pieces of ADC (JESD204B interface) with 2.5GSPS sampling rate and 12bits resolution to sample 4 channels of analog signals and then transmit the sampled data to FPGA, then 4 pieces of ADC data The specific process of synchronization is as follows:

S1.1. As shown in Figure 2, use the crystal oscillator to generate a low-frequency source clock signal and send it to the clock chip of the dual phase-locked loop;

S1.2. The FPGA initializes and configures the registers of the clock manager through the SPI communication protocol; after the initialization configuration is completed, the clock manager locks and amplifies the low-frequency source clock signal in two stages, and then generates 4 samples through the internal clock distribution network. Clock SCLK and 4 reference clocks REFCLK, where SCLK is sent to each ADC, and REFCLK is sent to FPGA;

S1.3. Each piece of ADC samples the input analog signal under the drive of SCLK, and converts the analog signal into 12-bit sampling point data; then, add 4 bits to the 12-bit sampling point data through the serial channel mapping unit inside the ADC The redundant control bits of 16-bit form 16-bit serial channel data, as shown in Figure 3. By default, the value of the redundant control bits is 0;

S1.4. The FPGA sends the synchronization pulse to the clock manager three times to complete the clock synchronization, data transmission link establishment and time stamping respectively;

After the synchronization pulse sent by the FPFA to the clock manager for the first time, the clock distribution network in the clock manager performs a reset operation to align the phases of the four sampling clocks SCLK and the four reference clocks REFCLK; then, the FPGA sends the clock to the clock. The manager sends SPI commands to shield the clock distribution network's response to the synchronization pulse on the one hand, and open the pulse distribution network's response to the synchronization pulse on the other hand. At the same time, the FPGA also sends SPI commands to the ADC to rewrite the ADC's default register data. Disable the default multi-frame clock alignment function in the ADC and turn on the timestamp function;

After the synchronization pulse sent by the FPFA for the second time to the clock manager, the pulse distribution network in the clock manager resets, generates the system reference pulse SYSREF, and feeds it back to the FPGA and all ADCs respectively; when the gigabit transceiver inside the FPGA After the module receives the reference pulse SYSREF, it sets high the SYNCB signal sent by the FPGA to each ADC. When the ADC receives the set SYNCB signal, it starts to transmit the serial channel data stream to the FPGA;

After the synchronization pulse sent by the FPFA for the third time to the clock manager, the pulse distribution network in the clock manager resets again, generates the system reference pulse SYSREF for the second time, and feeds it back to the FPGA and all ADCs respectively; when the ADC receives After the reference pulse SYSREF, mark the first sampling point data after the rising edge of the reference pulse SYSREF, and set a certain position in the redundant control bits of the corresponding serial channel data to 1, and the remaining bits are kept as 0, thus Complete the time stamp marking; in this embodiment, the process of adding the time stamp marking bit by the ADC is shown in Figure 4. When the transition of the SYSREF signal from low level to high level is detected, the rising edge of the reference pulse SYSREF is marked. For the first sampling point data after the moment, the highest bit of the 4 control bits is set to 1, and the control bit is 0 at any other time;

S1.5. The FPGA uses a gigabit transceiver to receive the serial channel data stream sent by 4 ADCs, and uses the high-speed serial technology to deserialize, reduce the speed and increase the bit width of the serial channel data stream of each channel, and convert it into 8 channels of parallel data, and extract the data clock DCLK of the parallel data stream through clock recovery technology;

S1.6. Sequence the 8-channel parallel data of each channel: check the position where the time stamp appears in the parallel data, denoted as L, 1≤L≤8; delay the first to L-1 channels of the original parallel data For two DCLK cycles, the Lth to 8th channels of the original parallel data are delayed by one DCLK cycle to form the delayed parallel data; finally, the delayed parallel data is divided into the Lth channel to the 8th channel and the 1st channel to the Lth channel. The order of the -1 channel is rearranged in order to form the parallel data after sequencing;

Due to the limitation of the FPGA clock rate, the sampling data of the ADC must be received and transmitted by reducing the clock rate and increasing the bit width. The data bit width of the single-chip ADC in this system is 12bits, and the clock rate is as high as 2.5GHz. After the FPGA deserializer After the clock rate will be reduced to 312.5MHz, the bit width will be correspondingly increased to 96bits, which means that in the FPGA, one data clock cycle is aligned with 8 sampling points, and the sampling points with timestamp marks may exist in 8 channels. For any channel in the data, first adjust the sequence of each data stream so that the sampling point carrying the time stamp is fixed on the first channel of the 8 channels of data.

The sampling point adjustment sequence is shown in Figure 5. The sampling point sequence adjustment starts after the Timestamp (timestamp signal) is detected to be high, and the sampling point (D4) carrying the timestamp is moved to the original first sampling point. position, the 3 sampling points (D5, D6, D7) after D4 in the same clock cycle and the 4 sampling points (D8, D9, D10, D10) before the next clock cycle complement the remaining 7 sampling points position, when the data is enabled, it can be pulled high.

S1.7. Use multiple FIFOs to add dynamic delay to the sequenced parallel data of each channel. When the sequenced parallel data of a channel is detected to contain the timestamp flag bit "1", the corresponding channel's parallel data will be turned on. Write enable of FIFO; when parallel data after all channels are sequenced are detected to contain timestamp flag bit "1", the read enable of FIFO of all channels is turned on, and the write enable is kept on, and the read and write are kept on. Balance, the parallel data of each channel is dynamically increased with delay to form the final user data stream;

In this embodiment, after the order of the data streams is adjusted, the data of each channel has a phase difference that is an integer multiple of the clock cycle, that is: ΔT=±N*3.2ns, N=1, 2, 3, . . . We can send the sequentially adjusted data stream to a FIFO array, and each piece of ADC data is sent to a FIFO. The write bit width and read bit width of FIFO are consistent, both are 96bits. The write enable of the FIFO is the data valid enable; when it is detected that all FIFOs have data written, all FIFOs turn on the read enable together, the write enable is not closed, and the FIFO maintains a read-write balance of reading while writing. In this way, the fast data will increase the corresponding delay and the slow data will be kept aligned. The process of adding dynamic delay to fast data through FIFO is shown in Figure 6; and the FPGA flow chart of the above sequencing and adding dynamic delay is shown in Figure 7 As shown, the timestamp synchronization mechanism has been configured so far.

S2, multi-channel sampling synchronization;

S2.1, adjust the ADC timing;

Read back the internal register data of the ADC through the SPI communication protocol, and monitor the SYSREF setup/hold time window register of the ADC. If the readback value of the register is 1, it indicates a timing violation, that is, the valid edge of SYSREF appears in the window of the valid edge of SCLK, and SYSREF does not If the timing conditions of SCLK are met, the corresponding SYSREF delay value sent to the ADC should be gradually increased until the timing violation is not displayed after re-initialization, that is, the readback value is 0;

S2.2, measure the delay between channels;

S2.2.1. Select one channel as the reference channel, and the other channels as the channels to be tested;

S2.2.2. The signal source outputs a sinusoidal signal with a known frequency, and then inputs the sinusoidal signal to the reference channel and the channel to be measured through the power divider and equal-length transmission line;

S2.2.3. Use the FPGA debugging tool ILA to collect the user data collected by the reference channel and the channel to be tested in the same time period;

S2.2.4. Calculate the phase difference of the collected user data, denoted as θ;

S2.2.5. Calculate the inter-channel delay Δt of the channel under test relative to the reference channel;

Among them, f is the frequency of the input sinusoidal signal;

S2.3. Correct the delay between channels;

Step by step increase the SCLK delay and SYSREF delay of the channel under test, so that the increased delay amount is as close as possible to the inter-channel delay value Δt measured in step S2.2, until the increased delay amount is absolutely equal to the measured inter-channel delay value The difference between the values is less than the adjustable minimum step of the clock chip delay;

S2.4. Repeat the above steps S2.1 to S2.3 until the inter-channel delay correction of all channels is completed.

In this embodiment, the delay value between multiple ADC channels can be divided into a fixed part and a random part. The random delay comes from the metastable phenomenon caused by the timing violation between the SYSREF signal and the device clock. By adjusting the phase relationship between the SYSREF and the device clock, the metastable state can be avoided to eliminate this part of the random delay; the fixed delay comes from the inconsistent data transmission path. The fixed delay can be reduced to less than a programmable delay value by using the previously deployed timestamp mechanism in conjunction with the delay adjustment described below.

As shown in Figure 7, the ADC used in the embodiment of the present invention contains a monitoring register for the setup time and hold time of SYSREF. If the valid edge of SYSREF appears in the window of the valid edge of CLK, the read value of this register will be 1, warning User SYSREF does not meet the timing conditions of CLK, the window width can be increased to allow more margin. After the clock manager provides a stable clock for the ADC, the SYSREF pulse signal is sent, and the above register value is read back. If the value is 0, no adjustment is necessary; if it is 1, the delay value of the corresponding SYSREF pulse is increased, and then Repeat the above process until the readback value becomes 0. For this embodiment, a sampling clock period is 400ps, and the programmable delay value of the output channel of the clock manager is 25ps, and the adjustable step is 0 to 23. Therefore, an appropriate value can always be found to make the valid edge of SYSREF will not fall within the timing violation window of CLK. The last thing to note is that all ADCs must do this.

After that, a reference channel is determined, and the other channels are the channels to be tested. Input the same signal to measure the phase difference between the reference channel and the channel to be tested. The signal is divided into two parts from a signal source through a power divider, and is connected to the system through an equal-length transmission line; the phase difference measurement method can use the cross-correlation phase difference measurement method, three-parameter sinusoidal fitting or other signal phase differences The measurement algorithm is not discussed in detail here. The calculated result can be expressed by the following formula: Δt=A*T+C*D+M;

Among them, Δt is the calculated inter-channel delay, T is the sampling clock period, D is the programmable delay value of the clock manager, A and C are integers greater than or equal to 0, and m is the delay portion less than D. The meaning of this formula is to divide the inter-channel delay value into A clock cycles, C adjustable minimum steps and the remaining unadjustable delay m parts. Taking the embodiment of the present invention as an example, T=400ps, D=25ps, if Δt is measured to be 736ps, then Δt can be decomposed into: Δt=736ps=1*400ps+13*25ps+11ps; it is the SYSREF signal delay of the lag channel A delay value of T (using a digital delay channel different from D) can advance the lagging signal data by A clock cycles, because the SYSRFF signal moves at an integer multiple of the clock cycle, so no new timing violations will be generated; The SYSREF signal and the CLK signal are delayed by C and D delay values at the same time (not used for the analog delay channel of T), which can advance the delayed data by C*D time value. Because SYSREF and CLK move at the same time, the phase relationship will not change, so it will not change. A timing violation occurs. After the above decomposition, m will always be smaller than D, which is 25ps for this embodiment.

Although the illustrative specific embodiments of the present invention have been described above to facilitate the understanding of the present invention by those skilled in the art, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, As long as various changes are within the spirit and scope of the present invention as defined and determined by the appended claims, these changes are obvious, and all inventions and creations utilizing the inventive concept are included in the protection list.

Claims (1)

1. a multi-channel sampling synchronization method based on time stamp, is characterized in that, comprises the following steps: (1), multi-ADC data synchronization; (1.1), use the crystal oscillator to generate a low-frequency source clock signal and send it to the clock manager of the dual phase-locked loop; (1.2) FPGA performs register initialization configuration on the clock manager through the SPI communication protocol; after the initialization configuration is completed, the clock manager locks and amplifies the low-frequency source clock signal in two stages, and then generates multi-channel sampling through the internal clock distribution network Clock SCLK and multiple reference clocks REFCLK, where the number of SCLK and REFCLK corresponds to the number of ADCs used by the system, SCLK is sent to each ADC, and REFCLK is sent to FPGA; (1.3) Each piece of ADC samples the input analog signal under the drive of SCLK, and converts the analog signal into M-bit sampling point data; then, the serial channel mapping unit inside the ADC is the M-bit sampling point Add W bits of redundant control bits to the data to form M+W bits of serial channel data. By default, the value of the redundant control bits is 0; (1.4), FPGA sends synchronization pulses to the clock manager three times to complete clock synchronization, data transmission link establishment and time stamping respectively; After the synchronization pulse sent by the FPFA to the clock manager for the first time, the clock distribution network in the clock manager performs a reset operation to align the phases of the multi-channel sampling clock SCLK and the multi-channel reference clock REFCLK; then, the FPGA sends the clock to the clock. The manager sends SPI commands to shield the clock distribution network's response to the synchronization pulse on the one hand, and open the pulse distribution network's response to the synchronization pulse on the other hand. At the same time, the FPGA also sends SPI commands to the ADC to rewrite the ADC's default register data. Disable the default multi-frame clock alignment function in the ADC and turn on the timestamp function; After the synchronization pulse sent by the FPFA for the second time to the clock manager, the pulse distribution network in the clock manager resets, generates the system reference pulse SYSREF, and feeds it back to the FPGA and all ADCs respectively; when the gigabit transceiver inside the FPGA After the module receives the reference pulse SYSREF, it sets high the SYNCB signal sent by the FPGA to each ADC. When the ADC receives the set SYNCB signal, it starts to transmit the serial channel data stream to the FPGA; After the synchronization pulse sent by the FPFA for the third time to the clock manager, the pulse distribution network in the clock manager resets again, generates the system reference pulse SYSREF for the second time, and feeds it back to the FPGA and all ADCs respectively; when the ADC receives After the reference pulse SYSREF, mark the first sampling point data after the rising edge of the reference pulse SYSREF, and set a certain position in the redundant control bits of the corresponding serial channel data to 1, and the remaining bits are kept as 0, thus completion timestamp; (1.5) The FPGA uses a gigabit transceiver to receive the serial channel data stream sent by multiple ADCs, and uses high-speed serial technology to deserialize, reduce the speed and increase the bit width of the serial channel data stream of each channel, and convert it into K channels of parallel data, and extract the data clock DCLK of the parallel data stream through clock recovery technology; (1.6) Sequence the K channels of parallel data of each channel: check the position where the timestamp mark appears in the parallel data, denoted as L, 1≤L≤K; delay the first to L-1 channels of the original parallel data For two DCLK cycles, the L-th to K-th channels of the original parallel data are delayed by one DCLK cycle to form the delayed parallel data; finally, the delayed parallel data is divided into the L-th channel to the K-th channel, and the 1-th channel to the L-th channel. The order of the -1 channel is rearranged in order to form the parallel data after sequencing; (1.7) Use multiple FIFOs to add dynamic delays to the parallel data sequenced for each channel. When the sequenced parallel data of a channel is detected to contain a timestamp flag bit "1", the corresponding channel's parallel data will be turned on. Write enable of FIFO; when parallel data after all channels are sequenced are detected to contain timestamp flag bit "1", the read enable of FIFO of all channels is turned on, and the write enable is kept on, and the read and write are kept on. Balance, the parallel data of each channel is dynamically increased with delay to form the final user data stream; (2), multi-channel sampling synchronization; (2.1), adjust the ADC timing; Read back the internal register data of the ADC through the SPI communication protocol, and monitor the SYSREF setup/hold time window register of the ADC. If the readback value of the register is 1, it indicates a timing violation, that is, the valid edge of SYSREF appears in the window of the valid edge of SCLK, and SYSREF does not If the timing conditions of SCLK are met, the corresponding SYSREF delay value sent to the ADC should be gradually increased until the timing violation is not displayed after re-initialization, that is, the readback value is 0; (2.2), measure the delay between channels; (2.2.1), select one channel as the reference channel, and the other channels as the channels to be tested; (2.2.2) The signal source outputs a sinusoidal signal with a known frequency, and then inputs the sinusoidal signal to the reference channel and the channel to be measured through the power divider and equal-length transmission line; (2.2.3), use the FPGA debugging tool ILA to collect the user data collected by the reference channel and the channel to be tested in the same time period; (2.2.4), calculate the phase difference of the collected user data, denoted as θ; (2.2.5), calculate the inter-channel delay Δt of the channel to be tested relative to the reference channel;

Among them, f is the frequency of the input sinusoidal signal; (2.3), correct the delay between channels; Increase the SCLK delay and SYSREF delay of the channel under test step by step, so that the added delay is as close as possible to the inter-channel delay value Δt, until the absolute value of the difference between the increased delay and the measured inter-channel delay value is smaller than the clock management Adjustable minimum steps for the delay of the controller; (2.4) Repeat the above steps (2.1) to (2.3) until the inter-channel delay correction of all channels is completed.

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