CN117614421B - Multichannel pulse synchronization method and electronic equipment - Google Patents
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
- H03K5/1506—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
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- H—ELECTRICITY
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- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
Abstract
The invention discloses a multichannel pulse synchronization method and electronic equipment. The method comprises the following steps: acquiring design pulse time sequences of a plurality of channels, and acquiring delay differences of level control switches of the channels and overall delay differences between overall delay of the channels and minimum overall delay, wherein the minimum overall delay is the overall delay of the channel with the shortest overall delay; for each channel, controlling the switch delay difference and the design pulse time sequence according to the level of the channel to obtain a switch delay compensation sequence of the channel, and controlling the switch delay difference, the overall delay difference and the design pulse time sequence according to the level of the channel to obtain a door pocket delay sequence of the channel; and adjusting the corresponding switch delay compensation sequence according to the gate pocket delay sequence so as to enable the channels to synchronously play the pulse time sequence. The method can reduce cost and improve reliability.
Description
Technical Field
The present invention relates to the field of pulse signals, and in particular, to a multi-channel pulse synchronization method and an electronic device.
Background
In the apparatus and equipment related to complex pulse time sequence signals such as a quantum computer and a magnetic resonance detection apparatus, a plurality of modules working cooperatively are respectively provided with a signal channel, and in order to ensure synchronous playing of multi-channel pulse time sequence signals, delay compensation units are usually required to be arranged in each channel in the related art. However, in the case of a large number of channels, such as 12 channels, 20 channels, or even more channels, if a delay compensation unit is provided in each channel, cost saving and improvement of reliability are not facilitated.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems in the related art to some extent. To this end, a first object of the present invention is to propose a multi-channel pulse synchronization method to save costs and improve reliability.
A second object of the invention is to propose an electronic device.
To achieve the above object, an embodiment of a first aspect of the present invention provides a multi-channel pulse synchronization method, including: acquiring design pulse time sequences of a plurality of channels, and acquiring delay difference of a level control switch of each channel and overall delay difference between overall delay of each channel and minimum overall delay, wherein the minimum overall delay is the overall delay of the channel with the shortest overall delay; for each channel, controlling the switch delay difference and the design pulse time sequence according to the level of the channel to obtain a switch delay compensation sequence of the channel, and controlling the switch delay difference, the overall delay difference and the design pulse time sequence according to the level of the channel to obtain a door pocket delay sequence of the channel; and adjusting a corresponding switch delay compensation sequence according to the gate pocket delay sequence so as to enable the channels to synchronously play pulse time sequences.
To achieve the above object, an embodiment of a second aspect of the present invention provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, where the computer program is executed by the processor to implement the above-mentioned multi-channel pulse synchronization method.
According to the multi-channel pulse synchronization method and the electronic device, the design pulse time sequence of a plurality of channels is obtained, the delay difference of the level control switch of each channel and the integral delay difference between the integral delay of each channel and the minimum integral delay are obtained, wherein the minimum integral delay is the integral delay of the channel with the shortest integral delay, the switch delay compensation sequence of each channel is obtained according to the level control switch delay difference and the design pulse time sequence of the channel, the door pocket delay sequence of the channel is obtained according to the level control switch delay difference, the integral delay difference and the design pulse time sequence of the channel, and the corresponding switch delay compensation sequence is adjusted according to the door pocket delay sequence, so that the plurality of channels synchronously play the pulse time sequence, different integral delays of different channels are avoided, the plurality of channels can synchronously play the pulse time sequence without setting a delay compensation unit, the cost is saved, and the reliability is improved.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
FIG. 1 is a schematic diagram of an exemplary multi-channel pulse;
FIG. 2 is a flow diagram of a multi-pulse synchronization method in accordance with one or more embodiments of the invention;
FIG. 3 is a schematic diagram of an exemplary multi-channel pulse of the present invention;
fig. 4 is a schematic diagram of a multi-channel pulse of another example of the invention.
Detailed Description
The multi-channel pulse synchronization method, the electronic device of the embodiments of the present invention are described below with reference to the drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described with reference to the drawings are exemplary and should not be construed as limiting the invention.
The playing of pulse time sequence signals of all channels is asynchronous, and two main influencing factors are: firstly, the integral delay of the channel is different due to the difference of the characteristics of signal wires and signal devices in the channel; and secondly, the actual execution result of the pulse time sequence is deviated and accumulated on the integral delay of the channel due to the different delay between the high level to low level and the low level to high level of the level control unit of the pulse generating circuit in each channel. Referring specifically to the example shown in fig. 1, two channels are provided: AWG (American Wire Gauge ) channels and DAQ (Data Acquisition) channels. In fig. 1, timings 1 and 3 are the positions and lengths where the high level is theoretically located, taking the overall delay of the channel into consideration. The time sequence 2 and the time sequence 4 are the positions and the lengths of the high level after considering the integral delay of the channel, namely the execution time sequence corresponding to the design pulse time sequence. The level control switch delay of the level control unit comprises a first delay and a second delay, wherein the first delay is the delay when the level control switch control pulse is converted from a low level to a high level, and the second delay is the delay when the level control switch control pulse is converted from the high level to the low level. As can be seen from the AWG design timing and the AWG execution timing in fig. 1, which correspond to the design pulse timing of the AWG channel, the overall delay of the AWG channel is a, the first delay is b, and the second delay is c. As can be seen from the DAQ design timing and the DAQ execution timing corresponding to the design pulse timing of the DAQ channel in fig. 1, the overall delay of the DAQ channel is a ', the first delay is b ', and the second delay is c '. As is apparent from fig. 1, the delay of the level control switches for controlling the high-low level transition of the pulse timing signal in the AWG channel and the DAQ channel is different, so that the actual lengths of the high-low level of the pulse timing signal are not identical to the design, and the overall length of the execution timing pulse signal is also deviated.
Moreover, the above-mentioned overall delay, first delay and second delay generally need to be obtained by measurement, and the measurement method and measurement circuit involved in the overall delay of each channel and the delay of the level control switch are complex.
Thus, the present invention proposes a multi-channel pulse synchronization method.
Fig. 2 is a flow diagram of a multi-channel pulse synchronization method in accordance with one or more embodiments of the invention.
As shown in fig. 2, the multi-channel pulse synchronization method includes:
s21, acquiring design pulse time sequences of a plurality of channels, and acquiring delay differences of level control switches of the channels and overall delay differences between overall delay of the channels and minimum overall delay, wherein the minimum overall delay is the overall delay of the channel with the shortest overall delay.
S22, for each channel, controlling the switch delay difference and the design pulse time sequence according to the level of the channel to obtain a switch delay compensation sequence of the channel, and controlling the switch delay difference, the integral delay difference and the design pulse time sequence according to the level of the channel to obtain a door pocket delay sequence of the channel.
S23, adjusting a corresponding switch delay compensation sequence according to the gate pocket delay sequence so as to enable the channels to synchronously play the pulse time sequence.
Therefore, the design pulse time sequence of a plurality of channels is obtained, the delay difference of the level control switch of each channel and the integral delay difference between the integral delay of each channel and the minimum integral delay are obtained, wherein the minimum integral delay is the integral delay of the channel with the shortest integral delay, the switch delay compensation sequence of each channel is obtained according to the level control switch delay difference and the design pulse time sequence of the channel, the door pocket delay sequence of the channel is obtained according to the level control switch delay difference, the integral delay difference and the design pulse time sequence of the channel, and the corresponding switch delay compensation sequence is adjusted according to the door pocket delay sequence, so that the plurality of channels synchronously play the pulse time sequence, different integral delays are avoided, the plurality of channels can synchronously play the pulse time sequence without setting a delay compensation unit, the cost is saved, and the reliability is improved. In addition, the real values of the integral delay, the first delay and the second delay do not need to be measured, and the structure and the debugging workload of the measuring circuit are greatly reduced.
In one or more embodiments of the present invention, obtaining a level control switch delay difference for each channel includes: generating a first test pulse time sequence, and obtaining a plurality of second test pulse time sequences according to the first test pulse time sequence, wherein the plurality of second test pulse time sequences are time sequences obtained by inputting the first test pulse time sequences into a plurality of channels; acquiring a first high-level pulse width of a preset high level in a first test pulse time sequence, and acquiring a second high-level pulse width of the preset high level for each second test pulse time sequence; and subtracting a second high-level pulse width corresponding to the channel from the first high-level pulse width for each channel to obtain the level control switch delay difference of the channel.
Specifically, the upper computer outputs the first test pulse time sequence to a plurality of channels, and as the pulse time sequences output by all the channels are connected to the multichannel oscilloscope, the second test pulse time sequence can be obtained according to the first test pulse time sequence after the multichannel oscilloscope inputs the channels. It should be noted that, the test pulse timing of all channels need not be exactly the same, but the high level pulse width and the position of the test pulse timing of all channels need not be guaranteed to be the same.
The multichannel oscilloscope displays and records the second test pulse time sequence output by all channels executing the first test pulse time sequence.
For each channel, a high-level pulse width of a first test pulse time sequence is obtained to obtain a first high-level pulse width D, and a high-level pulse width of a second test pulse time sequence corresponding to the channel is obtained to obtain a second high-level pulse width D ', so that a level control switch delay difference delta=D-D' of the channel is obtained.
In one or more embodiments of the present invention, obtaining an overall delay difference between an overall delay of each channel and a minimum overall delay includes: aiming at each channel, processing a second test pulse time sequence corresponding to the channel by adopting the level control opening Guan Yan time difference of the channel to obtain a third test pulse time sequence, and obtaining the integral delay of the channel according to the third test pulse time sequence; taking the minimum value in the plurality of overall delays as the minimum overall delay; subtracting the minimum overall delay from the overall delay to obtain an overall delay difference.
Specifically, after the delay difference of the level control switch of each channel is obtained, the delay difference of the level control switch of each channel is adopted for processing aiming at the second test pulse time sequence corresponding to each channel, so as to obtain a third test pulse time sequence.
After the third test pulse time sequence is obtained, the overall delay of the channel can be obtained according to the third test pulse time sequence. The method for obtaining the overall delay may be selecting a reference object, and obtaining the overall delay of the channel according to the position of the reference object in the first test pulse time sequence and the third test pulse time sequence. Taking the reference object as a high-level rising edge as an example, firstly selecting a high level from a first test pulse time sequence, acquiring the high-level rising edge position, inputting the first test pulse time sequence into a channel to acquire a second test pulse time sequence, adjusting the second test pulse time sequence to acquire a third test pulse time sequence, acquiring the high-level rising edge position of the selected high level in the third test pulse time sequence, and calculating to acquire the distance between the two high-level rising edge positions to acquire the integral delay of the channel.
After the overall delay is obtained for each channel, the minimum overall delay is obtained, and if the channel corresponding to the minimum overall delay is the first channel and one of the other channels is the second channel, the difference between the overall delay of the second channel and the minimum overall delay is the overall delay difference of the second channel.
The following is a detailed description with reference to the example shown in fig. 3.
In the example shown in fig. 3, the upper computer outputs the first test pulse timing to channel 1, channel 2, channel 3, channel 4, and displays the pulse timing of the input channel through the oscilloscope. In fig. 3, symbol 1 represents a second test pulse timing corresponding to the channel, and symbol 2 represents a third test pulse timing corresponding to the channel.
As can be seen from fig. 3, the overall delay of the channel 4 is the shortest, that is, the overall delay of the channel 4 is the shortest overall delay, so as to calculate the difference between the overall delays of the channel 1, the channel 2, the channel 3 and the overall delay of the channel 4, obtain the overall delay differences corresponding to the channel 1, the channel 2 and the channel 3, and the overall delay difference corresponding to the channel 1 is the maximum overall delay difference.
The overall delay difference corresponding to the channel 1 is the maximum overall delay difference Lf, the overall delay difference corresponding to the channel 2 is L2, and the overall delay difference corresponding to the channel 3 is L3.
In one or more embodiments of the present invention, the processing of the second test pulse timing corresponding to the channel by using the level control opening Guan Yan time difference of the channel to obtain the third test pulse timing includes: and when the delay difference of the level control switch is smaller than zero, delaying the high-level rising edge of the second test pulse time sequence by a first preset value, and taking the delayed second test pulse time sequence as a third test pulse time sequence. And when the delay difference of the level control switch is larger than zero, delaying the high-level falling edge of the second test pulse time sequence by a second preset value, and taking the delayed second test pulse time sequence as a third test pulse time sequence. The first preset value is equal to the absolute value of the delay difference of the level control switch, and the second preset value is equal to the delay difference of the level control switch, that is, if delta is negative, the high-level rising edge in the pulse time sequence recorded by the oscilloscope is delayed by delta; if delta is positive, the high level rising edge in the pulse sequence recorded by the oscilloscope is unchanged, and the falling edge is delayed by delta.
In one or more embodiments of the present invention, a switching delay compensation sequence of the channel is obtained according to a level control switching delay difference and a design pulse timing of the channel, including: when the delay difference of the level control switch is larger than zero, extending the high-level pulse width of the designed pulse time sequence by a third preset value to obtain a switch delay compensation sequence of the channel; and when the delay difference of the level control switch is smaller than zero, shortening the high-level pulse width of the designed pulse time sequence by a fourth preset value to obtain a switch delay compensation sequence of the channel.
The third preset value is equal to the delay difference of the level control switch, and the fourth preset value is equal to the absolute value of the delay difference of the level control switch.
The description continues with the example shown in fig. 1.
Specifically, for AWG channels, the level control switch delay difference is equal to the difference between b and c, i.e., if the level control switch delay difference is greater than zero, b > c is indicated, and if the level control switch delay difference is less than zero, b < c is indicated. If b > c, delta is positive, the high-level pulse width of each AWG channel is extended by delta, and if b < c, delta is negative, and the high-level pulse width of each AWG channel is shortened by delta. The extension Δ or shortening Δ may be the adjustment of the rising edge position of all the high levels, or the adjustment of the falling edge position of all the high levels.
The high-level rising edge position is preferably selected and adjusted if the high-level pulse width needs to be extended, and the high-level rising edge position is preferably selected and adjusted if the high-level pulse width needs to be shortened, so that the rising edge or the falling edge of the high-level pulse time sequence of each AWG design pulse is only required to be delayed, the superposition of a preset sequence is not required, and the processing method is simple and convenient. And after the pulse width of the high level of the designed pulse time sequence is adjusted, forming a switch delay compensation sequence.
In one or more embodiments of the present invention, a gate pocket delay sequence of the channel is obtained according to a level control switch delay difference, an overall delay difference, and a design pulse timing sequence of the channel, including: and obtaining the total time sequence length of the channel according to the time sequence information of the level control switch time delay difference, the overall time delay difference and the design pulse time sequence, wherein the time sequence information comprises the number of high levels of the design pulse time sequence and a preset interval, and the preset interval is the interval between the leading edge of the design pulse time sequence and the falling edge of the last high level.
After the corresponding total time sequence length is obtained for a plurality of channels, the delay sequence of the door pocket of the channel is obtained according to the level control switch delay difference, the overall delay difference and the design pulse time sequence of the channel, and the method further comprises the following steps: acquiring the longest time sequence total length and the shortest time sequence total length in a plurality of time sequence total lengths; obtaining a reference length according to the longest time sequence total length and the shortest time sequence total length; and obtaining a gate pocket delay sequence of the channel according to the reference length, the shortest time sequence total length, the time sequence total length of the channel and the overall delay difference.
Wherein, calculate and get the time sequence total length according to the following formula:
M1=Lf-L1+d+Δ*n，
wherein M1 is the total time sequence length, lf is the maximum overall delay difference, L1 is the overall delay difference of the channel, d is the preset interval, delta is the delay difference of the level control switch, and n is the number of high levels.
Obtaining a door pocket delay sequence of the channel according to the reference length, the shortest time sequence total length, the time sequence total length of the channel and the overall delay difference, wherein the door pocket delay sequence comprises the following steps: obtaining the signal length of the front-end door pocket according to the integral delay time difference of the channel, and obtaining the signal length of the rear-end door pocket according to the reference length, the shortest time sequence total length and the time sequence total length of the channel; generating a front door pocket sequence according to the front door pocket signal length, and generating a rear door pocket sequence according to the rear door pocket signal length; the front door pocket sequence and the back door pocket sequence are used as door pocket delay sequences of the channel.
And calculating to obtain the signal length of the rear door pocket according to the following steps:
M2=M min +Lb-M1，
wherein M2 is the signal length of the rear door pocket, M min Lb is the total length of the shortest time sequenceThe reference length, M1, is the total time sequence length of the channel.
The description will be continued taking the AWG channel shown in fig. 1 as an example.
The method for generating the gate pocket delay sequence of the AWG channel comprises the following steps:
s1, if delta is negative, delaying a high-level rising edge in an AWG channel pulse time sequence signal recorded by an oscilloscope by delta; if delta is positive, the high level rising edge in the AWG channel pulse sequence signal is unchanged; and processing the high-level rising edge in the pulse time sequence signals of the rest channels recorded by the oscilloscope according to the method.
S2, obtaining the maximum overall delay time Lf of the high-level rising edge in each channel according to the high-level rising edge positions in all the channel pulse time sequence signals processed in the S1.
And S3, the time difference between the high-level rising edge in the AWG channel and the high-level rising edge in the channel with the shortest delay is L1, and the signal length of the front end gate sleeve of the AWG channel is Lf-L1.
And S4, the number of high levels in the AWG channel design time sequence is n, the interval from the front edge of the design time sequence signal to the falling edge of the last high level is d, and the total length of the time sequence is M1=Lf-L1+d+delta x n.
S5, determining the reference length Lb of the rear-end gate sleeve signal, wherein Lb is greater than or equal to the longest generating time sequence total length M in each channel max And shortest generation time sequence total length M min Lb is equal to or greater than the longest generation timing total length M in each channel max And shortest generation time sequence total length M min Any value of the difference of (c).
S6, the signal length of the rear end door pocket of the AWG channel is M min +Lb-M1。
S7, generating a gate pocket delay sequence for each channel according to the front gate pocket signal length and the rear gate pocket signal length of each channel.
The AWG channel is illustrated as an example.
Referring to fig. 4, after the design pulse timing is generated, gate cover signals are added to the front and rear ends of the design pulse timing, and each high level of the design pulse timing is adjusted. Specifically, the difference delta between b and c is determined first, if b > c, delta is positive, i.e. the high level pulse width of each AWG channel is extended by delta, and if b < c, delta is negative, i.e. the high level pulse width of each AWG channel is shortened by delta. The extension delta or shortening delta can be the adjustment of all high-level rising edge positions, the adjustment of all high-level falling edge positions, the preferential adjustment of high-level falling edge positions if the high-level pulse width needs to be extended, and the preferential adjustment of high-level rising edge positions if the high-level pulse width needs to be shortened, so that only the time delay is needed for the high-level rising edge or the falling edge of each design pulse time sequence, the superposition of preset sequences is not needed, and the processing method is simple and convenient.
And after the pulse width of the high level of the pulse time sequence designed by the AWG is adjusted, forming a switch delay compensation sequence. According to the gate pocket delay sequence, a front gate pocket sequence (low level signal) is added at the front end of the switch delay compensation sequence, and a rear gate pocket sequence (low level signal) is added at the rear end of the switch delay compensation sequence, so that the switch delay compensation sequence is adjusted according to the gate pocket delay sequence.
By increasing the gate pocket delay sequence and adjusting the high level, the design pulse timing is adjusted from the design timing shown in fig. 4 to the generation timing shown in fig. 4, and then the design pulse timing is input to the corresponding channel, resulting in the execution timing shown in fig. 4.
By setting the door pocket delay sequence, the problem of different overall delays is solved, namely, the lengths of front-end door pocket signals are set to be L1 and L2, so that L1+a=L2+a'; the back-end gate sleeve signal is arranged to cause the generation timings of the AWG channel and the DAQ channel to have the same length as a whole. By adjusting the high-level pulse width, the practical high-level and low-level length of the pulse time sequence is consistent with the design.
It is well understood that 12 channels or 20 channels, or even other numbers of channels, can be correspondingly expanded in application according to the above-described method.
In summary, the multi-channel pulse synchronization method of the embodiment of the invention obtains the design pulse time sequence of a plurality of channels, obtains the delay difference of the level control switch of each channel and the integral delay difference between the integral delay of each channel and the minimum integral delay, wherein the minimum integral delay is the integral delay of the channel with the shortest integral delay, obtains the switch delay compensation sequence of each channel according to the delay difference of the level control switch of the channel and the design pulse time sequence, obtains the door pocket delay sequence of the channel according to the delay difference of the level control switch of the channel, the integral delay difference and the design pulse time sequence, and adjusts the corresponding switch delay compensation sequence according to the door pocket delay sequence, so that the plurality of channels synchronously play the pulse time sequence, thereby avoiding different integral delays of different channels, enabling the plurality of channels to synchronously play the pulse time sequence without setting a delay compensation unit, saving cost and improving reliability. By setting the front door pocket signal, the problem of different overall delays is solved; the back-end gate sleeve signal is arranged to cause the generation timings of the AWG channel and the DAQ channel to have the same length as a whole. By adjusting the high-level pulse width, the practical high-level and low-level length of the pulse time sequence signal is consistent with the design. Moreover, the overall delay, the first delay, and the second delay need not be obtained by means of measurement.
Further, the invention provides electronic equipment.
In an embodiment of the present invention, an electronic device includes a memory, a processor, and a computer program stored on the memory and executable on the processor, where the computer program, when executed by the processor, implements the above-described multi-channel pulse synchronization method.
According to the electronic equipment, through the multi-channel pulse synchronization method, the design pulse time sequence of the channels is obtained, the delay difference of the level control switch of each channel and the integral delay difference between the integral delay of each channel and the minimum integral delay are obtained, wherein the minimum integral delay is the integral delay of the channel with the shortest integral delay, the switch delay compensation sequence of the channel is obtained according to the level control switch delay difference and the design pulse time sequence of each channel, the door pocket delay sequence of the channel is obtained according to the level control switch delay difference, the integral delay difference and the design pulse time sequence of the channel, and the corresponding switch delay compensation sequence is adjusted according to the door pocket delay sequence, so that the channels can synchronously play the pulse time sequence, different integral delays of different channels are avoided, the channels can synchronously play the pulse time sequence without setting a delay compensation unit, the cost is saved, and the reliability is improved. By setting the front door pocket signal, the problem of different overall delays is solved; the back-end gate sleeve signal is arranged to cause the generation timings of the AWG channel and the DAQ channel to have the same length as a whole. By adjusting the high-level pulse width, the practical high-level and low-level length of the pulse time sequence signal is consistent with the design. Moreover, the overall delay, the first delay, and the second delay need not be obtained by means of measurement.
It should be noted that the logic and/or steps represented in the flow diagrams or otherwise described herein may be considered a ordered listing of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer readable medium may even be paper or other suitable medium on which the program is printed, as the program may be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.
It is to be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
In the description of the present specification, the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. refer to an orientation or positional relationship based on that shown in the drawings, and do not indicate or imply that the apparatus or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and should not be construed as limiting the invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
In the description of the present specification, unless otherwise indicated, the terms "mounted," "connected," "secured," and the like are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present invention, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.
Claims (4)
1. A method of multi-channel pulse synchronization, the method comprising:
acquiring design pulse time sequences of a plurality of channels, and acquiring delay difference of a level control switch of each channel and overall delay difference between overall delay of each channel and minimum overall delay, wherein the minimum overall delay is the overall delay of the channel with the shortest overall delay;
for each channel, controlling the switch delay difference and the design pulse time sequence according to the level of the channel to obtain a switch delay compensation sequence of the channel, and controlling the switch delay difference, the overall delay difference and the design pulse time sequence according to the level of the channel to obtain a door pocket delay sequence of the channel;
adjusting a corresponding switch delay compensation sequence according to the gate pocket delay sequence so as to enable a plurality of channels to synchronously play pulse time sequences;
the step of obtaining the delay difference of the level control switch of each channel comprises the following steps:
generating a first test pulse time sequence, and obtaining a plurality of second test pulse time sequences according to the first test pulse time sequence, wherein the plurality of second test pulse time sequences are time sequences obtained by inputting the first test pulse time sequences into a plurality of channels;
acquiring a first high-level pulse width of a preset high level in the first test pulse time sequence, and acquiring a second high-level pulse width of the preset high level for each second test pulse time sequence;
subtracting a second high-level pulse width corresponding to the channel from the first high-level pulse width for each channel to obtain a level control switch delay difference of the channel;
the step of controlling the switch delay difference and the design pulse time sequence according to the level of the channel to obtain the switch delay compensation sequence of the channel comprises the following steps:
when the delay difference of the level control switch is larger than zero, extending the high-level pulse width of the design pulse time sequence by a third preset value to obtain a switch delay compensation sequence of the channel;
when the delay difference of the level control switch is smaller than zero, shortening the high-level pulse width of the design pulse time sequence by a fourth preset value to obtain a switch delay compensation sequence of the channel;
the gate pocket delay sequence of the channel is obtained according to the level control switch delay difference, the overall delay difference and the design pulse time sequence of the channel, and the gate pocket delay sequence comprises the following steps:
obtaining the total time sequence length of the channel according to the level control switch delay difference, the overall delay difference and the time sequence information of the design pulse time sequence, wherein the time sequence information comprises the number of high levels of the design pulse time sequence and a preset interval, and the preset interval is the interval between the leading edge of the design pulse time sequence and the falling edge of the last high level;
after the corresponding total time sequence length is obtained for a plurality of channels, the gate pocket delay sequence of the channel is obtained according to the level control switch delay difference, the overall delay difference and the design pulse time sequence of the channel, and the gate pocket delay sequence further comprises:
acquiring the longest time sequence total length and the shortest time sequence total length in a plurality of time sequence total lengths;
obtaining a reference length according to the longest time sequence total length and the shortest time sequence total length;
obtaining a door pocket delay sequence of the channel according to the reference length, the shortest time sequence total length, the time sequence total length of the channel and the overall delay difference;
the total length of the time sequence is calculated according to the following formula:
M1=Lf-L1+d+Δ*n，
wherein M1 is the total length of the time sequence, lf is the maximum overall delay difference, L1 is the overall delay difference of the channel, d is the preset interval, Δ is the delay difference of the level control switch, and n is the number of high levels;
the obtaining the door pocket delay sequence of the channel according to the reference length, the shortest time sequence total length, the time sequence total length of the channel and the overall delay difference comprises the following steps:
obtaining the signal length of the front-end door pocket according to the integral delay time difference of the channel, and obtaining the signal length of the rear-end door pocket according to the reference length, the shortest time sequence total length and the time sequence total length of the channel;
generating a front-end door pocket sequence according to the front-end door pocket signal length, and generating a rear-end door pocket sequence according to the rear-end door pocket signal length;
taking the front door pocket sequence and the rear door pocket sequence as door pocket delay sequences of the channel;
and calculating the signal length of the rear door pocket according to the following steps:
M2=M min +Lb-M1，
wherein M2 is the signal length of the rear door pocket, M min For the shortest total length of the time sequence, lb is the reference length, M1 is the total length of the time sequence of the channel;
the obtaining a reference length according to the longest time sequence total length and the shortest time sequence total length includes:
calculating to obtain a difference value between the longest time sequence total length and the shortest time sequence total length;
setting the reference length to be any value greater than or equal to the difference value;
the method for obtaining the front door pocket signal length according to the integral delay difference of the channel comprises the following steps:
and taking the difference between the maximum integral delay difference and the integral delay difference of the channel as the front-end door pocket signal length.
2. The method of claim 1, wherein obtaining the overall delay difference between the overall delay of each of the channels and the minimum overall delay comprises:
aiming at each channel, processing a second test pulse time sequence corresponding to the channel by adopting a level control switch time delay difference of the channel to obtain a third test pulse time sequence, and obtaining the overall time delay of the channel according to the third test pulse time sequence;
taking the minimum value of the plurality of integral delays as the minimum integral delay;
subtracting the minimum overall delay from the overall delay to obtain the overall delay difference.
3. The multi-channel pulse synchronization method according to claim 2, wherein the processing the second test pulse timing sequence corresponding to the channel by using the level control switch delay difference of the channel to obtain a third test pulse timing sequence includes:
when the delay difference of the level control switch is smaller than zero, delaying the high-level rising edge of the second test pulse time sequence by a first preset value, and taking the delayed second test pulse time sequence as the third test pulse time sequence;
and when the delay difference of the level control switch is larger than zero, delaying the high-level falling edge of the second test pulse time sequence by a second preset value, and taking the delayed second test pulse time sequence as the third test pulse time sequence.
4. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, which when executed by the processor, implements the multi-channel pulse synchronization method of any one of claims 1-3.
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