CN117879548A - Multichannel pulse synchronization method, device and system and electronic equipment - Google Patents

Abstract

The invention discloses a multichannel pulse synchronization method, a multichannel pulse synchronization device, a multichannel pulse synchronization system and electronic equipment. The method comprises the following steps: acquiring design pulse time sequences of a plurality of channels, and overall delay, level control on-delay and level control Guan Yanshi of each channel; generating a gate pocket delay sequence for each channel according to the plurality of overall delays, the plurality of level control on-delays, and the plurality of level control Guan Yan; and adjusting the corresponding design pulse time sequence according to the gate pocket delay sequence so as to enable the channels to synchronously play the pulse time sequence. The method can reduce the cost and improve the reliability of the system.

Description

Multichannel pulse synchronization method, device and system and electronic equipment

Technical Field

The present invention relates to the field of pulse signal technologies, and in particular, to a method, an apparatus, a system, and an electronic device for multi-channel pulse synchronization.

Background

In the apparatus and equipment related to complex pulse time sequence signals such as a quantum computer and a magnetic resonance detection apparatus, a plurality of modules working cooperatively are respectively provided with a signal channel, and in order to ensure synchronous playing of multi-channel pulse time sequence signals, delay compensation units are usually required to be arranged in each channel in the related art. However, in the case of a large number of channels, such as 12 channels, 20 channels, or even more channels, if a delay compensation unit is provided in each channel, cost saving and improvement of system reliability are not facilitated.

Disclosure of Invention

The present invention aims to solve at least one of the technical problems in the related art to some extent. To this end, a first object of the present invention is to propose a multi-channel pulse synchronization method to save costs and improve system reliability.

A second object of the invention is to propose an electronic device.

A third object of the present invention is to provide a multi-channel pulse synchronization device.

A fourth object of the present invention is to propose a multi-channel pulse synchronization system.

To achieve the above object, an embodiment of a first aspect of the present invention provides a multi-channel pulse synchronization method, including: acquiring design pulse time sequences of a plurality of channels, and overall delay, level control on-delay and level control Guan Yanshi of each channel; generating a gate cover delay sequence for each of the channels based on the plurality of overall delays, the plurality of level control on-delays, and the plurality of level controls Guan Yanshi; and adjusting the corresponding design pulse time sequence according to the gate pocket delay sequence so as to enable the channels to synchronously play the pulse time sequence.

To achieve the above object, an embodiment of a second aspect of the present invention provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, where the computer program is executed by the processor to implement the above-mentioned multi-channel pulse synchronization method.

To achieve the above object, an embodiment of a third aspect of the present invention provides a multi-channel pulse synchronization device, including: an acquisition module for acquiring a design pulse timing of a plurality of channels, and an overall delay, a level control on-delay, and a level control Guan Yanshi for each of the channels; a generating module for generating a door pocket delay sequence for each of the channels based on a plurality of the overall delays, a plurality of the level control on-delays, and a plurality of the level controls Guan Yanshi; and the adjusting module is used for adjusting the corresponding design pulse time sequence according to the gate pocket delay sequence so as to enable the channels to synchronously play the pulse time sequence.

In order to achieve the above object, a fourth aspect of the present invention provides a multi-channel pulse synchronization system, which includes the multi-channel pulse synchronization device.

According to the multi-channel pulse synchronization method, the device, the system and the electronic equipment, the design pulse time sequence of a plurality of channels, the overall delay of each channel, the level control on-delay and the level control Guan Yanshi are obtained; generating a gate pocket delay sequence for each channel according to the plurality of overall delays, the plurality of level control on-delays, and the plurality of level control Guan Yan; and adjusting the corresponding design pulse time sequence according to the gate pocket delay sequence so as to enable the channels to synchronously play the pulse time sequence. Therefore, the overall delay of each channel is obtained, the gate pocket delay sequence of each channel is generated according to the overall delay, and the corresponding design pulse time sequence is adjusted according to the gate pocket delay sequence, so that different channels are prevented from having different overall delays, a plurality of channels can synchronously play the pulse time sequence, a delay compensation unit is not required to be arranged, the cost is saved, and the reliability of the system is improved.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

FIG. 1 is a schematic diagram of an exemplary multi-channel pulse;

FIG. 2 is a flow diagram of a multi-channel pulse synchronization method in accordance with one or more embodiments of the invention;

FIG. 3 is a flow diagram of a multi-channel pulse synchronization method in accordance with one or more embodiments of the present invention;

FIG. 4 is a schematic diagram of a multi-channel pulse of one example of the present invention;

FIG. 5 is a schematic diagram of a multi-channel pulse of another example of the present invention;

FIG. 6 is a block diagram of a multi-channel pulse synchronization device according to an embodiment of the present invention;

fig. 7 is a block diagram of a multi-channel pulse synchronization system according to an embodiment of the present invention.

Detailed Description

The following describes a multi-channel pulse synchronization method, apparatus, system and electronic device of embodiments of the present invention with reference to the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described with reference to the drawings are exemplary and should not be construed as limiting the invention.

The playing of pulse time sequence signals of all channels is asynchronous, and two main influencing factors are: firstly, the integral delay of the channel is different due to the difference of the characteristics of signal wires and signal devices in the channel; and secondly, the actual execution result of the pulse time sequence is deviated and accumulated on the integral delay of the channel due to the fact that the delay from high level to low level and the delay from low level to high level of the level control unit of the pulse generating circuit in each channel are different. Referring specifically to the example shown in fig. 1, two channels are provided: AWG (American Wire Gauge ) channels and DAQ (Data Acquisition) channels. In fig. 1, timings 1 and 3 are the positions and lengths where the high level is theoretically located, taking the overall delay of the channel into consideration. The time sequence 2 and the time sequence 4 are the positions and the lengths of the high level after considering the integral delay of the channel, namely the execution time sequence corresponding to the design pulse time sequence. The high-level-to-low-level delay and the low-level-to-high-level delay of the level control unit are level control switch delay for controlling the high-level-to-low-level conversion of the pulse signal, the level control switch delay comprises level control switch delay and level control Guan Yanshi, in fig. 1, the overall delay of an AWG channel is a, the level control switch delay is b, and the level control Guan Yanshi is c; the overall delay of the DAQ channel is a ', the level control on delay is b ', and the level control Guan Yanshi is c '. As is apparent from fig. 1, the delay of the level control switches for controlling the high-low level transition of the pulse timing signal in the AWG channel and the DAQ channel is different, so that the actual lengths of the high-low level of the pulse timing signal are not identical to the design, and the overall length of the execution timing pulse signal is also deviated.

Thus, the present invention proposes a multi-channel pulse synchronization method.

Fig. 2 is a flow diagram of a multi-channel pulse synchronization method in accordance with one or more embodiments of the invention.

As shown in fig. 2, the multi-channel pulse synchronization method includes:

s21, acquiring design pulse time sequences of a plurality of channels, and overall delay, level control on-delay and level control Guan Yanshi of each channel.

S22, generating a gate cover delay sequence of each channel according to the plurality of integral delays, the plurality of level control opening delays and the plurality of level control Guan Yan.

S23, adjusting the corresponding design pulse time sequence according to the gate pocket delay sequence so as to enable the channels to synchronously play the pulse time sequence.

Therefore, the overall delay of each channel is obtained, the gate pocket delay sequence of each channel is generated according to the overall delay, and the corresponding design pulse time sequence is adjusted according to the gate pocket delay sequence, so that different channels are prevented from having different overall delays, a plurality of channels can synchronously play the pulse time sequence, a delay compensation unit is not required to be arranged, the cost is saved, and the reliability of the system is improved. Moreover, the upper computer can jointly compensate the time delay of a plurality of lower computers without each lower computer compensating own time delay.

In one or more embodiments of the invention, a gate cover delay sequence for each channel is generated based on a plurality of overall delays, a plurality of level control on-delays, and a plurality of level control Guan Yan, comprising: obtaining a first reference length according to the longest overall delay and the shortest overall delay in the overall delays of the plurality of channels; for each channel, obtaining a corresponding front-end door pocket signal length and a corresponding back-end door pocket signal length according to a plurality of overall delays, a first reference length, a plurality of level control opening delays and a plurality of level controls Guan Yanshi; generating a front door pocket sequence according to the front door pocket signal length, generating a rear door pocket sequence according to the rear door pocket signal length, and taking the front door pocket sequence and the rear door pocket sequence as door pocket delay sequences.

In one or more embodiments of the present invention, deriving the corresponding front-end and back-end jammer signal lengths from a plurality of overall delays, a first reference length, a plurality of level control on-delays, and a plurality of level controls Guan Yanshi, comprises: calculating the difference value between the integral delay of the channel and the first reference length to obtain the corresponding front-end door pocket signal length; for each channel, calculating to obtain the total time sequence length corresponding to the channel according to the time sequence information of the designed pulse time sequence corresponding to the channel, the level control on delay of the channel, the level control off delay of the channel and the front-end gate sleeve signal length corresponding to the channel; and determining the signal length of the rear door pocket of the channel according to the time sequence total length of the channel and the time sequence total lengths.

In one or more embodiments of the present invention, determining a back-end gate sleeve signal length of the channel according to a time sequence total length and a plurality of time sequence total lengths of the channel includes: acquiring the longest time sequence total length and the shortest time sequence total length in a plurality of time sequence total lengths; obtaining a second reference length according to the longest time sequence total length and the shortest time sequence total length; and calculating the signal length of the rear door pocket of the channel according to the second reference length, the shortest time sequence total length and the time sequence total length of the channel.

Specifically, for a plurality of channels, each channel obtains an overall delay, thereby obtaining the longest overall delay a of the plurality of overall delays _max With the shortest overall delay a _min 。

After the longest overall delay and the shortest overall delay are obtained, calculating to obtain a difference value between the longest overall delay and the shortest overall delay, and obtaining a first difference value. The first reference length Lf may be set to any value greater than or equal to the first difference value.

After the first reference length is obtained, the signal length of the front door pocket of each channel can be obtained according to the first reference length. Taking the AWG channel as an example, the front end sleeve signal length of the AWG channel l1=lf-a. After the front-end door pocket signal length is obtained, a front-end door pocket sequence is generated according to the front-end door pocket signal length, and then the front-end door pocket sequence is added at the front end of the designed pulse time sequence. This process is performed for each channel so that each channel has the same overall delay, and if the above-described fig. 1 is taken as an example, the problem that the overall delays a and a 'are different is solved by setting the gate sleeve signal, that is, setting the lengths of the front gate sleeve signals to L1 and L2 so that l1+a=l2+a'.

The level control switch delays include a low-to-high delay and a high-to-low delay as shown in fig. 1. And acquiring corresponding delay of the level control switch for each channel, and calculating to obtain the corresponding time sequence total length of the channel according to the time sequence information of the design pulse time sequence corresponding to the channel, the delay of the level control switch of the channel and the signal length of the front gate sleeve.

Thus, it is possible to achieve the total length of the timing of one channel.

After the corresponding time sequence total length is calculated for each channel by adopting the method, determining the rear-end gate sleeve signal length of the channel according to the multiple design pulse time sequences, the level control switch delay and the front-end gate sleeve signal length of the channel, and the method further comprises the following steps: acquiring the longest time sequence total length and the shortest time sequence total length in the time sequence total lengths of a plurality of channels; obtaining a second reference length according to the longest time sequence total length and the shortest time sequence total length; and calculating the signal length of the rear door pocket of the channel according to the second reference length, the shortest time sequence total length and the time sequence total length corresponding to the channel.

Specifically, after calculating the corresponding time sequence total length for each channel, the longest time sequence total length M of the plurality of time sequence total lengths is obtained _max And the shortest time sequence total length M _min And calculating a difference value between the longest time sequence total length and the shortest time sequence total length to obtain a second difference value, and further obtaining a second reference length according to the second difference value.

Wherein the second reference length may be any value greater than or equal to the second difference.

After the second reference length is obtained, the signal length of the rear-end gate sleeve is calculated according to the time sequence total length of the channel, the second reference length and the shortest time sequence total length aiming at the channel needing to generate the rear-end gate sleeve sequence, so that the rear-end gate sleeve sequence is generated according to the signal length of the rear-end gate sleeve, and the rear-end gate sleeve sequence is connected to the rear end of the designed pulse time sequence, so that the generation time sequences of different channels have the same length as a whole.

In one or more embodiments of the present invention, the timing information includes a preset interval and a high level number, the preset interval is an interval between a leading edge of a designed pulse timing and a trailing edge of a last high level, and a total length of the timing is calculated according to the following formula:

M1＝L1+d+(x1-x2)*n，

wherein M1 is the total time sequence length, L1 is the signal length of the front end gate sleeve, d is the preset interval, x1 is the level control on delay, x2 is the level control Guan Yanshi, and n is the high level number. Taking the AWG channel shown in fig. 1 as an example, x1 is b and x2 is c.

In one or more embodiments of the present invention, the back-end jamb signal length is calculated according to the following equation:

M2＝M _min +Lb-M1，

wherein M2 is the signal length of the rear door pocket, M _min For the shortest total length of the time sequence, lb is the second reference length, and M1 is the total length of the time sequence corresponding to the channel.

Continuing with the description of the AWG channel in the example shown in fig. 1, specific steps may be as follows.

The total time sequence length of each channel is determined, taking an AWG channel as an example, the number of high levels in the design pulse time sequence is n, the interval from the leading edge of the design pulse time sequence signal to the falling edge of the last high level is d, and the total time sequence length m1=l1+d+ (b-c) n.

Determining the reference length Lb of the back-end gate sleeve sequence, wherein Lb is greater than or equal to the longest time sequence total length M in each channel _max And the shortest time sequence total length M _min Is a difference in (c).

Determining the signal length of the rear door pocket of each channel, taking an AWG channel as an example, and the signal length of the rear door pocket is M _min +Lb-M1。

And generating a back-end door pocket sequence according to the back-end door pocket signal length.

And generating a door pocket delay sequence for each channel according to the front door pocket sequence and the rear door pocket sequence of each channel. Specifically, a front-end gate sleeve sequence can be added at the front end of the designed pulse sequence, and a rear-end gate sleeve sequence can be added at the rear end of the designed pulse sequence.

In one or more embodiments of the present invention, after generating the back-end gate sleeve sequence according to the back-end gate sleeve signal length, referring to fig. 3, adjusting the corresponding design pulse timing according to the gate sleeve delay sequence, further includes:

s31, adding the rear-end gate sleeve sequence to the front end of the designed pulse time sequence to obtain a delay reference sequence.

S32, acquiring the rising edge position and the falling edge position of the delay reference sequence.

S33, a rising delay sequence is generated according to the rising edge position and the level control on delay, and a falling delay sequence is generated according to the falling edge position and the level control Guan Yanshi.

S34, adjusting the design pulse time sequence by the rising delay sequence and the falling delay sequence.

The description continues with the AWG channel shown in fig. 1. Specifically, first, a corresponding back-end gate sleeve sequence is added to the front end of the design timing signal of each channel to obtain a delay reference sequence.

With reference to the delay reference sequence, a high level with a pulse width of b is generated at each rising edge position, and the high level falling edge with the pulse width of b is aligned with the corresponding rising edge in the delay reference sequence, and the rest is complemented with a low level, thereby generating a rising delay sequence.

With reference to the delay reference sequence, a high level with a pulse width of c is generated at each falling edge position, and the high level falling edge with the pulse width of c is aligned with the corresponding falling edge in the delay reference sequence, and the rest part is complemented with a low level, thereby generating a falling delay sequence.

Further, the position of the design pulse time sequence of the AWG channel corresponding to the high level in the rising delay sequence is adjusted to be high level in the first interval, the position of the design pulse time sequence of the AWG channel corresponding to the high level in the falling delay sequence is adjusted to be low level, and the pulse width and the position of the high level of the design pulse time sequence are changed to form the switch delay compensation sequence.

Therefore, deviation of the actual execution result of the pulse time sequence caused by different high-level to low-level delay and low-level to high-level delay of different channels can be avoided, and the pulse time sequence can be synchronously played.

After the switching delay compensation sequence is obtained, a low-level signal with the length of L1 can be added at the front end of the switching delay compensation sequence, and a low-level signal with the length of M can be added at the rear end of the switching delay compensation sequence _min The low level signal of +Lb-M1, namely, the front end gate sleeve sequence is added at the front end of the switch delay compensation sequence, and the rear end gate sleeve sequence is added at the rear end of the switch delay compensation sequence, so as to obtain the pulse time sequence of the actual input channel.

Referring to fig. 4, after generating the AWG channel design pulse sequence, the design pulse sequence may refer to fig. 4, and the design pulse sequence is processed according to the obtained AWG gate sleeve delay (i.e., the back end gate sleeve sequence of the AWG channel) to obtain a delay reference sequence, a high level is generated at the rising edge position of the delay reference sequence to obtain a rising delay sequence (i.e., the AWG rising delay in fig. 4), and a high level is generated at the falling edge position of the delay reference sequence to obtain a falling delay sequence (i.e., the AWG falling delay in fig. 4).

After the rising delay sequence and the falling delay sequence are generated, the position corresponding to the high level in the rising delay sequence in the design pulse time sequence is adjusted to be high level, the position corresponding to the high level in the falling delay sequence in the design pulse time sequence is adjusted to be low level, a switch delay compensation sequence is obtained, a low level signal with the length of L1 is added at the front end of the switch delay compensation sequence (namely, the switch delay compensation sequence is adjusted according to the front end gate sleeve sequence), and the length of M is added at the rear end of the switch delay compensation sequence _min The low level signal of +lb-M1 (i.e., the switching delay compensation sequence is adjusted according to the back-end gate sleeve sequence) results in the AWG generation sequence shown in fig. 4. In fig. 4, the sequence 5 is a sequence before the design pulse sequence is processed according to the rising delay sequence and the falling delay sequence, and the sequence 6 is a sequence after the design pulse sequence is processed according to the rising delay sequence and the falling delay sequence.

And inputting the AWG generating time sequence into an AWG channel to obtain an AWG executing time sequence.

The description continues with the example shown in fig. 1.

Referring to fig. 5, after the design pulse timing is obtained, the design timing of the design pulse timing is processed to obtain a generation timing, and then the generation timing is input into a corresponding channel to obtain an execution timing.

Specifically, the problem of the overall delays a and a 'being different is solved by providing the door pocket, i.e., the front-end door pocket sequences are provided with lengths L1 and L2 such that l1+a=l2+a'; the back-end gate sleeve sequence is arranged to provide the generation timings of the AWG channel and the DAQ channel with the same length as a whole.

In addition, the rising edge and the falling edge of each high level of the AWG channel and the DAQ channel are pre-adjusted, specifically, the rising edge of each high level of the AWG channel is advanced by b time, the falling edge of each high level of the AWG channel is advanced by c time, the rising edge of each high level of the DAQ channel is advanced by b 'time, and the falling edge of each high level of the DAQ channel is advanced by c' time.

After the generation time sequence generated by the processing enters the AWG channel and the DAQ channel for playing, the actual execution time sequence is shown in fig. 5, and the two channel time sequences are synchronous and accord with the designed high-low level distribution.

Of course, 12 channels or 20 channels or even more channels, the application can be extended accordingly in accordance with the method of the present invention.

In summary, the multi-channel pulse synchronization method of the embodiment of the invention obtains the design pulse time sequence of a plurality of channels, and the overall delay, the level control on-delay and the level control Guan Yanshi of each channel; generating a door pocket delay sequence of each channel according to the plurality of integral delays, the plurality of bubble control opening delays and the plurality of level control Guan Yan; and adjusting the corresponding design pulse time sequence according to the gate pocket delay sequence so as to enable the channels to synchronously play the pulse time sequence. Therefore, the overall delay of each channel is obtained, the gate pocket delay sequence of each channel is generated according to the overall delay, and the corresponding design pulse time sequence is adjusted according to the gate pocket delay sequence, so that different channels are prevented from having different overall delays, a plurality of channels can synchronously play the pulse time sequence, a delay compensation unit is not required to be arranged, the cost is saved, and the reliability of the system is improved. And the back-end gate sleeve sequence can be generated, and then the back-end gate sleeve sequence is connected to the back end of the designed pulse time sequence, so that the generation time sequences of different channels have the same length as a whole. And by generating the delay reference sequence, generating the rising delay sequence and the falling delay sequence according to the delay reference sequence, and utilizing the rising delay sequence and the falling delay sequence, the deviation of the actual execution result of the pulse time sequence caused by different high-level to low-level delay and low-level to high-level delay of different channels is avoided, so that the pulse time sequence can be synchronously played.

Further, the invention provides electronic equipment.

In an embodiment of the present invention, an electronic device includes a memory, a processor, and a computer program stored on the memory and executable on the processor, where the computer program, when executed by the processor, implements the above-described multi-channel pulse synchronization method.

The electronic equipment of the embodiment of the invention obtains the design pulse time sequence of a plurality of channels, and the integral delay, the level control on-delay and the level control Guan Yanshi of each channel by realizing the multi-channel pulse synchronization method; generating a door pocket delay sequence of each channel according to the plurality of integral delays, the plurality of bubble control opening delays and the plurality of level control Guan Yan; and adjusting the corresponding design pulse time sequence according to the gate pocket delay sequence so as to enable the channels to synchronously play the pulse time sequence. Therefore, the overall delay of each channel is obtained, the gate pocket delay sequence of each channel is generated according to the overall delay, and the corresponding design pulse time sequence is adjusted according to the gate pocket delay sequence, so that different channels are prevented from having different overall delays, a plurality of channels can synchronously play the pulse time sequence, a delay compensation unit is not required to be arranged, the cost is saved, and the reliability of the system is improved. And the back-end gate sleeve sequence can be generated, and then the back-end gate sleeve sequence is connected to the back end of the designed pulse time sequence, so that the generation time sequences of different channels have the same length as a whole. And by generating the delay reference sequence, generating the rising delay sequence and the falling delay sequence according to the delay reference sequence, and utilizing the rising delay sequence and the falling delay sequence, the deviation of the actual execution result of the pulse time sequence caused by different high-level to low-level delay and low-level to high-level delay of different channels is avoided, so that the pulse time sequence can be synchronously played.

Further, the invention provides a multi-channel pulse synchronization device.

Fig. 6 is a block diagram of a multi-channel pulse synchronization apparatus according to an embodiment of the present invention.

As shown in fig. 6, the multi-channel pulse synchronization device 100 includes: an acquisition module 101 for acquiring the design pulse timing of the plurality of channels, and the overall delay, the level control on-delay, and the level control Guan Yanshi of each channel; a generating module 102, configured to generate a gate cover delay sequence of each channel according to the plurality of overall delays, the plurality of level control on-delays, and the plurality of level control Guan Yan; the adjusting module 103 is configured to adjust the corresponding design pulse sequence according to the gate pocket delay sequence, so that the multiple channels play the pulse sequence synchronously.

It should be noted that, for other specific implementations of the multi-channel pulse synchronization device according to the embodiments of the present invention, reference may be made to the multi-channel pulse synchronization method of the foregoing embodiments.

The multi-channel pulse synchronization device acquires the design pulse time sequence of a plurality of channels, and the overall delay, the level control on-delay and the level control Guan Yanshi of each channel; generating a door pocket delay sequence of each channel according to the plurality of integral delays, the plurality of bubble control opening delays and the plurality of level control Guan Yan; and adjusting the corresponding design pulse time sequence according to the gate pocket delay sequence so as to enable the channels to synchronously play the pulse time sequence. Therefore, the overall delay of each channel is obtained, the gate pocket delay sequence of each channel is generated according to the overall delay, and the corresponding design pulse time sequence is adjusted according to the gate pocket delay sequence, so that different channels are prevented from having different overall delays, a plurality of channels can synchronously play the pulse time sequence, a delay compensation unit is not required to be arranged, the cost is saved, and the reliability of the system is improved. And the back-end gate sleeve sequence can be generated, and then the back-end gate sleeve sequence is connected to the back end of the designed pulse time sequence, so that the generation time sequences of different channels have the same length as a whole. And by generating the delay reference sequence, generating the rising delay sequence and the falling delay sequence according to the delay reference sequence, and utilizing the rising delay sequence and the falling delay sequence, the deviation of the actual execution result of the pulse time sequence caused by different high-level to low-level delay and low-level to high-level delay of different channels is avoided, so that the pulse time sequence can be synchronously played.

Further, the invention provides a multichannel pulse synchronization system.

Fig. 7 is a block diagram of a multi-channel pulse synchronization system according to an embodiment of the present invention.

As shown in fig. 7, the multi-channel pulse synchronization system 10 includes the multi-channel pulse synchronization device 100 described above.

The multi-channel pulse synchronization system of the embodiment of the invention obtains the design pulse time sequence of a plurality of channels, and the overall delay, the level control on-time delay and the level control Guan Yanshi of each channel; generating a door pocket delay sequence of each channel according to the plurality of integral delays, the plurality of bubble control opening delays and the plurality of level control Guan Yan; and adjusting the corresponding design pulse time sequence according to the gate pocket delay sequence so as to enable the channels to synchronously play the pulse time sequence. Therefore, the overall delay of each channel is obtained, the gate pocket delay sequence of each channel is generated according to the overall delay, and the corresponding design pulse time sequence is adjusted according to the gate pocket delay sequence, so that different channels are prevented from having different overall delays, a plurality of channels can synchronously play the pulse time sequence, a delay compensation unit is not required to be arranged, the cost is saved, and the reliability of the system is improved. And the back-end gate sleeve sequence can be generated, and then the back-end gate sleeve sequence is connected to the back end of the designed pulse time sequence, so that the generation time sequences of different channels have the same length as a whole. And by generating the delay reference sequence, generating the rising delay sequence and the falling delay sequence according to the delay reference sequence, and utilizing the rising delay sequence and the falling delay sequence, the deviation of the actual execution result of the pulse time sequence caused by different high-level to low-level delay and low-level to high-level delay of different channels is avoided, so that the pulse time sequence can be synchronously played.

It should be noted that the logic and/or steps represented in the flow diagrams or otherwise described herein may be considered a ordered listing of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer readable medium may even be paper or other suitable medium on which the program is printed, as the program may be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.

It is to be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.

In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In the description of the present specification, the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. refer to an orientation or positional relationship based on that shown in the drawings, and do not indicate or imply that the apparatus or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and should not be construed as limiting the invention.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.

In the description of the present specification, unless otherwise indicated, the terms "mounted," "connected," "secured," and the like are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.

In the present invention, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.

While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.

Claims (10)

1. A method of multi-channel pulse synchronization, the method comprising:

acquiring design pulse time sequences of a plurality of channels, and overall delay, level control on-delay and level control Guan Yanshi of each channel;

generating a gate cover delay sequence for each of the channels based on the plurality of overall delays, the plurality of level control on-delays, and the plurality of level controls Guan Yanshi;

and adjusting the corresponding design pulse time sequence according to the gate pocket delay sequence so as to enable the channels to synchronously play the pulse time sequence.

2. The method of claim 1, wherein said generating a gate cover delay sequence for each of said channels based on a plurality of said global delays, a plurality of said level control on-delays, and a plurality of said level controls Guan Yanshi comprises:

obtaining a first reference length according to the longest overall delay and the shortest overall delay of the overall delays of the channels;

for each channel, obtaining a front-end door pocket signal length and a rear-end door pocket signal length according to a plurality of integral delays, a first reference length, a plurality of level control opening delays and a plurality of level control closing delays;

generating a front-end door pocket sequence according to the front-end door pocket signal length, generating a rear-end door pocket sequence according to the rear-end door pocket signal length, and taking the front-end door pocket sequence and the rear-end door pocket sequence as the door pocket delay sequence.

3. The method of claim 2, wherein the obtaining the corresponding front-end and back-end jammer signal lengths from the plurality of overall delays, the first reference length, the plurality of level-controlled on-delays, and the plurality of level-controlled off-delays comprises:

calculating the difference value between the integral delay of the channel and the first reference length to obtain the corresponding front-end door pocket signal length;

for each channel, calculating to obtain the total time sequence length corresponding to the channel according to the time sequence information of the design pulse time sequence corresponding to the channel, the level control on-time delay of the channel, the level control off-time delay of the channel and the front-end gate sleeve signal length corresponding to the channel;

and determining the signal length of the rear door pocket of the channel according to the time sequence total length of the channel and a plurality of time sequence total lengths.

4. The method of claim 3, wherein determining the back-end gate sleeve signal length of the channel according to the total time sequence length of the channel and the total time sequence lengths comprises:

acquiring the longest time sequence total length and the shortest time sequence total length in a plurality of time sequence total lengths;

obtaining a second reference length according to the longest time sequence total length and the shortest time sequence total length;

and calculating the signal length of the rear door pocket of the channel according to the second reference length, the shortest time sequence total length and the time sequence total length of the channel.

5. The multi-channel pulse synchronization method according to claim 3, wherein the timing information includes a preset interval and a high level number, the preset interval is an interval between a leading edge of the designed pulse timing and a trailing edge of a last high level, and the total length of the timing is calculated according to the following formula:

M1＝L1+d+(x1-x2)*n，

wherein M1 is the total length of the time sequence, L1 is the signal length of the front end gate sleeve, d is the preset interval, x1 is the level control on delay, x2 is the level control off delay, and n is the high level number.

6. The multi-channel pulse synchronization method of claim 4, wherein the back-end gate sleeve signal length is calculated according to the following equation:

M2＝M _min +Lb-M1，

wherein M2 is the signal length of the rear door pocket, M _min And Lb is the second reference length, and M1 is the corresponding time sequence total length of the channel.

7. The method of claim 4, wherein after generating the back-end gating sequence according to the back-end gating signal length, the adjusting the corresponding design pulse timing according to the gating delay sequence further comprises:

adding the rear-end gate sleeve sequence to the front end of the designed pulse time sequence to obtain a delay reference sequence;

acquiring the rising edge position and the falling edge position of the delay reference sequence;

generating a rising delay sequence according to the rising edge position and the level control on delay, and generating a falling delay sequence according to the falling edge position and the level control Guan Yanshi;

and adjusting the design pulse time sequence according to the rising delay sequence and the falling delay sequence.

8. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, which when executed by the processor, implements the multi-channel pulse synchronization method of any one of claims 1-7.

9. A multi-channel pulse synchronization device, comprising:

an acquisition module for acquiring a design pulse timing of a plurality of channels, and an overall delay, a level control on-delay, and a level control Guan Yanshi for each of the channels;

a generating module for generating a door pocket delay sequence for each of the channels based on a plurality of the overall delays, a plurality of the level control on-delays, and a plurality of the level controls Guan Yanshi;

and the adjusting module is used for adjusting the corresponding design pulse time sequence according to the gate pocket delay sequence so as to enable the channels to synchronously play the pulse time sequence.

10. A multi-channel pulse synchronization system comprising the multi-channel pulse synchronization device of claim 9.