JP2007292471A - Semiconductor tester - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor tester capable of shortening the adjustment time for timing calibration and improving the adjustment accuracy. <P>SOLUTION: The semiconductor tester includes a driver DR1 generating a driver signal; a delay element 50 variably delaying output timing of the driver signal; a comparator CP1 having an input end connected to an output end of the driver DR1; a delay element 52 variably delaying input timing of a strobe signal; a reference strobe signal output circuit 40, having a reference driver DR0 outputting a reference driver signal having known rise timing or fall timing; an input/output terminal where the connection points of the driver DR1 and the comparator CP1 are connected to a DUT 200; and relays RA1, RB1, RC1 selectively connected to either a reference strobe signal output circuit 40 or a termination resistor 70 that terminates a signal path, ahead of the connection point and a voltage source 72. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor test apparatus that adjusts the operation timing of a driver or a comparator in pin electronics of a semiconductor test apparatus.

  The pin electronics of a semiconductor test apparatus includes a driver that applies a signal to a device under measurement. This driver performs an output operation of a signal synchronized with an input clock signal. By the way, since the time length of the signal path for each input / output pin of the device under test varies, in the initial state, the timing of outputting a signal from each driver deviates from the expected timing. For this reason, timing calibration is performed before various tests are performed on the device under measurement. Specifically, a path for inputting and outputting a calibration signal is formed by a multi-stage relay circuit (relay matrix), and when performing timing calibration, the output terminal of each driver and a reference comparator ( There is known a method of connecting the input terminal of the reference voltage comparator) and adjusting the phase of the output signal of each driver based on the phase of the strobe signal input to the reference voltage comparator (for example, a patent). Reference 1). Note that the same timing calibration can be performed even if the reference comparator is replaced with a reference driver.

FIG. 7 is a diagram illustrating a conventional configuration in which timing calibration is performed using a reference driver and a multistage relay circuit. The output terminal of the driver DR to be calibrated and the input terminal of the comparator CP are connected at a common connection point, and the output terminal of the reference driver DR0 is connected to this connection point via the multistage relay circuit 100. Yes. In such a configuration, timing calibration is performed in the following procedure.
(1) First, the input terminal of the comparator CP is connected to the output terminal of the reference driver DR0 via the multistage relay circuit 100. At this time, the relay 110 on the DUT 200 side is turned off, and the relay 112 provided between the comparator CP and the multistage relay circuit 100 is turned on. In such a connection state, the output signal of the reference driver DR0 is input to the comparator CP, and the phase of the strobe signal that determines the timing of the comparison operation by the comparator CP is adjusted. By switching the connection state in the multistage relay circuit 100, the phase of the strobe signal corresponding to each comparator CP is adjusted in order.
(2) Next, both the relays 110 and 112 are turned off. As a result, the connection point between the comparator CP and the driver DR is disconnected from both the DUT 200 and the multistage relay circuit 100. In such a connection state, the phase of the output signal of the driver DR is adjusted with reference to the phase of the strobe signal of the comparator CP.
JP-A-11-287844 (page 2-4, FIG. 3-9)

  By the way, recent semiconductor test equipment has a tendency to adopt a liquid cooling method using a cooling liquid as a countermeasure against heat generation of semiconductor parts in the apparatus, and one of them is an immersion in which the heat generating parts in the apparatus are immersed in the cooling liquid. There is a liquid cooling system. In this method, since the relays 110 and 112, which are consumable parts in the pin electronics, are difficult to be immersed in the coolant from the viewpoint of maintenance, a certain distance from the driver DR and the comparator CP is ensured to the outside of the cooling unit. Need to be placed. In this case, when both the relays 110 and 112 are turned off to adjust the phase of the output signal of the driver DR, the branch wiring portion from the connection point between the driver DR and the comparator CP to the relays 110 and 112 becomes an open end. Signal reflection occurs. For this reason, the comparison level for detecting the rising or falling edge of the input signal in the comparator CP cannot be shared by 50% of the signal amplitude. As shown in FIG. There is a problem that it is necessary to set the comparison level separately at the time of phase adjustment, and it takes time for timing calibration. In addition, there is a problem that the timing calibration adjustment accuracy deteriorates as the difference between the actual test comparison level (50% of the signal amplitude) and the timing calibration comparison level increases.

  The present invention was created in view of the above points, and an object of the present invention is to provide a semiconductor test apparatus capable of reducing the timing calibration time and improving the adjustment accuracy. It is in.

  In order to solve the above-described problems, a semiconductor test apparatus according to the present invention is provided with a driver that generates a driver signal to be output to a device under test, and a driver signal output from the driver. A first delay means for delaying the output timing, and an input terminal connected to the output terminal of the driver; the input signal is compared with a predetermined reference level in synchronization with the input timing of the strobe signal; A reference signal having a reference driver for outputting a reference driver signal whose rise timing or fall timing is known, a second delay means for delaying the input timing of the strobe signal input to the comparator in a changeable manner Connect the connection point between the output means, driver and comparator to the device under test Input and output terminals, a reference signal output unit, and a connection switching means for selectively connecting to one of the termination means for terminating the previous signal path than the connecting point. Specifically, the delay amount is set by the second delay means using the reference driver signal output from the reference signal output means while the connection by the connection switching means is switched to the reference signal output means side. Thereafter, in a state where the connection by the connection switching unit is switched to the termination unit side, the driver signal output from the driver is input to the comparator, whereby the delay amount is set by the first delay unit.

  After adjusting the input timing of the strobe signal of the comparator using the reference driver signal, when adjusting the output timing of the driver signal by inputting the driver signal output from the driver to the comparator, the connection point between the driver and the comparator Since the end of the previous signal path does not become an open end, reflection of the signal generated at this end can be suppressed. For this reason, the reference level of the comparator for determining the rising timing and falling timing of the driver signal can be set to 50% of the driver signal, and the timing calibration time can be shortened. Further, since the comparison operation by the comparator can be performed without using the shoulder portion in which the input waveform is deteriorated, the adjustment accuracy can be improved.

  The semiconductor test apparatus of the present invention is provided with a driver that generates a driver signal to be output to the device under test and a front stage of the driver, and delays the output timing of the driver signal output from the driver so that the output timing can be changed A first delay unit that causes the input end to be connected to the output end of the driver, and compares the input signal with a predetermined reference level in synchronization with the input timing of the strobe signal, and outputs a comparison result; Second delay means for delaying the input timing of the strobe signal input to the input, reference comparison means having a reference comparator for performing a comparison operation according to a reference strobe signal whose input timing is known, a driver and a comparator, The connection points of the I / O terminal connected to the device under test, the reference comparison means, and this connection And a connection switching means for selectively connecting to one of the termination means for terminating the previous signal path than. Specifically, the delay amount is set by the first delay means by inputting the driver signal output from the driver to the reference comparator in a state where the connection by the connection switching means is switched to the reference signal output means side. After that, the delay amount is set by the second delay means by inputting the driver signal output from the driver to the comparator while the connection by the connection switching means is switched to the termination means side.

  After adjusting the output timing of the driver signal output from the driver using the reference comparator, when the driver signal output from the driver is input to the comparator and the input timing of the strobe signal of the comparator is adjusted, Since the end of the signal path ahead of the connection point is not an open end, reflection of the signal generated at this end can be suppressed. For this reason, the reference level of the comparator for determining the rising timing and falling timing of the driver signal can be set to 50% of the driver signal, and the timing calibration time can be shortened. Further, since the comparison operation by the comparator can be performed without using the shoulder portion in which the input waveform is deteriorated, the adjustment accuracy can be improved.

  Moreover, it is desirable that the termination means described above has a resistance value equivalent to the impedance of the signal path to which the termination means is connected. Thereby, the reflection of the signal generated at the end of the signal path can be completely eliminated, and the adjustment accuracy can be further improved.

  Hereinafter, a semiconductor test apparatus according to an embodiment to which the present invention is applied will be described in detail.

  FIG. 1 is a diagram illustrating an overall configuration of a semiconductor test apparatus that is a target of timing calibration performed in an embodiment. The semiconductor test apparatus includes a semiconductor test apparatus main body 10 and a workstation 80 in order to perform a predetermined test on a DUT (device under measurement) 200.

  The workstation 80 controls a whole series of test operations such as a function test and a timing calibration operation, and realizes an interface with the user. The function of the workstation 80 may be built in the semiconductor test apparatus body 10. The semiconductor test apparatus main body 10 performs various tests on the DUT 200 by executing a predetermined test program transferred from the workstation 80. In addition, the semiconductor test apparatus main body 10 performs timing calibration by executing a dedicated program transferred from the workstation 80. For this purpose, the semiconductor test apparatus main body 10 includes a tester control unit 12, a timing generator 14, a pattern generator 16, a data selector 18, a format control unit 20, a pin electronics 22, and a performance board (PB) 30.

  The tester control unit 12 is connected to each component such as the timing generator 14 via a bus, and executes various test operations on each component by executing a test program transferred from the workstation 80. Control necessary for timing calibration.

  The timing generator 14 sets a basic period of the test operation and generates various timing edges included in the set basic period. The pattern generator 16 generates pattern data to be input to each pin of the device under measurement. The data selector 18 associates various pattern data output from the pattern generator 16 with each pin of the device under measurement that inputs the pattern data. The format control unit 20 performs waveform control on the device under measurement based on the pattern data generated by the pattern generator 16 and selected by the data selector 18 and the timing edge generated by the timing generator 14.

  The pin electronics 22 is used to establish a physical interface with the device under test, and is actually measured based on the clock signal CLK and strobe signal STB generated by the waveform control of the format control unit 20. Generates signals that are input to and output from the device. For this purpose, the pin electronics 22 includes n drivers DR1, DR2,..., N comparators CP1, CP2,..., And a reference strobe signal output circuit 40 used for timing calibration. It consists of

  The drivers DR1, DR2,... Perform a signal generation operation synchronized with the clock signal CLK1 output from the format control unit 20. The comparators CP1, CP2,... Perform a comparison operation in synchronization with the strobe signals STB1, STB2,... Output from the format control unit 20, and when the strobe signals STB1, STB2,. The logic of the signal input from the corresponding pin is determined. The output terminal of the driver DR1 and the input terminal of the comparator CP1 are connected, and this connection point is connected to one input / output terminal via the relay RA1 and the performance board 30, and to the reference strobe signal output circuit 40 via the relay RB1. Each is connected. The other drivers DR2,... And the other comparators CP2,. That is, an output terminal of one driver is connected to an input terminal of a corresponding comparator, and this connection point is connected to one input terminal via relay RA (RA2,...) And relay RB (RB1). ,...) Are connected to the reference strobe signal output circuit 40, respectively. The reference strobe signal output circuit 40 includes a reference driver DR0 (described later) for timing correction, and outputs a reference driver signal whose rise timing is known.

  FIG. 2 is a diagram showing a partial configuration in the pin electronics 22. In FIG. 2, the peripheral configuration is shown focusing on a pair of driver DR1 and comparator CP1, but the same applies to other drivers DR2 and the like, and detailed description thereof is omitted.

  As shown in FIG. 2, the pin electronics 22 includes a delay element 50 corresponding to the driver DR1 and a delay element 52 corresponding to the comparator CP1. A clock signal is input to the driver DR1 through the delay element 50. A strobe signal is input to the comparator CP1 through the delay element 52. The entire driver DR1, comparator CP1, and delay elements 50 and 52 are provided inside the cooling unit 60 together with other drivers and the like. The cooling unit 60 is filled with a cooling liquid 62, and the cooling of the driver DR1 and the like is performed by the cooling liquid 62. Other drivers, comparators, and delay elements corresponding to these drivers are also provided in the cooling unit 60 and are cooled by the cooling liquid 62.

  As shown in FIG. 2, the pin electronics 22 includes a relay RC1, a terminating resistor 70, and a voltage source 72 corresponding to the driver DR1 and the comparator CP1 paired therewith. As described above, the relay RB1 is inserted in the path branched to the reference strobe signal output circuit 40 side at the connection point between the driver DR1 and the comparator CP1, and the relay RC1 further outputs the relay RB1 and the reference strobe signal. It is provided between the circuits 40. The relay RC1 is for switching the connection destination of the connection point between the driver DR1 and the comparator CP1 to either the reference strobe signal output circuit 40 or the termination resistor 70 side. When switching to the termination resistor 70 side, the connection point between the driver DR1 and the comparator CP1 is connected to one end of the termination resistor 70 via the relays RB1 and RC1. The resistance value Rx of the termination resistor 70 is set to a value that is transparent to the impedance of the transmission line from the termination resistor 70 on the driver DR1 side. The other end of the termination resistor 70 is connected to the voltage source 72.

  As shown in FIG. 2, the reference strobe signal output circuit 40 includes a reference driver DR0 and a multistage relay circuit 42. The reference driver DR0 outputs a reference driver signal with a known rising timing (or falling timing). The multi-stage relay circuit 42 is configured by combining a plurality of relays. By appropriately switching the on / off state of each relay, the reference driver signal output from the reference driver DR0 is selectively directed toward each comparator CP1 and the like. Output.

  The delay element 50 described above is the first delay means, the delay element 52 is the second delay means, the reference strobe signal output circuit 40 is the reference signal output means, and the relays RA1, RB1, and RC1 are the connection switching means. The resistor 70 and the voltage source 72 correspond to termination means, respectively.

  The semiconductor test apparatus according to the present embodiment has such a configuration, and next, an operation when timing calibration is performed on the driver DR1 and the comparator CP1 will be described. The timing calibration operation described below is performed by executing a predetermined calibration program by the tester control unit 12.

  First, the phase adjustment of the strobe signal input to the comparator CP1 is performed by inputting the reference driver signal to the comparator CP1. FIG. 3 is a diagram showing the adjustment procedure of the strobe signal using the reference driver signal. At this time, the relay RA1 is turned off, the relay RB1 is turned on, and the relay RC1 is switched to the reference strobe signal output circuit 40 side. In such a connection state, as shown in FIG. 3, the timing for inputting the strobe signal to the comparator CP1 is adjusted in accordance with the rising timing of the reference driver signal. This adjustment is performed by varying the delay amount of the delay element 52 corresponding to the comparator CP1. The comparator CP1 performs an operation of comparing a reference level corresponding to 50% of the reference driver signal with an observation waveform (input waveform), and the comparison result is obtained when the input timing of the strobe signal is shifted little by little. The input timing of the strobe signal is adjusted by setting the delay amount of the delay element 52 at the timing when the signal changes.

  Next, by inputting the driver signal output from the driver DR1 to the comparator CP1, the phase of the driver signal output from the driver DR1 is adjusted. FIG. 4 is a diagram illustrating a driver signal adjustment procedure. At this time, the relay RA1 is turned off, the relay RB1 is turned on, and the relay RC1 is switched to the termination resistor 70 side. In such a connection state, as shown in FIG. 4, the rising timing and falling timing of the driver signal output from the driver DR1 are adjusted with the phase of the strobe signal input to the comparator CP1 fixed. This adjustment is performed by varying the delay amount of the delay element 50 corresponding to the driver DR1. Further, in this connection form, the branch wiring portion (signal path) ahead of the connection point between the driver DR1 and the comparator CP1 is terminated by the termination resistor 70 and the voltage source 72 via the relays RB1 and RC1. Signal reflection does not occur at the tip of the wiring portion. Therefore, the comparator CP1 can compare the reference level corresponding to 50% of the driver signal with the observation waveform (input waveform), and the comparator CP1 compares the output timing of the driver signal little by little. By setting the delay amount of the delay element 50 at the timing when the result changes, the output timing of the driver signal is adjusted.

  Thus, after adjusting the input timing of the strobe signal of the comparator CP1 using the reference driver signal, the driver signal output from the driver DR is input to the comparator CP to adjust the output timing of the driver signal. Since the end of the signal path beyond the connection point between the DR and the comparator CP does not become an open end, reflection of a signal generated at this end can be suppressed. Therefore, the reference level of the comparator CP that determines the rising timing and falling timing of the driver signal can be set to 50% of the driver signal, and the timing calibration time can be shortened. Further, since the comparison operation by the comparator CP can be performed without using the shoulder portion whose input waveform has deteriorated, the adjustment accuracy can be improved.

  By the way, in the configuration shown in FIG. 2, when the length of the branch wiring portion from the connection point of the relay RA1 and the relay RB1 to the relay RA1 becomes longer, reflection occurs at the tip of the branch wiring portion. FIG. 5 is a diagram showing a configuration of a modified example in which reflection at the branch wiring portion is further suppressed. The configuration shown in FIG. 5 is obtained by replacing two relays RA1 and RB1 with one relay RD1 with respect to the configuration shown in FIG. This relay RD1 is for switching the connection point of the connection point between the driver DR1 and the comparator CP1 to either the input / output terminal of the pin electronics 22 or the relay RC1. When the connection destination of this connection point is switched to the relay RC1 side, since there is no branch wiring portion on the input / output terminal side, there is no reflected wave generated when the end of the branch wiring portion becomes an open end.

  In addition, this invention is not limited to embodiment mentioned above, A various deformation | transformation implementation is possible within the range of the summary of this invention. For example, in the above-described embodiment, the delay amount of the delay element 50 corresponding to the driver DR1 is first set using the reference strobe signal output from the reference strobe signal output circuit 40, but first, the delay element 52 is set. May be set to adjust the input timing of the strobe signal corresponding to the comparator CP1. FIG. 6 is a diagram showing a configuration of a modified example of the semiconductor test apparatus. The configuration shown in FIG. 6 is obtained by replacing the reference strobe signal output circuit 40 with a reference comparison circuit 40A serving as a reference comparison unit with respect to the configuration shown in FIG. The reference comparison circuit 40A has a configuration in which the reference driver DR0 included in the reference strobe signal output circuit 40 is replaced with a reference comparator CP0. The reference comparator CP0 selectively receives a driver signal output from the driver DR1 or the like via the multistage relay circuit 42, and performs a comparison operation according to a reference strobe signal whose input timing is known.

  First, the output timing of the driver signal output from the driver DR1 is adjusted by inputting the driver signal output from the driver DR1 to the reference comparator CP0. At this time, relay RA1 is turned off, relay RB1 is turned on, and relay RC1 is switched to the reference comparison circuit 40A side. In such a connection state, the rising timing and falling timing of the driver signal output from the driver DR1 are adjusted with the phase of the reference strobe signal input to the comparator CP1 fixed.

  Next, the timing for inputting the strobe signal to the comparator CP1 is adjusted in accordance with the rising timing or falling timing of the driver signal output from the driver DR1. At this time, the relay RA1 is turned off, the relay RB1 is turned on, and the relay RC1 is switched to the termination resistor 70 side.

  As described above, after adjusting the output timing of the driver signal output from the driver DR1 using the reference comparator CP0, the driver signal output from the driver DR1 is input to the comparator CP1, and the input timing of the strobe signal of the comparator CP1 is set. When adjusting, since the end of the signal path beyond the connection point between the driver DR1 and the comparator CP1 does not become an open end, reflection of a signal generated at this end can be suppressed. Therefore, the reference level of the comparator CP1 that determines the rising timing and falling timing of the driver signal can be set to 50% of the driver signal, and the timing calibration time can be shortened. Further, since the comparison operation by the comparator CP1 can be performed without using the shoulder portion whose input waveform has deteriorated, the adjustment accuracy can be improved.

It is a figure which shows the whole structure of the semiconductor test apparatus used as the object of the timing calibration performed in one Embodiment. It is a figure which shows the partial structure in pin electronics. It is a figure which shows the adjustment point of the strobe signal using a reference | standard driver signal. It is a figure which shows the adjustment point of a driver signal. It is a figure which shows the structure of the modification which further suppressed the reflection in a branch wiring part. It is a figure which shows the structure of the modification of a semiconductor test apparatus. It is a figure which shows the conventional structure which performs a timing calibration using a reference | standard driver and a multistage relay circuit. It is a figure which shows the adjustment point of the driver signal using the structure shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor test apparatus main body 12 Tester control part 14 Timing generator 16 Pattern generator 18 Data selector 20 Format control part 22 Pin electronics 30 Performance board 40 Reference strobe signal output circuit 42 Multistage relay circuit 50, 52 Delay element 60 Cooling part 62 Cooling Liquid 80 Workstation 200 DUT (Device Under Test)
DR0 Reference driver DR1, DR2, ... Driver CP1, CP2, ... Comparator RA1, RB1, RC1, RD1 Relay

Claims (5)

A driver that generates a driver signal to be output to the device under test;
A first delay unit provided in a preceding stage of the driver, for delaying the output timing of the driver signal output from the driver in a changeable manner;
A comparator that has an input connected to the output of the driver, compares the input signal with a predetermined reference level in synchronization with the input timing of the strobe signal, and outputs a comparison result;
Second delay means for delayably changing the input timing of the strobe signal input to the comparator;
A reference signal output means having a reference driver for outputting a reference driver signal with a known rising timing or falling timing;
A connection point between the driver and the comparator is any one of an input / output terminal connected to the device under test, the reference signal output unit, and a termination unit that terminates a signal path ahead of the connection point. A connection switching means for selectively connecting to one;
A semiconductor test apparatus comprising: In claim 1,
In a state where the connection by the connection switching means is switched to the reference signal output means side, the delay amount is set by the second delay means using the reference driver signal output from the reference signal output means, and thereafter The setting of the delay amount by the first delay means is performed by inputting the driver signal output from the driver to the comparator in a state where the connection by the connection switching means is switched to the termination means side. A semiconductor test equipment. A driver that generates a driver signal to be output to the device under test;
A first delay unit provided in a preceding stage of the driver, for delaying the output timing of the driver signal output from the driver in a changeable manner;
A comparator that has an input connected to the output of the driver, compares the input signal with a predetermined reference level in synchronization with the input timing of the strobe signal, and outputs a comparison result;
Second delay means for delayably changing the input timing of the strobe signal input to the comparator;
A reference comparator having a reference comparator for performing a comparison operation in accordance with a reference strobe signal whose input timing is known;
One of a connection point between the driver and the comparator, an input / output terminal connected to the device under test, the reference comparison unit, and a termination unit that terminates a signal path ahead of the connection point Connection switching means for selectively connecting to,
A semiconductor test apparatus comprising: In claim 3,
The delay amount is set by the first delay means by inputting the driver signal output from the driver to the reference comparator in a state where the connection by the connection switching means is switched to the reference signal output means side. Thereafter, the delay amount is set by the second delay means by inputting the driver signal output from the driver to the comparator in a state where the connection by the connection switching means is switched to the termination means side. A semiconductor test apparatus. In any one of Claims 1-4,
The semiconductor test apparatus characterized in that the termination means has a resistance value equivalent to the impedance of the signal path to which the termination means is connected.

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