JP2010185790A - Test apparatus and calibration method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a test apparatus capable of calibrating an output timing and an acquisition timing prior to its test operation in order to enable a test signal and a response signal to be supplied and acquired precisely at a designated timing. <P>SOLUTION: The test apparatus for testing a device under test includes: a plurality of test signal output units each of which outputs a test signal for testing the device under test; a plurality of response signal acquisition units each of which acquires a response signal output by the device under test in response to the test signal; a device mounting unit for mounting, instead of the device under test, a calibration-use device with a reference driver unit which outputs a logic signal corresponding to a voltage level of a reference test signal output by the test signal output units to each of the plurality of response signal acquisition units, when calibrating the test apparatus; and an adjustment unit for adjusting the timing at which the response signal acquisition unit being an object to be adjusted acquires the logic signal, on the basis of results obtained by acquiring the logic signal output from the reference driver unit by the response signal acquisition unit being the object to be adjusted, in such the state that the calibration-use device is mounted. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a test apparatus and a calibration method.

  A test apparatus for testing a semiconductor device or the like supplies a test signal having a specified waveform to a device under test at a specified timing. Further, the test apparatus acquires the value of the response signal output from the device under test at a designated timing. Prior to the test, the test apparatus calibrates the output timing and the acquisition timing so that the test signal can be supplied and the response signal can be accurately acquired at the designated timing (Patent Document 1).

JP 2003-43124 A

  By the way, when the test apparatus calibrates the output timing and the acquisition timing, a calibration robot is placed on the test head instead of the device under test. The calibration robot mechanically connects each terminal of the test apparatus to the measuring apparatus one by one in order and calibrates each terminal.

  However, in recent years, the test apparatus has a configuration including a large number of drivers and comparators. Therefore, with such a calibration method, a great amount of time is spent for calibration.

  Further, when testing the device under test, a handler device is provided for transporting the device under test to the test head. Therefore, when the test apparatus is calibrated, the handler apparatus must be removed in order to avoid mechanical interference between the calibration robot and the handler apparatus.

  In order to solve the above-mentioned problem, in a first aspect of the present invention, a test apparatus for testing a device under test, which outputs a plurality of test signals for outputting test signals for testing the device under test. Unit, a plurality of response signal acquisition units for acquiring response signals output from the device under test according to the test signal, and a test output by the test signal output unit serving as a reference when the test apparatus is calibrated A device mounting unit for mounting a calibration device including a reference driver unit that outputs a logic signal corresponding to the voltage level of the signal to each of the plurality of response signal acquisition units instead of the device under test; and Based on the result of the response signal acquisition unit to be adjusted that the logic signal output from the reference driver unit is acquired in a state where the device is mounted, Response signal acquiring unit to provide a test apparatus comprising, an adjustment unit that adjusts the timing of acquiring the logic signal.

  According to a second aspect of the present invention, there is provided a test apparatus for testing a device under test, wherein a plurality of test signal output units each output a test signal for testing the device under test, and according to the test signal A plurality of response signal acquisition units that respectively acquire response signals output from the device under test, and when calibrating the test apparatus, acquire logical values of the test signals output by the two or more test signal output units, respectively. A calibration device including a reference comparator unit that outputs to the response signal acquisition unit serving as a reference, instead of the device under test, and a calibration target in a state where the calibration device is mounted. The test signal output from the test signal output unit is adjusted based on the result obtained by the reference comparator unit. An adjustment unit that adjusts the timing of outputting the, to provide a test device comprising a.

  According to a third aspect of the present invention, there is provided a calibration method for calibrating a test apparatus for testing a device under test, wherein the test apparatus outputs a plurality of tests each for outputting a test signal for testing the device under test. A signal output unit, a plurality of response signal acquisition units for acquiring response signals output from the device under test according to the test signal, and the test signal output unit serving as a reference when the test apparatus is calibrated. A device mounting section for mounting, instead of the device under test, a calibration device including a reference driver section that outputs a logic signal corresponding to the voltage level of the test signal to each of the plurality of response signal acquisition sections. Based on the result of the response signal acquisition unit to be adjusted acquiring the logic signal output from the reference driver unit in a state where the calibration device is mounted. To provide a calibration method wherein the response signal acquiring unit to be adjusted to adjust the timing of acquiring the logic signal.

  According to a fourth aspect of the present invention, there is provided a calibration method for calibrating a test apparatus for testing a device under test, wherein the test apparatus outputs a plurality of tests each for outputting a test signal for testing the device under test. A signal output unit, a plurality of response signal acquisition units that respectively acquire response signals output from the device under test according to the test signal, and two or more test signal output units when calibrating the test apparatus, respectively A device mounting unit for mounting a calibration device including a reference comparator unit that acquires the logical value of the output test signal and outputs the logical value to the response signal acquisition unit serving as a reference; and Based on the result obtained by the reference comparator unit that the test signal output from the test signal output unit to be adjusted with the calibration device mounted. Provides a calibration method for adjusting the timing of outputting the test signal from the test signal output unit to be adjusted.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

FIG. 1 shows a configuration of a test apparatus 10 according to the present embodiment. FIG. 2 shows a functional configuration of the test apparatus 10. FIG. 3 shows an example of the configuration of the test signal output unit 32 and the response signal acquisition unit 34. FIG. 4 shows the configuration of the calibration device 300. FIG. 5 shows a processing flow during calibration of the test apparatus 10 according to the present embodiment. FIG. 6 shows an example of signal output timing and acquisition timing in each step of FIG. FIG. 7 shows a configuration of a calibration device 300 according to the first modification of the present embodiment. FIG. 8 shows an example of a processing flow for adjusting the timings of the plurality of reference driver units 70 and the plurality of reference comparator units 72 of the test apparatus 10 according to this modification. FIG. 9 shows a configuration of a test apparatus 10 according to a second modification of the present embodiment.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  FIG. 1 shows a configuration of a test apparatus 10 according to the present embodiment. The test apparatus 10 tests the device under test 200. The test apparatus 10 includes a main body unit 20 and a device mounting unit 30. The main body unit 20 internally includes a plurality of test modules that supply signals to the device under test 200 and obtain signals from the device under test 200.

  The device mounting unit 30 mounts the device under test 200 when testing the device under test 200. The device mounting section 30 has wiring that connects between the test module in the main body section 20 and the device under test 200. For example, the device mounting unit 30 may be a motherboard, a socket board, or the like.

  FIG. 2 shows a functional configuration of the test apparatus 10. The device mounting unit 30 mounts the calibration device 300 instead of the device under test 200 when the test apparatus 10 is calibrated. The main unit 20 includes a plurality of test signal output units 32, a plurality of response signal acquisition units 34, a power supply unit 36, a timing generation unit 38, a pattern generation unit 40, a comparison unit 42, and an adjustment unit 44. Have.

  The plurality of test signal output units 32 each output a test signal for testing the device under test 200. More specifically, each of the plurality of test signal output units 32 outputs a test signal having a designated waveform at a timing designated by a given timing signal.

  The plurality of response signal acquisition units 34 respectively acquire response signals output from the device under test 200 according to the test signal. More specifically, each of the plurality of response signal acquisition units 34 acquires the logical value of the response signal at the timing (strobe timing) specified by the given timing signal. Note that one test signal output unit 32 and one response signal acquisition unit 34 are connected to the device under test 200 via a common terminal as an example.

  The power supply unit 36 outputs a power supply voltage supplied to the device under test 200 during the test. The power supply unit 36 supplies a power supply voltage to the calibration device 300 via the device mounting unit 30 during calibration. Further, as an example, the power supply unit 36 may supply a power supply voltage to any one of the test signal output units 32 as a drive voltage that determines the voltage level of the test signal. Further, as an example, the power supply unit 36 may supply a power supply voltage as a threshold value for determining the logical value of the response signal to any one of the response signal acquisition units 34.

  The timing generator 38 generates a timing signal for designating the timing for outputting the logic signal and the timing for acquiring the logic signal during calibration. The timing generation unit 38 supplies the generated timing signal to the calibration device 300 via the device mounting unit 30.

  For example, the timing generator 38 supplies a timing signal for designating the timing for outputting a test signal to the device under test 200 to the at least one test signal output unit 32 during testing. In addition, as an example, the timing generator 38 supplies a timing signal designating a timing (strobe timing) for acquiring a response signal output from the device under test 200 to the at least one response signal acquisition unit 34 during a test.

  The pattern generator 40 generates a logic pattern of logic signals output from the calibration device 300 and the test signal output unit 32 to be adjusted during calibration. Furthermore, the pattern generation unit 40 generates an expected value of the logic signal acquired by the calibration device 300 and the test signal output unit 32 to be adjusted. The pattern generator 40 supplies the generated logic pattern to the calibration device 300 or the test signal output unit 32 to be adjusted. Alternatively, the pattern generation unit 40 supplies the generated expected value to the comparison unit 42.

  For example, the pattern generation unit 40 supplies a logic pattern representing the logic of a test signal output to the device under test 200 to at least one test signal output unit 32 during a test. For example, the pattern generator 40 generates an expected value of a response signal output from the device under test 200 during a test.

  The comparison unit 42 compares whether or not the logical value of the logical signal acquired by the calibration device 300 matches the expected value generated by the pattern generation unit 40 during calibration. Alternatively, the comparison unit 42 compares whether the logical value of the logical signal acquired by the response signal acquisition unit 34 to be adjusted matches the expected value generated by the pattern generation unit 40 during calibration. As an example, the comparison unit 42 includes a logical value of the response signal of the device under test 200 acquired by the at least one response signal acquisition unit 34 and an expected value of the response signal generated by the pattern generation unit 40 during the test. Compare whether they match.

  The adjustment unit 44 adjusts the timing at which the test signal output unit 32 to be adjusted outputs a test signal based on the comparison result by the comparison unit 42 during calibration. More specifically, the adjustment unit 44 adjusts the test signal output unit 32 to be adjusted so that the test signal having the specified waveform is output from the pin of the test signal output unit 32 to be adjusted without error at the specified timing. The delay amount of the timing signal given to is adjusted.

  The adjustment unit 44 adjusts the timing (strobe timing) at which the response signal acquisition unit 34 to be adjusted acquires the response signal based on the comparison result by the comparison unit 42 during calibration. More specifically, the adjustment unit 44 gives the timing given to the response signal acquisition unit 34 to be adjusted so that the logical value of the response signal is fetched from the pin of the response signal acquisition unit 34 to be adjusted without error at the designated timing. Adjust the amount of signal delay. The adjustment unit 44 is realized by including any one test signal output unit 32 provided in the main body unit 20 as an example.

  FIG. 3 shows an example of the configuration of the test signal output unit 32 and the response signal acquisition unit 34. As an example, the test signal output unit 32 includes a timing adjustment circuit 52, a flip-flop circuit 54, and a drive circuit 56.

  The timing adjustment circuit 52 delays the timing signal provided from the timing generator 38. The flip-flop circuit 54 acquires a value corresponding to the logical pattern generated by the pattern generator 40. The flip-flop circuit 54 outputs the acquired value at the timing specified by the timing signal delayed by the timing adjustment circuit 52. The drive circuit 56 supplies the signal output from the flip-flop circuit 54 to the device mounting unit 30 as a test signal.

  Here, the timing adjustment circuit 52 adjusts the delay amount by the adjustment unit 44. When the delay amount of the timing adjustment circuit 52 changes, the timing at which the timing signal is given to the flip-flop circuit 54 changes. Thereby, the adjustment unit 44 can adjust the output timing of the test signal by the test signal output unit 32. Further, as an example, the drive circuit 56 is supplied with a power supply voltage from the power supply unit 36 and sets the voltage level of the test signal in accordance with the supplied power supply voltage.

  As an example, the response signal acquisition unit 34 includes a level comparator circuit 62, a timing adjustment circuit 64, and a timing comparator circuit 66. The level comparator circuit 62 receives the response signal from the device mounting unit 30 and outputs the logical value of the response signal. The timing adjustment circuit 64 delays the timing signal given from the timing generator 38. The timing comparator circuit 66 acquires the logical value acquired by the level comparator circuit 62 at the timing of the timing signal delayed by the timing adjustment circuit 64. The timing comparator circuit 66 outputs the acquired logical value to the comparison unit 42.

  Here, the timing adjustment circuit 64 adjusts the delay amount by the adjustment unit 44. When the delay amount of the timing adjustment circuit 64 changes, the timing at which the timing signal is given to the timing comparator circuit 66 changes. Thereby, the adjustment unit 44 can adjust the acquisition timing of the logic signal by the response signal acquisition unit 34. Further, as an example, the level comparator circuit 62 is supplied with a power supply voltage from the power supply unit 36, and sets a threshold value for determining a logical value of the response signal in accordance with the supplied power supply voltage.

  FIG. 4 shows the configuration of the calibration device 300. The calibration device 300 includes a reference driver unit 70, a reference comparator unit 72, and an external connection switch 74.

  When the test apparatus 10 is calibrated, the reference driver unit 70 sends a logic signal corresponding to the voltage level of the test signal output from the test signal output unit 32 serving as a reference to each of the plurality of response signal acquisition units 34. Output. For example, the reference driver unit 70 receives a timing signal from the timing generation unit 38 via a terminal of the calibration device 300 and outputs a logic signal at a timing specified by the received timing signal. For example, the reference driver unit 70 receives a power supply voltage from the power supply unit 36 via the terminal of the calibration device 300 and sets the voltage level of the logic signal to be output.

  The reference comparator unit 72 acquires the logical value of the test signal output by each of the two or more test signal output units 32. As an example, the reference comparator 72 receives a timing signal from the timing generator 38 via the terminal of the calibration device 300 and acquires a test signal at a timing specified by the received timing signal. For example, the reference comparator unit 72 receives a power supply voltage from the power supply unit 36 via the terminal of the calibration device 300 and sets a threshold value for determining the logical value of the received test signal.

  Such a reference driver unit 70 has the same configuration as the test signal output unit 32 shown in FIG. 3 as an example. In addition, the reference comparator unit 72 has the same configuration as the response signal acquisition unit 34 illustrated in FIG. 3 as an example.

  Further, the logic signal output terminal of the reference driver section 70 and the test signal input terminal of the reference comparator section 72 are connected. Accordingly, the reference comparator unit 72 can acquire the logical value of the logical signal output from the reference driver unit 70.

  The external connection switch 74 switches which of the response signal acquisition unit 34 and the test signal output unit 32 the reference driver unit 70 and the reference comparator unit 72 are connected to. The external connection switch 74 receives a signal from the comparison unit 42 via the terminal of the calibration device 300 and switches the connection according to the received signal.

  FIG. 5 shows a processing flow during calibration of the test apparatus 10 according to the present embodiment. FIG. 6 shows an example of signal output timing and acquisition timing in each step of FIG.

  First, in step S <b> 10, the test apparatus 10 mounts the calibration device 300 on the device mounting unit 30. For example, the calibration device 300 is transported to the device mounting unit 30 by the handler device. The adjustment unit 44 executes the following steps S11 to S13 while the calibration device 300 is mounted.

  Next, in step S <b> 11, the adjustment unit 44 determines the timing of the reference driver unit 70 and the reference comparator unit 72 so that the output timing of the logic signal by the reference driver unit 70 matches the acquisition timing of the logic signal by the reference comparator unit 72. Adjust. More specifically, as an example, the adjustment unit 44 switches the external connection switch 74 so as not to connect the reference driver unit 70 and the reference comparator unit 72 to any test signal output unit 32 and response signal acquisition unit 34.

  Then, the adjustment unit 44 adjusts the timings of the reference driver unit 70 and the reference comparator unit 72 based on the result obtained by the reference comparator unit 72 using the logic signal output from the reference driver unit 70. As an example, the adjustment unit 44 provides a timing signal for designating the same timing to the reference driver unit 70 and the reference comparator unit 72 every predetermined period. The adjusting unit 44 gives the reference driver unit 70 a logic pattern in which the logic changes at the timing specified by the timing signal, and repeatedly generates a logic signal having the same waveform every predetermined period. Further, the adjustment unit 44 causes the reference comparator unit 72 to acquire the value of the logic signal at the timing specified by the timing signal.

  Then, as shown in FIGS. 6A and 6B, the adjustment unit 44 at least of the delay amount of the timing adjustment circuit 52 of the reference driver unit 70 and the delay amount of the timing adjustment circuit 64 of the reference comparator unit 72. One of them is sequentially changed in units of a predetermined amount every predetermined period, and the timing of acquiring the logic signal by the reference comparator 72 is adjusted so as to coincide with the change point of the logic value. Thereby, the adjustment unit 44 can match the output timing of the logic signal by the reference driver unit 70 and the acquisition timing of the logic signal by the reference comparator unit 72.

  Next, in step S <b> 12, the adjustment unit 44 adjusts the output timing of the test signal of each test signal output unit 32 in the test apparatus 10. More specifically, as an example, the adjustment unit 44 sequentially selects each of the plurality of test signal output units 32 as an adjustment target, and connects the test signal output unit 32 to be adjusted to the reference comparator unit 72. The external connection switch 74 is switched.

  Subsequently, with respect to the selected test signal output unit 32 to be adjusted, the adjustment unit 44 determines the test to be adjusted based on the result obtained by the reference comparator unit 72 that has output the test signal output from the test signal output unit 32 to be adjusted. The timing for outputting the test signal from the signal output unit 32 is adjusted. As an example, the adjustment unit 44 provides a timing signal and a logic pattern to the test signal output unit 32 and the reference comparator unit 72 to be adjusted, as in step S11.

  Then, as shown in FIGS. 6C and 6E, the adjustment unit 44 sequentially sets the delay amount of the timing adjustment circuit 52 of the test signal output unit 32 to be adjusted in units of a predetermined amount every predetermined period. By changing, the acquisition timing of the logic signal by the reference comparator unit 72 is adjusted so as to coincide with the change point of the logic value. Thereby, the adjustment unit 44 can match the output timing of each of the plurality of test signal output units 32 included in the test apparatus 10 with the acquisition timing of the reference comparator unit 72.

  Next, in step S <b> 13, the adjustment unit 44 adjusts the response signal acquisition timing of each response signal acquisition unit 34 in the test apparatus 10. More specifically, as an example, the adjustment unit 44 sequentially selects each of the plurality of response signal acquisition units 34 as an adjustment target, and connects the response signal acquisition unit 34 to be adjusted to the reference driver unit 70. The external connection switch 74 is switched.

  Subsequently, for the selected response signal acquisition unit 34 to be adjusted, the adjustment unit 44 adjusts the response signal to be adjusted based on the result of the response signal acquisition unit 34 to be adjusted acquiring the logic signal output by the reference driver unit 70. The acquisition unit 34 adjusts the timing for acquiring the logic signal. As an example, the adjustment unit 44 provides a timing signal and a logic pattern to the reference driver unit 70 and the response signal acquisition unit 34 to be adjusted, as in step S11.

  Then, as shown in FIGS. 6D and 6F, the adjustment unit 44 sequentially sets the delay amount of the timing adjustment circuit 64 of the response signal acquisition unit 34 to be adjusted in units of a predetermined amount for each predetermined period. By changing, the acquisition timing of the logic signal by the response signal acquisition unit 34 to be adjusted is adjusted so as to coincide with the change point of the logic value. Thereby, the adjustment unit 44 can match the acquisition timing of each of the plurality of response signal acquisition units 34 included in the test apparatus 10 with the output timing of the reference driver unit 70.

  Through the above processing, the adjustment unit 44 can match the output timings of the plurality of test signal output units 32 included in the test apparatus 10 and the acquisition timings of the plurality of response signal acquisition units 34.

  As described above, according to the test apparatus 10, the plurality of test signal output units 32 and the plurality of response signal acquisition units 34 can be collectively adjusted by mounting the calibration device 300 on the device mounting unit 30. it can. Thereby, according to such a test apparatus 10, it is not necessary to mechanically connect each terminal of the test apparatus to the measurement apparatus one by one using a calibration robot, so that calibration can be completed in a short time. Can do. Further, according to such a test apparatus 10, for example, the calibration device 300 can have the same size as the device under test 200, so that no mechanical interference occurs between the calibration device 300 and the handler device. The handler device does not have to be removed during calibration.

  FIG. 7 shows a configuration of a calibration device 300 according to the first modification of the present embodiment. Since the test apparatus 10 according to this modification employs substantially the same configuration and function as the test apparatus 10 described with reference to FIGS. 1 to 6, members having substantially the same configuration and function are denoted by the same reference numerals, The description is omitted below except for the differences.

  The calibration device 300 according to this modification includes a plurality of reference driver units 70 (70-1, 70-2,...), A plurality of reference comparator units 72 (72-1, 72-2), and a plurality of external devices. A connection switch 74 and an internal connection switch 80 are included.

  In the present embodiment, each of the plurality of reference driver units 70 is associated with each of the plurality of reference comparator units 72 on a one-to-one basis. The logic signal output terminal of the associated reference driver unit 70 and the test signal input terminal of the reference comparator unit 72 are connected.

  In the present embodiment, each of the plurality of external connection switches 74 is associated with each of the plurality of reference driver units 70 on a one-to-one basis. Each of the plurality of external connection switches 74 switches to which response signal acquisition unit 34 and test signal output unit 32 the corresponding reference driver unit 70 and reference comparator unit 72 are connected. As an example, each of the plurality of external connection switches 74 connects the corresponding reference driver unit 70 and the reference comparator unit 72 to the test signal output unit 32 and the response signal acquisition unit 34 that are different from each other.

  The internal connection switch 80 switches which reference comparator unit 72 the one reference driver unit 70 is connected to. Furthermore, the internal connection switch 80 switches which reference driver unit 70 the one reference comparator unit 72 is connected to. The internal connection switch 80 receives a signal from the comparison unit 42 via the terminal of the calibration device 300 and switches the connection according to the received signal.

  FIG. 8 shows an example of a processing flow for adjusting the timings of the plurality of reference driver units 70 and the plurality of reference comparator units 72 of the test apparatus 10 according to this modification. The adjustment unit 44 executes the processes of steps S21 to S23 below in a state where the calibration device 300 according to this modification is mounted.

  First, in step S21, the adjustment unit 44 adjusts the timing of one reference driver unit 70-1 and one reference comparator unit 72-1. As an example, the adjustment unit 44, as in step S11 of FIG. 5, uses one reference comparator unit 72-1 to acquire a logic signal output from one reference driver unit 70-1, and then uses one reference comparator unit 72-1. The timing of the driver unit 70-1 and one reference comparator unit 72-1 is adjusted.

  Next, in step S22, the adjustment unit 44 adjusts the output timing of the logic signal of the reference driver unit 70-2 other than the one reference driver unit 70-1. The adjustment unit 44 switches the internal connection switch 80 so that the other reference driver units 70-2 are sequentially selected one by one and connected to one reference comparator unit 72-1. And the adjustment part 44 selected based on the result acquired by the one reference | standard comparator part 72-1, the logic signal output from the other selected reference | standard driver part 70-2 similarly to step S12 of FIG. The timing for outputting a logic signal from the other reference driver unit 70-2 is adjusted.

  Next, in step S <b> 23, the adjustment unit 44 adjusts the logic signal acquisition timing of the reference comparator unit 72-2 other than the one reference comparator unit 72-1. The adjustment unit 44 switches the internal connection switch 80 so that the other reference comparator units 72-2 are sequentially selected one by one and connected to one reference driver unit 70-1. Then, the adjustment unit 44 selects, based on the result obtained by the other reference comparator unit 72-2 that has selected the logic signal output by the one reference driver unit 70-1, in the same manner as Step S13 of FIG. The reference comparator unit 72-2 adjusts the timing for acquiring the logic signal.

  Through the above processing, the adjustment unit 44 can match the output timings of the plurality of reference driver units 70 and the acquisition timings of the plurality of reference comparator units 72 of the calibration device 300 according to the modification.

  Then, the adjustment unit 44 selects a plurality of test signal output units 32 to be adjusted, and outputs test signals output from the selected plurality of test signal output units 32 to be adjusted to a plurality of reference comparator units 72. The timings at which the plurality of test signal output units 32 to be adjusted output test signals are adjusted in parallel. In addition, the adjustment unit 44 selects a plurality of adjustment target response signal acquisition units 34 and selects a plurality of adjustment target response signal acquisition units 34 that have selected logic signals output from the plurality of reference driver units 70, respectively. The timing at which the plurality of response signal acquisition units 34 to be adjusted acquire logic signals is adjusted in parallel. Thereby, according to the test apparatus 10 which concerns on this modification, calibration can be completed in a shorter time.

  FIG. 9 shows a configuration of a test apparatus 10 according to a second modification of the present embodiment. Since the test apparatus 10 according to this modification adopts substantially the same configuration and function as the test apparatus 10 described with reference to FIGS. 1 to 8, members having the same configuration and function are denoted by the same reference numerals, The description is omitted below except for the differences.

  The test apparatus 10 according to this modification further includes a handler device 82 and a control unit 84. The handler device 82 transports the device under test 200 to the device mounting unit 30 and mounts it on the device mounting unit 30 during the test. In the calibration, the handler device 82 carries the calibration device 300 instead of the device under test 200 to the device mounting unit 30 and mounts it on the device mounting unit 30.

  The control unit 84 controls the main body unit 20 and the handler device 82. For example, the controller 84 controls the handler device 82 to carry and mount the calibration device 300 instead of the device under test 200 during calibration.

  Further, when the response signal acquisition unit 34 cannot acquire the logic signal output from the reference driver unit 70, the control unit 84 controls the external handler device 82 to mount the calibration device 300 on the device mounting unit 30. Let me fix it. Thereby, according to the test apparatus 10 which concerns on this modification, the failure of the calibration process by the connection failure by the device 300 for a calibration can be eliminated.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

DESCRIPTION OF SYMBOLS 10 Test apparatus, 20 main-body part, 30 device mounting part, 32 test signal output part, 34 response signal acquisition part, 36 power supply part, 38 timing generation part, 40 pattern generation part, 42 comparison part, 44 adjustment part, 52 timing adjustment Circuit, 54 flip-flop circuit, 56 drive circuit, 62 level comparator circuit, 64 timing adjustment circuit, 66 timing comparator circuit, 70 reference driver section, 72 reference comparator section, 74 external connection switch, 80 internal connection switch, 82 handler device, 84 control unit, 200 device under test, 300 calibration device

Claims (10)

A test apparatus for testing a device under test,
A plurality of test signal output units each for outputting a test signal for testing the device under test;
A plurality of response signal acquisition units respectively acquiring response signals output by the device under test according to the test signal;
A calibration provided with a reference driver unit that outputs a logic signal corresponding to the voltage level of the test signal output from the test signal output unit serving as a reference to each of the plurality of response signal acquisition units when the test apparatus is calibrated A device mounting unit for mounting the device for use instead of the device under test;
Based on a result of the response signal acquisition unit to be adjusted acquiring the logic signal output from the reference driver unit in a state where the calibration device is mounted, the response signal acquisition unit to be adjusted receives the logic signal. An adjustment unit for adjusting the acquisition timing;
A test apparatus comprising: The calibration device further includes a reference comparator unit that acquires a logical value of a test signal output by each of the two or more test signal output units,
The adjustment unit is configured to adjust the test signal output unit to be adjusted based on a result of the test signal output from the test signal output unit to be adjusted by the reference comparator unit in a state where the calibration device is mounted. The test apparatus according to claim 1, further adjusting a timing at which a test signal is output from the test apparatus. A timing generator for supplying a timing signal for specifying a timing for outputting a test signal to the device under test to at least one test signal output unit;
The reference driver unit receives the timing signal via a terminal of the calibration device, and outputs the logic signal at a timing specified by the timing signal,
The reference comparator unit receives the timing signal via a terminal of the calibration device, and acquires the test signal at a timing specified by the timing signal.
The test apparatus according to claim 2. A power supply unit that outputs a power supply voltage to be supplied to the device under test;
The reference driver unit receives the power supply voltage from the power supply unit via a terminal of the calibration device, sets a voltage level of a logic signal to be output,
The reference comparator unit receives the power supply voltage from the power supply unit via a terminal of the calibration device, and sets a threshold value for determining a logical value of the received test signal. The test apparatus described. The calibration device further includes an external connection switch that switches which of the response signal acquisition unit and the test signal output unit is connected to the reference driver unit and the reference comparator unit,
The adjustment unit sends a signal specifying which of the response signal acquisition unit and the test signal output unit to which the reference driver unit and the reference comparator unit are to be connected from at least one test signal output unit to the external connection. The test apparatus according to claim 2, wherein the test apparatus is supplied to a switch. The calibration device is:
A plurality of the reference driver units and a plurality of the reference comparator units;
An internal connection switch for switching which one of the reference driver units is connected to which of the reference comparator units;
With
In the state where the calibration device is mounted, the adjustment unit connects the one reference driver unit to each of the reference comparator units and outputs a signal output from the one reference driver unit to the reference destination The test apparatus according to claim 2, further adjusting the timing at which the plurality of reference comparator units acquire a test signal based on a result acquired by the comparator unit.   And a control unit that controls an external handler device to remount the calibration device in the device mounting unit when the response signal acquisition unit cannot acquire the logic signal output from the reference driver unit. Item 7. The test apparatus according to any one of Items 1 to 6. A test apparatus for testing a device under test,
A plurality of test signal output units each for outputting a test signal for testing the device under test;
A plurality of response signal acquisition units respectively acquiring response signals output by the device under test according to the test signal;
When calibrating the test apparatus, a calibration device including a reference comparator unit that acquires a logical value of a test signal output from each of the two or more test signal output units and outputs the logical value to the response signal acquisition unit serving as a reference A device mounting portion for mounting instead of the device under test;
With the calibration device mounted, the test signal output from the test signal output unit to be adjusted is output based on the result obtained from the test signal output from the test signal output unit to be adjusted by the reference comparator unit. An adjustment unit for adjusting the timing to perform,
A test apparatus comprising: A calibration method for calibrating a test apparatus for testing a device under test,
The test apparatus comprises:
A plurality of test signal output units each for outputting a test signal for testing the device under test;
A plurality of response signal acquisition units respectively acquiring response signals output by the device under test according to the test signal;
A calibration provided with a reference driver unit that outputs a logic signal corresponding to the voltage level of the test signal output from the test signal output unit serving as a reference to each of the plurality of response signal acquisition units when the test apparatus is calibrated A device mounting section for mounting the device for use instead of the device under test,
Based on a result of the response signal acquisition unit to be adjusted acquiring the logic signal output from the reference driver unit in a state where the calibration device is mounted, the response signal acquisition unit to be adjusted receives the logic signal. Calibration method to adjust the acquisition timing. A calibration method for calibrating a test apparatus for testing a device under test,
The test apparatus comprises:
A plurality of test signal output units each for outputting a test signal for testing the device under test;
A plurality of response signal acquisition units respectively acquiring response signals output by the device under test according to the test signal;
When calibrating the test apparatus, a calibration device including a reference comparator unit that acquires a logical value of a test signal output from each of the two or more test signal output units and outputs the logical value to the response signal acquisition unit serving as a reference A device mounting portion for mounting instead of the device under test;
With
With the calibration device mounted, the test signal output from the test signal output unit to be adjusted is output based on the result obtained from the test signal output from the test signal output unit to be adjusted by the reference comparator unit. Calibration method to adjust timing.

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