JP3216608B2 - Semiconductor test apparatus and storage medium storing program - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test apparatus for judging the quality of a semiconductor integrated circuit and a storage medium storing a program used in the apparatus, and more particularly to a timing skew of a test signal waveform applied to an IC under test. It is about adjustment.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing a configuration of a conventional semiconductor test apparatus. In FIG. 5, reference numeral 8 denotes a timing generation circuit, which generates a pulse serving as a reference for generating a test cycle of an IC under test and various test waveforms. Reference numeral 7 denotes a pattern generation circuit which generates an application pattern to the IC under test and an expected value pattern used for judging pass / fail according to a test program of the IC under test. Reference numeral 9 denotes a waveform shaper which generates the applied pattern and the like into an actual waveform by the reference pulse. Reference numeral 10 denotes a delay element having a variable delay time, which adjusts the timing of applying the generated waveform to the IC under test for each wiring. Reference numeral 11 denotes a driver, which applies the delay-adjusted waveform as a voltage to the IC under test from the terminal 16 for each wiring.

[0004] Reference numeral 4 denotes a comparator, which outputs the output from each driver 11 sequentially switched by a relay 17 to a reference signal Vre.
The difference time between the two is detected by comparing with f. Reference numeral 5 denotes a time measuring unit for measuring the time of the comparison output waveform. 6
Is a correction controller for sequentially adjusting the delay time of each delay element 10 via the relay 18 according to the measured time. Reference numeral 13 denotes a voltage control unit that controls the voltage level of the reference signal Vref. A voltage application circuit 12 applies the voltage of the reference signal Vref to the comparator 4. Here, the wiring system of signals applied to the IC under test such as a driver is generally called a tester pin, and the number of tester pins that can be independently applied is called a tester pin number.

In the above configuration, each driver 11 outputs a signal waveform for performing the test of the IC under test. Normally, however, the output is output at the same timing between the outputs of the drivers on a plurality of tester pins. , A time lag (timing skew) occurs in the actually output waveform. This is caused by differences in transmission systems such as individual differences of used components and wiring specifications in each driver. For this reason, conventionally, it has been necessary to perform timing skew adjustment for adjusting the timing of each output waveform of each driver by the delay element 10.

In the skew adjustment, the output waveform of each driver is compared with a reference signal Vref by a comparator 4, and a time measurement unit 5 measures a shift time of the output waveform with respect to the reference signal. Correction control is performed according to the shift time. The delay element 10
Adjust the delay time. That is, when the shift time is earlier than the reference signal, the adjustment is made later, and when it is later, the adjustment is made earlier. At this time, the measurement of the deviation time of each driver is performed by the relay 17,
The switching is performed for each driver by 18.

[0006]

In the above-described conventional semiconductor test apparatus, the measurement of the time lag is performed by switching the relays one by one.
In recent semiconductor test equipment, there are tester pins of the class of 640 pins per measuring head. Therefore, in the method of serially measuring a shift time by switching a relay, timing skew adjustment takes a very long time and is inefficient. Was.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to shorten the time for adjusting timing skew and improve efficiency.

[0008]

According to another aspect of the present invention, there is provided a semiconductor test apparatus comprising: a plurality of test signals generated by a plurality of test signals; a multiple driver means grouped respectively applied to the plurality of pins of the IC as a voltage, a plurality of comparing the respective reference signals simultaneously and collectively each output of the driver means belonging to any group
Comparison results between signal matrix means and signal matrix means
Based on the delay of the entire driver means belonging to the group
A time measuring means for obtaining a time, wherein the delay time is predetermined
If it is not time for each driver hand belonging to the group
It is characterized in that the timing skew of the stage is adjusted.

According to a second aspect of the present invention, there is provided a semiconductor device according to the first aspect.
In the test equipment , time measuring means is provided for each group.
Each signal matrix means is provided with an arbitrary group.
The output from the driver means is compared with the reference signal for each
Outputs comparison results to time measurement means
2. The semiconductor test apparatus according to claim 1, wherein:

According to a third aspect of the present invention, there is provided a semiconductor testing apparatus.
A plurality of generating means for generating a test signal; and
Using the plurality of generated test signals as voltages,
A plurality of driver means respectively applied to a number of pins;
A plurality of delay means for adjusting the application timing of the driver means
And the output of the driver means is compared with a reference signal,
Comparison means for detecting a shift time and outputting a comparison output waveform
Time measuring means for measuring the time of the comparison output waveform;
Mark on the delay means according to the time measured by the
Semiconductor having correction control means for correcting addition timing
The test device, wherein the driver means is divided into a plurality of groups.
Divided, semiconductor test equipment, furthermore, any group
All the drivers entered collectively from each driver
When the driver output level reaches the level of the reference signal,
A plurality of signal matrix means for outputting a loop signal;
Any of the driver means belonging to the group
First off switch to make or not to make comparison output waveform from force
Replacement means and any of comparison means and signal matrix means
Input or output of the means of
2 switching means, and normally, the second switching means
The output of each signal matrix means is sequentially input to the time measurement means
And the time measuring means
Measure the delay time of the entire driver
If it is not a fixed time, the output of the comparing means to the second switching means
Force to the time measuring means, the first switching means and the ratio
The comparison output of each driver in the group
Waveforms are sequentially produced, and the correction control means
To correct the application timing of each corresponding delay means.
Features.

According to a fourth aspect of the present invention, there is provided a semiconductor device according to the third aspect.
In the test apparatus, the comparing means, the first switching means, the second
Switching means and time measuring means are provided for each group.
It is characterized by that.

According to a fifth aspect of the present invention, there is provided a semiconductor device according to the fourth aspect.
In test equipment, semiconductor test equipment is grouped by group.
Measure the delay time of the entire group
Correcting the application timing of the driver means in the loop
It is characterized by.

According to a sixth aspect of the present invention, there is provided a semiconductor test apparatus comprising:
Generates a predetermined test signal for each signal pin of the IC under test
Means for applying the test signal as a voltage to the IC under test.
Driver means provided for each number pin and grouped
And a timing skew adjustment provided for each driver means.
Delay means for performing adjustment and any driver means
A ratio that compares the voltage with the reference signal and creates a comparison output waveform
Control means and each driver in the group.
When the voltage applied from the inverter means reaches the reference signal,
Signal matrix means for outputting a group signal if
From the comparison output waveform or group signal
Delay time to quasi-signal or
Time measuring means for measuring the delay time of the entire
From the time, the driver means that applied voltage to the comparison means
Correction control means for controlling the corresponding delay means.
A semiconductor test device, which is normally used for
Is a signal that belongs to the group from the group signal
The delay time of the entire driver means is measured sequentially for each group.
If a group with a delay time that is not
In the case of the comparison means, for each driver means in the group
Create a comparison output waveform sequentially and group it with the time measurement
To measure the lag time for each driver means within
It is characterized by.

According to a seventh aspect of the present invention, there is provided a semiconductor device according to the sixth aspect.
In the test apparatus, the time measuring means and the comparing means are grouped.
Group and provide parallel processing for each group.
Features.

[0015] The invention of a semiconductor test apparatus according to claim 8 is as follows.
Generates a predetermined test signal for each signal pin of the IC under test
Means for applying the test signal as a voltage to the IC under test.
Driver means provided for each number pin and grouped
And a timing skew adjustment provided for each driver means.
Semiconductor test equipment having delay means for performing adjustment.
Therefore, semiconductor test equipment must first be installed in multiple
The delay time measurement for each group at the same time.
Next, if the group does not meet the specified performance
Delay means corresponding to each driver means belonging to the group
Delay used for timing skew adjustment of each stage
It is characterized by adjusting the time.

According to a ninth aspect of the present invention, there is provided a recording medium comprising a plurality of recording media .
The process of generating test signals and the grouping
The plurality of test signals are converted into voltages by a plurality of driver means.
Applying each of the plurality of pins of the IC under test to
Belong to any group by multiple signal matrix means
The outputs of the driver means to be
The signal is compared with the reference signal and the signal
Based on the comparison result of
The process of determining the delay time of the entire driver means and the delay time
If it is not the specified time, each of the drivers belonging to the group
To adjust the timing skew of the control means.
A program for performing the program.

According to a tenth aspect of the present invention, there is provided a recording apparatus according to the ninth aspect.
In the medium, time measurement means are provided for each group.
Each signal matrix means
To compare the output from the driver means with the reference signal.
Outputs the comparison results to the time measurement means
And

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of a semiconductor test apparatus according to the present invention, in which parts corresponding to those in FIG. FIG.
The difference from FIG. 5 is that a plurality of signal matrix circuits 1
(A) and (b) and the switching circuits 2 and 3 are provided.

In this embodiment, each driver 11 is divided into a plurality of groups, each driver output in each group is input to the signal matrix circuit 1, and the reference signal Vref
Are simultaneously and simultaneously compared, and the comparison result (group signal) is switched by the switching circuit 2, and the pass / fail judgment is made for each group by the time measurement unit 5 and the correction control unit 6. If the entire group does not satisfy the predetermined performance, the output waveform of each driver in the group is switched by the switching circuit 2,
Switching is performed at 3, and the shift time is measured individually as in the conventional case.

FIG. 2 is a configuration diagram of the signal matrix circuit 1, and FIG. 3 is a timing chart showing the operation of the signal matrix circuit 1. Table 1 is a truth table of the signal matrix circuit 1.

[0021]

[Table 1]

Next, the operation of the above configuration will be described. Various pulses from the timing generator 8 and various patterns from the pattern generator 7 are applied to a plurality of waveform shapers 9. Each waveform shaper 9 generates a test waveform corresponding to an actual use condition for each signal pin of the IC under test. This waveform is applied to the driver 11 through the delay element 10, and the driver 11 applies a voltage specified by the test program to the waveform and applies the voltage to the IC under test as a test signal.

Next, the timing skew adjustment will be described. In FIG. 1, a plurality of drivers 11 are divided into two groups each including a plurality of drivers 11, and the outputs of the drivers 11 in each group are divided into a signal matrix circuit 1
In addition to (a) and (b). Each signal matrix circuit 1
In, when all the driver output levels reach the level of the reference signal Vref, a group signal is output,
It is applied to the time measuring unit 5 via the switching circuit 2. The time measurement circuit 5 measures the output time of the group signal from the time of input of the reference signal, thereby obtaining the delay time of the entire driver 11 of the group.

For example, in the signal matrix circuit 1 (a),
In FIG. 2, outputs D1, D2 to Dn of each driver 11 are shown.
Is applied to the comparator 14 to compare the timing with the reference signal Vref. And as shown in FIG.
When the outputs D1, D2 to Dn reach the reference signal Vref, the comparator 14 outputs D1 ', D2' to D as shift signals.
Output n '. As shown in Table 1, when the outputs of all the comparators 14 are applied to the NAND circuit 15, the NAND circuit 15 outputs a signal T1. By measuring an output time T5 of the signal T1 with respect to a predetermined level, a pass / fail judgment is made for all the drivers of the group belonging to the signal matrix circuit 1 (a).

That is, if the output time T5 is a predetermined time, the adjustment is terminated assuming that the entire driver satisfies the predetermined performance, and the next signal matrix circuit 1
(B) is adjusted in the same manner as above.

When the time T5 is not the predetermined time and the drivers of the group do not satisfy the predetermined performance, the operation of the signal matrix circuit 1 is stopped and the outputs of all the drivers 11 are switched. , The timing skew is adjusted individually for all the drivers in the same manner as in the prior art shown in FIG.

According to the present embodiment, first, the delay times of a plurality of drivers in a group are measured simultaneously,
Only if the group does not meet the required performance,
Since each driver is individually adjusted, the adjustment can be performed efficiently in a shorter time than before.

FIG. 4 shows a second embodiment of the present invention, and portions corresponding to those in FIG. 1 are denoted by the same reference numerals.
In the present embodiment, switching circuits 2, 3, a comparator 4, and a time measuring unit 5 are provided for each of a plurality of groups as shown.

With the above configuration, the signal matrix circuits 1 (a), (b) to (n) can simultaneously measure the delay time by parallel processing, and can adjust the delay time of each delay element 10. Can also be performed at the same time.
Therefore, the adjustment time can be further shortened to increase the efficiency.

When the configuration shown in FIGS. 1 and 4 is realized by a computer system including a CPU and a memory, the memory constitutes a storage medium according to the present invention. The storage medium stores a program for executing a process for performing the above-described operation. As this storage medium,
A semiconductor memory, an optical disk, a magneto-optical disk, a magnetic medium, or the like can be used.

[0031]

As described above, according to the present invention,
Since a plurality of driver outputs are collectively compared with the reference signal simultaneously by the signal matrix unit, the output time of the signal matrix unit is measured, so that the quality of the IC under test can be efficiently determined in one measurement in a short time. It can be determined well.

Thus, for example, in the case of using a recent semiconductor test apparatus having a driver of 640 pins or more per head, if 32 signal matrix circuits are provided and processing is performed for each of 20 pins, there is no delay in timing and there is no delay element. In the best case where it is not necessary to adjust the delay time, the measurement of the delay time only needs to be performed 32 times, and the time for confirming the timing is 1/20 of the conventional one, and the time can be greatly reduced.

In addition, the conventional individual adjustment can be performed, and when there is a driver that does not satisfy the specified performance, switching is performed to adjust the delay element, so that the timing skew can be more reliably adjusted.

Further, by dividing a plurality of drivers into a plurality of groups, even if some of the drivers do not satisfy the specified performance, the number of times of measurement can be reduced to batch processing in all signal matrix circuits and to one signal matrix circuit. The number of measurements is the same as the number of connected drivers.

Further, by performing simultaneous processing in each group, more efficient adjustment can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a semiconductor test apparatus according to the present invention.

FIG. 2 is a configuration diagram of a signal matrix circuit.

FIG. 3 is a timing chart showing an operation of the signal matrix circuit.

FIG. 4 is a block diagram showing a second embodiment of the semiconductor test apparatus according to the present invention.

FIG. 5 is a block diagram of a conventional semiconductor test apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Signal matrix circuit 2, 3 Switching circuit 4 Comparator 5 Time measuring unit 6 Correction control unit 7 Pattern generation unit 8 Timing generation unit 9 Waveform shaper 10 Delay element 11 Driver 12 Voltage application circuit 13 Voltage control circuit 14 Comparator 15 NAND Circuit 16 Terminal 17, 18 Relay Vref Reference signal

Claims (10)

(57) [Claims] 1. A generating means for generating a plurality of test signals, and the plurality of test signals generated by the generating means are defined as voltages.
Group to be applied to the plurality of pins of the IC Te
A plurality of signal Mato comparing divided and multiple driver means which is a reference signal simultaneously and collectively each of outputs of the driver means belonging to any group
Based on the result of comparison between the matrix unit and the signal matrix unit.
When calculating the delay time of the entire driver means belonging to the group
And a measuring unit, wherein when the delay time is not a predetermined time,
Adjust the timing skew of each driver means belonging to
A semiconductor test apparatus characterized by performing. 2. The time measuring means according to claim 1 , wherein
Each signal matrix means is provided with an arbitrary group.
Compare output from driver means and reference signal for each loop
Output the comparison results to the time measurement means.
The semiconductor test apparatus according to claim 1, wherein: A plurality of generating means for generating 3. A test signal, and the voltage a plurality of test signals generated by said generating means
A plurality of pins to be applied to a plurality of pins of the IC under test, respectively.
Driver means and a plurality of delays for adjusting the application timing of the driver means.
Extension means and the output of the driver means are compared with a reference signal,
Comparison means for detecting a shift time and outputting a comparison output waveform
When the time measuring means for measuring the time of the comparison output waveform, the slow depending on the time measured by the time measuring means
Correction control means for correcting the application timing of the
To a semiconductor test apparatus, said driver means is divided into a plurality of groups, the semiconductor test apparatus may further include the in any group
All drivers entered collectively from the driver means
Group when the output level reaches the level of the reference signal
A plurality of signal matrix means for outputting signals, and a driver means belonging to the group to the comparing means.
Switching from which output the comparison output waveform is created
First switching means, and any one of the comparing means and the signal matrix means.
Switching the output of the means to the time measuring means
A second switching means, and normally, each signal matrix means is provided in the second switching means.
Are sequentially input to the time measuring means, and the time
The group signal from the group signal.
Measure the delay time of the entire
If it is not a fixed time, the second switching means makes the comparison
Means for inputting the output of said means to said time measuring means,
The switching means and the comparing means,
The comparison output waveform of each stage is sequentially produced, and
Application of each delay means corresponding to the driver means to the control means
Semiconductor test equipment characterized by correcting timing
Place. 4. The comparison means, the first switching means, the second switching means,
Switching means and time measuring means are provided for each of the groups.
4. The semiconductor test equipment according to claim 3, wherein
Place. 5. The semiconductor test apparatus according to claim 1 , wherein:
Measure the delay time of the entire group
Correct the application timing of the driver means in the loop
The semiconductor test apparatus according to claim 4, wherein: 6. A predetermined test for each signal pin of an IC under test.
Means for generating a signal, and the signal for applying the test signal as a voltage to the IC under test.
Driver means provided for each number pin and grouped
And a timing skew adjustment provided for each driver means.
Delay means for performing adjustment and any driver means
A ratio that compares the voltage with the reference signal and creates a comparison output waveform
Comparing means , provided for each of the groups, and each driver in the group.
When the voltage applied from each stage reaches the reference signal,
If a signal matrix means for outputting a group signal, respectively based on the said comparison output waveform or group signal
Delay time for quasi-signal or belongs to the group
Time measuring means for measuring the delay time of the entire driver means
And the voltage applied to the comparing means from the time difference.
Correction control means for controlling the delay means corresponding to the delay means.
And a step, wherein the semiconductor test apparatus is normally provided with the time measuring means.
All driver means belonging to the group from the group signal
The body delay time is measured sequentially for each group,
If a group whose interval is not the predetermined time is detected,
The comparison means are ordered for each driver in the group.
The next comparison output waveform is created, and the time
Measure the delay time for each driver in the loop.
A semiconductor test apparatus. 7. The time measuring means and the comparing means,
It is provided for each group and performs parallel processing for each group.
7. The semiconductor test apparatus according to claim 6, wherein: 8. A predetermined test for each signal pin of an IC under test.
Means for generating a signal, and the signal for applying the test signal as a voltage to the IC under test.
Driver means provided for each number pin and grouped
And a timing skew adjustment provided for each driver means.
Semiconductor test equipment having delay means for performing adjustment.
Therefore, the semiconductor test apparatus first has a plurality of drivers in a group.
The delay time measurement for each group at the same time.
Next, if the group does not meet the specified performance
Corresponding to each driver means belonging to the group.
Used to adjust the timing skew of each delay means
Semiconductor test equipment characterized by adjusting delay time
Place. 9. A process for generating a plurality of test signals.
And a plurality of grouped driver means.
Apply test signal as voltage to multiple pins of IC under test
Process and apply to any group by multiple signal matrix means
The outputs of the driver means to be
The process of comparing with the quasi-signal and the comparison result of the signal matrix means by the time measuring means
Based on the driver means belonging to the group
Processing for obtaining a delay time , and when the delay time is not a predetermined time,
Adjust the timing skew of each driver means belonging to
Processing and the program that implements the
Recording medium. 10. The time measuring means, for each of the groups
And each signal matrix means has an arbitrary group.
Compare output from driver means and reference signal for each loop
And output the comparison results to the time measurement means.
The program according to claim 9, wherein the program is recorded.
recoding media.