JPH1026655A - Testing apparatus for lsi - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a testing apparatus, for an LSI, by which a multipin LSI can be tested in the small number of test pins and which is low-cost. SOLUTION: A plurality of test patterns are set in such a way that output pins (pout) 1, 2, 3, 4 from which an expected value is to be obtained for every test pattern do not compete, and the output pins 1, 2, 3, 4 from which expected outputs are obtained by the respective test patterns are changed over by an output changeover part 25 so as to be fetches by one test pin. As a result, even when the number of pins at a test is small as a whole, a multipin LSI can be tested.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI test apparatus for inputting test input data to a plurality of input pins of an LSI and comparing the output data output from an output pin with an expected value to perform a function test. In particular, the present invention relates to an LSI test apparatus that is optimal for a functional test of an LSI having a large number of pins.

[0002]

2. Description of the Related Art A functional test of an LSI is performed by testing the L function to be tested.
This is performed by inputting test input data to the SI and comparing output data with its expected value. The test pattern is for confirming whether or not the function of the LSI operates normally under a predetermined operation condition. An example of the input data is shown in FIG. The expected output value is described in the same manner. In a conventional LSI test apparatus, as shown in FIG. 10, the output buffers 31 ₁ , 31 ₂ , 3
1 _3, 31 _4, output from ... pin (pout) 1,2,3,
Comparators 22 ₁ , 22 ₂ , 22 which take in output data output via
There are multiple test pins including ₃ , 22 ₄ , ...

[0003]

The conventional test apparatus is:
Since each of the plurality of test pins has a comparison unit and the like,
The cost per pin (one channel) is high. Therefore,
If the number of pins of the tester is increased in response to the increase in the number of pins of the LSI, the tester becomes extremely expensive.

An object of the present invention is to provide an inexpensive LSI test apparatus capable of testing a multi-pin LSI with a small number of test pins.

[0005]

A first L according to the present invention is provided.
An SI test apparatus is an LSI test apparatus having a plurality of drive pins for supplying test input data to the LSI and a plurality of test pins for receiving output data obtained from the LSI. Test pattern generating means for generating a plurality of test patterns each including an expected value corresponding to data so that an output pin of an LSI from which an expected value is to be obtained is different for each test pattern;
And an output switching means for switching the output pin and connecting to one test pin.

In a second LSI test apparatus according to the present invention, the test pattern generating means may generate the plurality of test patterns so that the input pins of the LSI to which test input data are to be applied are different for each test pattern. And input switching means for switching and connecting a drive pin to a plurality of input pins of the LSI for each of the test patterns.

A third LSI test apparatus according to the present invention is characterized in that the drive pin and the test pin are constituted by a common I / O pin, and further provided with function switching means for switching the function of the I / O pin. Features.

Normally, even if the LSI as a whole has a large number of output pins, the expected value is not always expected for all the output pins for each test pattern. Further, actually, a test pattern is created in consideration of a failure analysis and the like, and therefore the number of output pins expected in one test pattern is smaller than the number of output pins of the entire LSI.
According to the first LSI test apparatus of the present invention, paying attention to this point, the plurality of test patterns generated by the test pattern generating means do not compete with each other for the output pins from which expected values are to be obtained for each test pattern. The output pins, which are set as described above and obtain the expected output according to each test pattern, are switched by the output switching means and are taken into one test pin. Therefore, even if the number of pins of the entire tester is small, it is possible to test the multi-pin LSI.

According to the second LSI test apparatus of the present invention, the plurality of test patterns generated by the test pattern generating means do not conflict with the input pins to which the test input data is applied for each test pattern. The input pins which are set as described above and to which the test input data is supplied by each test pattern are switched by the input switching means, and the test input data is supplied from one drive pin. Therefore, the number of drive pins of the tester can be reduced.

Further, according to the third LSI test apparatus of the present invention, the function of the I / O pin is switched by the function switching means according to each of the test patterns, so that the number of pins of the tester is further reduced. It can be used for testing a multi-pin LSI.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an LSI tester according to one embodiment of the present invention.

This LSI tester is composed of a measurement system for measuring the characteristics of the LSI 1 which is a device under test and a control system for controlling the same, and controls the input of control information, the input and output of test programs and the output of test results. Input / output device 2 to perform
And a storage device 3 for storing software such as system software and test programs and data of test results
And

The control system of the LSI tester includes a CPU 11
The test pattern is generated by the pattern generator 12 based on the signal from the controller, and the waveform is shaped by the formatter 14 based on the timing signal from the timing generator 13. The voltage level of this pattern is determined by the pin electronics unit 15 and applied to the input pin of the LSI 1. At this time, the programmable power supply 16
Supplies a bias voltage to the LSI 1 based on the signal from the LSI.

On the other hand, in the measurement system of this LSI tester, the pin electronics section 15 compares the level of the output data from the LSI 1, and the pattern comparator 17 compares the expected value from the pattern generator 12 with the output data "1". The logical comparison of the “0” pattern is performed. At this time, the timing at which the output level from the LSI 1 is compared with the expected value is designated based on a strobe signal from the timing generator 13. Similarly, by repeating such an operation several times, the quality of the LSI 1 is determined. If there is a mismatch between the output data from the LSI 1 and the expected value as a result of the pattern comparison, the information is sent to the fail analysis memory 18.

The pin electronics section 15 includes the LSI 1
Drives 2 that supply test input data to
11 ₁ , 21 ₂ , ..., 21 _n (connected to drive pins)
And a plurality of comparators 22 _1, 22 ₂ which receives the output data from the LSI 1, ..., and a 22 _n (connected to the test pins). The level setting in the drive 21
The input level setting unit 23 performs the processing based on the signal from the CPU 11 that has been D / A converted by the D / A converter 19. The setting of the determination level in the comparator 22 is performed by the output comparison level setting unit 24 based on the signal from the CPU 11 that has been D / A converted by the D / A converter 19.

In this embodiment, the test can be performed even when the number of test pins of the tester is smaller than the number of output pins of the LSI 1 to be tested. Therefore, in this embodiment, a plurality of test patterns from the test pattern generator 12 are generated such that the output pin of the LSI 1 from which an expected value is to be obtained differs for each test pattern. A specific example will be described later. Output switching means is provided for switching the output pin of the LSI 1 for each test pattern and connecting the output pin to one test pin of the tester.

FIG. 2 is a diagram showing a detailed configuration of a connection portion between the LSI 1 and the pin electronics section 15 for one test pin of the tester. Pseudo test pins (ptst) 1, 2, 3, 4, of pin electronics section 15
.. Represent output buffers 31 ₁ , 31 ₂ , 31 ₃ ,
The output data output from the output pins 31 ₄ ,... Via the output pins 1, 2, 3, 4,. At this time, the output switching unit 25, which is an additional part of the tester main unit, switches signals input via the pseudo test pins 1, 2, 3, 4,. 26.

FIG. 3 is a diagram showing an example of the configuration of the output switching unit 25. As the signal from the CPU 11, for example, control information added to each test pattern on the program can be used. At this time, the shift register 41
When a reset (“0000”) is applied at the time of power ON and control information is input, the value is set to “0001”, and then, based on the timing signal TM from the timing generator 13, the value is sequentially changed for each test pattern. shift. Thereby, the switch 42 is connected to the shift register 41
ON / OFF switching based on the output from.

When the internal circuit 32 is composed of a plurality of circuit blocks A, B and C independent of each other as shown in FIG. 4, in this embodiment, it is necessary to specify which circuit block has a defect. Or, in order to facilitate creation of a test pattern, a test is performed by creating a test pattern for each circuit block.

Further, even when the internal circuit 32 is composed of a plurality of circuit blocks that are not independent of each other, a test can be performed by creating a test pattern for each circuit block. That is, as shown in FIG. 5, the internal circuit 32 includes a ROM (Read Only Memory) 51 and a logic unit 52.
And external ROM when actually using
Even if it is not necessary to directly access the memory 51, it is difficult to test a large-capacity memory. Therefore, a terminal for accessing the ROM 51 is provided, and the ROM 51 and the logic unit 52 can be tested with different test patterns without conflicting output pins. Testing can be done. As described above, even when the internal circuit 32 includes a plurality of circuit blocks that are not independent from each other, a plurality of test patterns that do not cause output pins to compete can be used.

FIG. 6 is a diagram showing a specific example of the circuit blocks A and B of FIG. 3 and an example of a test pattern for these circuit blocks A and B. The test pattern A is for testing the circuit block A. At this time, the input pins (pins) 4, 5, 6, 7 and the output pins 2 of the circuit block B are used.
Is not used. When a test based on the test pattern A is performed, the output switching unit 25 causes the circuit block A
Are connected to the internal test terminal 26 by switching. On the other hand, the test pattern B is for testing the circuit block B, and at this time, the input pins 1, 2, 3 and the output pin 1 of the circuit block A are not used. When the test using the test pattern B is performed, the output switching unit 25 switches the output pin from which the output of the circuit block B is obtained to the internal test terminal 26.

According to this embodiment, the pattern generator 12
Are set so that output pins for which expected values are to be obtained do not conflict with each other for each test pattern, and output pins for which expected outputs are obtained by each test pattern are switched by the output switching unit 25. , Taken into one test pin. Therefore, even if the number of pins of the entire tester is small, it is possible to test a multi-pin LSI such as 128 pins.

As shown in FIG. 6, when the input pin of the LSI to which the test input data is applied is different for each test pattern, the drive 21 of the pin electronics unit 15 must be shared as shown in FIG. Can also. That is, the plurality of test patterns generated by the pattern generator 12 are set so that the input pins 1, 2, 3, and 4 to which the test input data should be applied do not conflict with each other for each test pattern, and the drive pin (pdr) 1 , 2, 3, and 4 are switched by the input switching unit 27, the input pins 1 and 2 of the LSI
2, 3, and 4 are switched and connected to the internal drive terminal 28, and test input data is supplied from the internal drive terminal 28 to any one of the input pins 1, 2, 3, and 4.

In the embodiment described above, the drive pins 1 and
Although a case has been described where the functions are divided into 2, 3, and 4 and the test pins 1, 2, 3, and 4, respectively, the drive pin and the test pin may be configured by a common I / O pin. In this case, as shown in FIG. 8, a function switching unit 62 for switching the function of the I / O pin 61 is provided. Thus, the number of pins of the tester can be further reduced.

[0025]

As described above, according to the present invention,
The plurality of test patterns generated by the test pattern generating means are LS for which an expected value is to be obtained for each test pattern.
The output pins of I are set so as not to compete with each other, and the output pins from which the expected output is obtained by each test pattern are switched by the output switching means and taken into one test pin, so that the total number of pins of the tester is small. Also, a multi-pin LSI can be tested.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an LSI tester according to one embodiment of the present invention.

FIG. 2 is a diagram illustrating a detailed configuration of a connection portion between an LSI and a pin electronics unit.

FIG. 3 is a diagram illustrating an example of a configuration of an output switching unit.

FIG. 4 is a diagram showing an example in which an LSI tester is applied to a function test.

FIG. 5 is a diagram showing another example in which the LSI tester is applied to a function test.

FIG. 6 is a diagram showing an example of a test pattern in the embodiment.

FIG. 7 is a diagram showing a main configuration of a pin electronics unit according to another embodiment of the present invention.

FIG. 8 is a diagram showing a main configuration of a pin electronics unit according to still another embodiment of the present invention.

FIG. 9 is a diagram illustrating an example of test input data.

FIG. 10 is a diagram showing a detailed configuration of a connection portion between an LSI and a conventional pin electronics unit.

[Explanation of symbols]

1: LSI, 15: Pin electronics section, 22 _1-
22 ₄ ··· Comparator, 25 ··· Output switching unit, 31 _{1 to} 3
1 ₄ ... output buffer.

Claims (3)

[Claims] 1. An LSI test apparatus comprising: a plurality of drive pins for supplying test input data to an LSI; and a plurality of test pins for receiving output data obtained from the LSI. Test pattern generating means for generating a plurality of test patterns composed of expected values corresponding to the test patterns such that output pins of an LSI from which expected values are to be obtained are different for each test pattern; An LSI test apparatus comprising: output switching means for switching an output pin and connecting the output pin to one test pin. 2. The test pattern generating means generates the plurality of test patterns such that input pins of an LSI to which test input data are applied are different for each test pattern. 2. The LSI test apparatus according to claim 1, further comprising input switching means for switching and connecting a drive pin to a plurality of input pins of said LSI. 3. The LSI according to claim 1, wherein the drive pin and the test pin are configured by a common I / O pin, and further comprising function switching means for switching a function of the I / O pin. Testing equipment.