JPH05281292A - Ic tester using ad circuit - Google Patents

Abstract

PURPOSE:To test a DUT speedily using an A/D circuit for an IC tester. CONSTITUTION:A driver 3 feeds a test pattern to each input pin of a DUT 10 and an A/D circuit 4 receives the output of the DUT 10. A strobe judging circuit 5 receives the output of the A/D circuit 4 and judges the output result of the DUT 10. The A/D circuit 4 is provided with an A/D converter which receives the output of the DUT 10, an 'H' limit comparator and an 'L' limit comparator both of which receive the output of the A/D converter, an OR gate which receives the output of the 'H' limit comparator/'L' limit comparator, an FF which receives the output of the OR gate, an 'H' limit data memory, an 'L' limit data memory, and an interface circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC tester for testing an IC such as an IC for driving a liquid crystal display device having a multi-pin and having a multi-value level output by combining input signals at high speed. Is.

[0002]

2. Description of the Related Art The structure of an IC tester according to the prior art will be described with reference to FIG. In FIG. 4, 1 is a timing generation circuit, 2 is a pattern generation circuit, 3 is a driver, 5 is a strobe determination circuit, 6 is a comparator, 7 is a VOH / VOL power supply,
10 is a DUT. The timing generation circuit 1 sends a timing signal to the pattern generation circuit 2 and the strobe determination circuit 5 to operate the pattern generation circuit 2 and the strobe determination circuit 5 in synchronization.

The pattern generation circuit 2 generates a plurality of test patterns and sends a logic signal of "1" or "0" to the driver 3. The driver 3 in FIG. 1 is illustrated as having two outputs. The driver 3 adds a necessary test pattern to the DUT 10. The output voltage of the driver 3 is preset by a power supply (not shown).

The comparator 6 outputs the output signal of the DUT 10 and VO.
Compare the VOH and VOL voltages of the H and VOL power supply 7,
It outputs "H" and "L" signals. VOH / VOL power supply 7
Outputs the voltage VOH.VOL according to the program of the tester CPU (not shown). Strobe determination circuit 5
Receives the output of the comparator 6 as an input and uses the timing generation circuit 2
Thus, it is determined whether the output signal of the DUT 10 is the expected output at the timing synchronized with the test pattern of the pattern generation circuit 4.

[0005]

In FIG. 4, since one output for one input is judged by the comparator 6, the number of output terminals is large, and the driving IC of the liquid crystal display element in which the output voltage changes depending on the combination of the input signals. In the case of such a DUT, the number of tests is increased to measure its characteristics. For example, DU
When the output of T10 has 64 gradations depending on the combination of input signals, a test of 64 times or more is required for each pin. In order to realize this, the voltage VOH / VOL of the VOH / VOL power supply 7 is changed when one measurement is completed and this is repeated for each gradation, so that the measurement takes time. The present invention includes a comparator 6 and a VOH / VOL power supply 7
The purpose of the present invention is to provide an IC tester that employs an AD circuit instead of, and tests a DUT at high speed.

[0006]

In order to solve this problem, according to the present invention, a timing generation circuit 1 for generating a timing signal, a pattern generation circuit 2 for generating a test pattern, and a test pattern are input, and a DUT 10 is used. Driver 3 that adds a test pattern to each input pin of
AD circuit 4 that receives the output of UT 10, and AD circuit 4
Of the DUT 10 and the strobe determination circuit 5 for determining the output result of the DUT 10.
A / D converter 4B having the output of 10 as input, and "H" limit comparator 4C having the output of A / D converter 4B as input
・ O with the output of "L" limit comparator 4D and "H" limit comparator 4C / "L" limit comparator 4D as input
R gate 4E and F that receives the output of OR gate 4E
F4F, "H" Limit data memory 4H, "L"
Limit data memory 4J and interface circuit 4
M, the pattern generation circuit 2 and the strobe determination circuit 5 are operated in synchronization by the timing signal of the timing generation circuit 1, the output of the DUT 10 is A / D converted, and the “H” limit comparator 4C and “L” are output. Limit comparator 4D
The data corresponding to the output level of the driver 3 is input to each pin of the “H” limit data memory 4H and the “L” limit data memory 4J, and the address is set according to the instruction of the interface circuit 4M. The data is input to the “H” limit comparator 4C and the “L” limit comparator 4D for comparison, and is input to the determination result memory 4G and the OR gate 4E to the FF4F.
The output of F is set to fail.

[0007]

Next, the configuration of the IC tester according to the present invention is shown in FIG.
Will be explained. Reference numeral 4 in FIG. 1 is an AD circuit, and the others are the same as those in FIG. That is, FIG. 1 is the VOH of FIG.
The AD circuit 4 is connected instead of the VOL power supply 7 and the comparator 6.

Next, the structure of the AD circuit 4 will be described with reference to FIG. 2A is a buffer amplifier, 4B is an A / D converter, 4C is an "H" limit comparator, 4D is an "L" limit comparator, 4E is an OR gate, 4F is an FF, 4G is a decision result memory, 4H. Is "H" limit data memory, 4J
Is an “L” limit data memory, 4K is an A / D conversion data memory, 4L is a memory address control, and 4M is an interface circuit.

The output of the DUT 10 is input to the buffer amplifier 4A and output from the buffer amplifier 4A to the A / D converter 4B. The buffer amplifier 4A has a sufficiently high input impedance with respect to the output impedance of the DUT 10, and reduces the error due to the load effect during measurement.

The A / D converter 4B constitutes a circuit so as to operate in synchronization with a test pattern applied to the DUT 10. As the A / D converter 4B, one that operates at the same speed as the test pattern or higher is used, and the logic circuit determines the digitally converted output voltage. As a result, the change of the value of the VOH / VOL power supply 7, which conventionally takes a few ms per test, is eliminated, and the test pattern speed can be tested at 100 ns, for example.

The A / D converter 4B converts the analog signal output of the DUT 10 into a digital signal. The conversion speed is faster than the pattern speed in order to synchronize with the driver pattern. For example, when measuring in synchronization with a 10MHz driver pattern, the conversion speed of the A / D converter 4B is 20M.
Set to about Hz.

"H" limit data memory 4H and "L"
The limit data memory 4J is the interface circuit 4
It is connected to a tester CPU (not shown) via M, and limit data for PASS / FAIL determination of a test for each pin specified by a test program or for each input gradation is written in advance.

The "H" limit comparator 4C uses the digital data from the A / D converter 4B as the A input and the output of the "H" limit data memory 4H as the B input to compare the magnitude relationship, and the A input> B input When output. The "L" limit comparator 4D uses the digital data from the A / D converter 4B as the A input and the output of the "L" limit data memory 4J as the B input to compare the magnitude relationships, and outputs when A input <B input. ..

The "H" limit comparator 4C and the "L" limit comparator 4D are digital comparators, and numerically process the output bit number n of the A / D converter 4B. This gives D
The output voltage of each pin of the UT 10 is compared with the determination value specified by the program for each input gray level to determine pass / fail. The outputs of the “H” limit comparator 4C and the “L” limit comparator 4D are written into the determination result memory 4G and stored by the FF 4F. If there is at least one failure in the measurement result, the FAIL signal is output and DU is output.
T10 is determined to be defective.

The memory circuits 4G to 4K are controlled by the memory address control 4L in synchronization with the driver pattern synchronizing signal. Therefore, the DUT 10 can be tested at the speed of the driver pattern signal.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the operation of FIG. 2 will be described with reference to the time chart of FIG. Figure 3a shows the driver pattern,
The patterns P1 to P5 are illustrated. Actually, the patterns P1 to P5 generate different patterns. FIG. 3A shows the output of the DUT 10, and the output level changes stepwise for each driver pattern shown in FIG. In Figure 3a,
The output of the DUT 10 is synchronized with the driver pattern, but there is a delay due to the operating time of the DUT 10.

FIG. 3C is a waveform diagram of the AD trigger signal.
A trigger signal is output when the output of FIG.
A / D conversion is performed at the timing of the trigger signal, and the conversion result is "H" limit comparator 4C and "L" limit comparator 4D.
Compare with limit data by and write to memory. FIG. 3D is data showing the addresses of the memories 4G to 4K, and the addresses sequentially move in synchronization with the driver pattern of FIG.

The data processing after A / D conversion is performed next by A / D
It must be finished before it is converted. Memory 4G
The total processing time is the sum of the reading speed of the memory of 4K and the speed of the comparators 4C and 4D, and the A / D time. The processing time is T1 in FIG.

For example, when the A / D conversion time is 50 ns, the memory time is 25 ns, and the comparison time is 25 ns, the total is 100 ns.
It becomes ns and can be measured in synchronization with the 10 MHz test pattern. In addition, the output of the A / D converter 4B is
By storing it in the D conversion data memory 4K, A /
The input voltage of the D converter 4B can be read out later as a numerical value. FF4F is one FAIL in all tests
If it is determined that "1" is output. This speeds up data processing.

[0020]

According to the present invention, since the AD circuit is used, all pins of the DUT can be simultaneously judged at a speed synchronized with the pattern. Therefore, 1
The IC can be tested at a speed of 00 times to 1000 times or more.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an IC tester according to the present invention.

FIG. 2 is a configuration diagram of an AD circuit in FIG.

FIG. 3 is a time chart of FIG.

FIG. 4 is a configuration diagram of an IC tester according to a conventional technique.

[Explanation of symbols]

 1 timing generation circuit 2 pattern generation circuit 3 driver 4 AD circuit 4B A / D converter 4C “H” limit comparator 4D “L” limit comparator 4E OR gate 4F FF 4H “H” limit data memory 4J “L” limit Data memory 4M Interface circuit 5 Strobe determination circuit 10 DUT

Claims (1)

[Claims] 1. A timing generation circuit (1) for generating a timing signal, a pattern generation circuit (2) for generating a test pattern, and the test pattern as an input, and the test pattern for each input pin of a DUT (10). A strobe judgment circuit (D) that determines the output result of the DUT (10) by inputting the driver (3) that adds the output, the AD circuit (4) that receives the output of the DUT (10), and the output of the AD circuit (4) 5) and AD circuit (4) has an A / D converter (4B) that receives the output of DUT (10) and an "H" that receives the output of A / D converter (4B). Limit comparator (4C), "L" limit comparator (4D)
And "H" limit comparator (4C), "L" limit comparator
OR gate (4E) that receives (4D) output and OR gate
FF (4F) that inputs (4E) output, “H” limit data memory (4H), and “L” limit data memory (4J)
And the interface circuit (4M), the pattern generation circuit (2) and the strobe determination circuit (5) are operated in synchronization by the timing signal of the timing generation circuit (1), and the output of the DUT (10) is A / D-convert and input to "H" limit comparator (4C) and "L" limit comparator (4D)
Input the data corresponding to the output pattern of (3) to each pin of “H” limit data memory (4H) and “L” limit data memory (4J), and set the address by the instruction of the interface circuit (4M). , Corresponding data is input to “H” limit comparator (4C) and “L” limit comparator (4D) for comparison, input to judgment result memory (4G) and OR gate
An IC tester using an AD circuit, which inputs (4E) to FF (4F) and outputs the output of FF (4F) as a fail signal.