JPH04236372A - Testing apparatus for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the time of a characteristic test, especially, the time of collecting shmoo plot by digitalizing the output data from a semiconductor integrated circuit device at a high speed to once store the same and subsequently subjecting the data to digital processing to judge the quality of the semiconductor integrated circuit device. CONSTITUTION:In a semiconductor integrated circuit testing apparatus 5 judging the quality of a semiconductor integrated circuit device by comparing the signal outputted from a semiconductor memory device with an expected value, a fast A/D converter 15 samples the signal outputted from the semiconductor integrated circuit device at a high speed to convert the same to a digital signal. A digital comparator 17 compares the digital signal from the fast A/D converter 15 with an expected value. A fast buffer memory 19 temporarily stores the comparing result of the digital comparator 17 and an operation apparatus 20 forms AND between the comparing result and the data in the fast buffer memory 19. A large capacity memory 24 stores the operation result of the operation apparatus 20. By investigating the data in the large capacity memory 24, the quality of the semiconductor integrated circuit device is judged.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit testing device for determining the quality of semiconductor integrated circuit devices such as semiconductor memory devices.

0002

2. Description of the Related Art FIG. 6 is a block diagram showing the main components of a conventional semiconductor integrated circuit testing apparatus. FIG. 7 is a diagram for explaining the operation of the comparator in FIG. 6, FIG. 8 is a configuration diagram of the digital comparator in FIG. 6, and FIG. 9 shows the results of a characteristic test of a semiconductor memory device. Illustrated diagrams, Figure 10, Figure 1
1 is a diagram for explaining the time required for the above characteristic test.

In FIGS. 6 to 11, 1 is a semiconductor memory device as a semiconductor integrated circuit device, 2 is a data output pin of the semiconductor memory device 1, and 3 is data output from the data output pin 2. , 4 is a signal propagation line for propagating the data 3, 5 is a semiconductor integrated circuit testing device, and 6a and 6b are inside the semiconductor integrated circuit testing device 5 to transmit the data.
7 is a strobe point which gives time for the comparators 6a and 6b to perform the comparison; 8 is a strobe point in the comparator 6a that compares the voltage level of the data with a constant voltage level; Threshold level Voh for comparison with the voltage level of data 3; 9 is in the comparator 6b; threshold level Vol, 10a, 10b is in the comparator 6b for comparison with the voltage level of data 3;
11 is a digital comparator which receives the outputs 10a and 10b and determines whether the data is as expected; 12 is inside the digital comparator 11 and outputs the outputs 10a and 10b; 10b is a selection circuit for selecting either output; 13 is the digital comparator 1;
An expected value 14 is used as a criterion for the test judgment in 1 or as a selection criterion for the selection circuit 12, and is located inside the digital comparator 11 and is a data output from the selection circuit 12. This is a comparison/judgment circuit that compares the expected value 13 with the expected value 13.

[0004] First, the operation of determining pass/fail on the test results of a semiconductor integrated circuit device tested by a semiconductor integrated circuit tester will be explained using an example in which a semiconductor memory device having a memory capacity of 1 Mbit is tested.

When data is read from one memory cell (not shown) in the semiconductor memory device 1, data 3 is output from the data output pin 2. This output data 3 is
The signal is sent to the comparators 6a and 6b of the semiconductor integrated circuit testing device 5 via the signal propagation line 4, and at the time of the preset strobe point 7, the comparator 6a has a voltage higher than the preset threshold level Voh8. In the case of the comparator 6b, it is similarly determined whether the voltage is lower than a preset threshold level Vol9. Note that the threshold levels Voh8 and Vol9 are supplied from a dedicated level generation circuit (not shown).

[0006] For example, in the comparator 6a, the determination is made using data.
If the comparator 3 is higher than the threshold level Voh8, it is set to "1", otherwise it is set to "0", or the comparator 6
Also in b, data 3 is at the threshold level Vo
If it is lower than l9, it outputs "0", otherwise it outputs "1". In this case, the read memory cell holds the logical value "H" as data, and the level of data 3 output from data output pin 2 is sufficiently higher than the threshold level Voh8. Assuming that the level is high, the output 10a of the comparator 6a is "1", and the output 10a of the comparator 6a is "1".
The output 10b of b also becomes "1".

[0007] Next, the outputs 10a and 10a of the comparators 6a and 6b,
10b is sent to the digital comparator 11 and enters the selection circuit 12 inside, where either the output 10a or 10b is selected depending on the value of the expected value 13 (the generation circuit is not shown), and the next comparison is made. The signal is sent to circuit 14. Expected value 13
corresponds to the logical value (“H” or “L”) of data that would be output by the semiconductor integrated circuit testing device 5, assuming that the test results of the tested semiconductor integrated circuit device are correct. This is data that has a value (“1” or “0”). Therefore, the selection circuit 12 determines that the expected value 13 is “
If it is “1”, output 10a, if “0”, output 10b
Select.

[0008] Also, in this case, the expected value 1
3 is "1", the output of the comparator 6a is 10.
a (data value is "1") is selected. Next, the comparison/judgment circuit 14 receives the data output from the selection circuit 12.
The output data 3 of the semiconductor integrated circuit device is compared with the expected value 13, and if they are the same, it is determined that the output data 3 of the semiconductor integrated circuit device is correct (good), and if not, it is determined that it is incorrect (defective). In this case, the read data of the memory cell is determined to be correct (good).

The above operations are carried out for each memory cell, and
If all the memory cells are determined to be good, the test determination result of the semiconductor memory device 1 is determined to be good. On the other hand, if even one memory cell is determined to be defective, in order to shorten the test time, the test is stopped as soon as the determination is made, even if there are memory cells that have not been determined. The test result of the semiconductor memory device 1 is determined to be defective.

Next, a method for testing the characteristics of the semiconductor memory device 1 will be explained. One of the characteristic tests for the semiconductor memory device 1 is the Schmumm plot. This is done by changing two of the several test condition parameters (power supply voltage, input timing of various signals, etc.) at regular intervals, conducting tests under each test condition, and checking the quality of the test. The characteristics of the semiconductor memory device 1 are investigated by plotting the results of the defect determination in a matrix with the above two condition parameters on the vertical and horizontal axes.

FIG. 9 shows an example, and the power supply voltage applied to the semiconductor memory device 1 is plotted on the vertical axis.
The horizontal axis is the time of strobe point 7, which is the timing for comparing the output 3 of each memory cell with the expected value 13. 26 points changed, total 11 points x 26 points = 2
Tests were conducted for 86 points under each test condition, and if the results were good, an asterisk mark "*" was plotted, and if the results were poor, a blank was plotted.

Next, FIG. 10 shows the results of trial calculations of the execution time of the Schmoe plot for each memory capacity of the semiconductor memory device 1. The conditions for the trial calculation are a marching pattern in which each memory cell is read or written 9 times in one test, and the test cycle time is 2.
20 ns, the number of Schmoe plots is 15 points on the vertical axis x 51 points on the horizontal axis = 765 points, and the number of points judged to be good (the number of asterisk marks "*") is 50.
It is assumed that the semiconductor memory device 1 is a dynamic random access memory (DRAM).

[0013]

[Problems to be Solved by the Invention] Since the conventional semiconductor integrated circuit test equipment is configured as described above, measurements must be repeated when performing characteristic tests, especially when collecting Schmoe plots. The time required for sampling increases dramatically as the capacity of semiconductor memory devices increases, such as 4.6 hours in the case of semiconductor memory devices, and as a result, it is virtually impossible to evaluate the characteristics of large-capacity semiconductor memory devices. The problem was that it was not possible.

The present invention was made to solve the above-mentioned problems, and the output data output from a semiconductor integrated circuit device is digitized at high speed and temporarily stored, and then the data is It is an object of the present invention to provide a semiconductor integrated circuit testing device that can reduce the time required to take a characteristic test, especially a Schmum plot, by digitally processing the data and determining the quality of the semiconductor integrated circuit device.

[0015]

[Means for Solving the Problems] A semiconductor integrated circuit testing apparatus according to the present invention includes a signal converting means (1) that samples a signal output from a semiconductor integrated circuit device (semiconductor memory device 1) at high speed and converts it into a digital signal. A high-speed A/D converter 15), a comparison means (digital comparator 17) for comparing the digital signal from this signal conversion means with an expected value, and a first comparator for temporarily storing the comparison result of this comparison means. storage means (high-speed buffer memory 19), and this first storage means (high-speed buffer memory 19).
an arithmetic means (
an arithmetic unit 20) and a second storage means (large capacity memory 24) for storing the arithmetic results of this arithmetic means;
The quality of the semiconductor integrated circuit device is determined by checking the data in the storage means.

[0016]

[Operation] The signal conversion means (high-speed A/D converter 15) samples the signal output from the semiconductor integrated circuit device (semiconductor memory device 1) at high speed and converts it into a digital signal. The comparison means (digital comparator 17) compares the digital signal from the signal conversion means with the expected value. 1st
The storage means (high-speed buffer memory 19) temporarily stores the comparison results of the comparison means. The arithmetic means (arithmetic device 20) performs a logical product with the data in the first storage means. Second
The storage means (large capacity memory 24) stores the calculation results of the calculation means. The quality of the semiconductor integrated circuit device is determined by checking the data in the second storage means.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the main structure of a semiconductor integrated circuit testing apparatus according to an embodiment of the present invention. Figure 2
is a block diagram for explaining the operation of this embodiment, FIG. 3 is a diagram for explaining the operation of the digital comparator in this embodiment, and FIG. The model diagram, FIG. 5, is a Schmoe plot diagram for explaining the effects of this embodiment. In FIGS. 1 to 5, 15 is a high-speed A/D converter as a signal conversion means for converting analog signals into digital signals at high speed, and 16 is a high-speed A/D converter.
17 is a digital signal outputted from the high-speed A/D converter 15, and 17 is a digital signal as a comparing means for comparing and determining the digital signal 16 with the expected value 13 and converting it into binary values of "0" and "1". a comparator; 18, a bit string output from the digital comparator 17; 19, a high-speed buffer memory as a first storage means for rapidly capturing and temporarily storing the bit string 18; 20, the high-speed buffer memory 19; 21 and 22 are registers in the arithmetic device 20 that store data to be operated on; 23 is a line of Schmu plot; 24 is a low-speed large-capacity memory device serving as a second storage means for storing the final results computed by the arithmetic unit 20.

Next, the operation will be explained. First, when data from memory cells (not shown) in the semiconductor memory device 1 is sequentially read out, data 3 is output from the data output pin 2 as in the conventional case. This output data 3 is sent to a high-speed A/D converter of a semiconductor integrated circuit testing device 5 via a signal propagation line 4.
For example, 6 bits are sent to the data storage device 15 at 1G sampling/s.
is converted into a digital signal 16 at a sampling rate of . The converted digital signal 16 is sent to the digital comparator 1
Sent to 7. The digital comparator 17 converts the digital signal 16 into two values of "0" and "1" using preset threshold levels Voh8, Vol9 and an expected value 13, thereby forming a bit string 18.

At this time, if the expected value 13 is the logical value "H", the portion where the digital signal 16 shows a voltage higher than the threshold level Voh8 is set to "1", and the other portion is set to "0". Make it. Further, when the expected value 13 is a logical value "L", the portion of the digital signal 16 showing a voltage lower than the threshold level Vol9 is set to "1", and the other portion is set to "0".

In other words, in either case, the portion that satisfies the expected value is converted to "1", and the portion that does not satisfy the expected value is converted to "0". In this sense, the bit string 18 that is created at this time, "1" means good and "0" means bad, corresponds to the results of repeated tests by changing the conventional strobe point 7 in fixed increments. are doing. For example, if this bit string 18 is a 36-bit string, it is equivalent to changing the strobe point 7 by 36 steps and repeating the test.

[0021] Next, the bit string 18 is once converted to the number 10.
It is temporarily stored in a high-speed buffer memory 19 having a capacity of about 0 Kbit. Then, the output data of all the memory cells of the semiconductor memory device 1 are processed according to the above operation.
This process of storing data in the high-speed buffer memory 19 is repeated. When this operation is completed, the high-speed buffer memory 19 will have stored the results of expected value determination of the output data of all memory cells of the semiconductor memory device 1.

Next, the data in the high-speed buffer memory 19 is sequentially transferred to the register 21 in the arithmetic unit 20,
Similarly, the logical product operation with the data (bit string) of the register 22 in the arithmetic unit 20 is repeated until the data in the high-speed buffer memory 19 runs out. The initial value of the data (bit string) in the register 22 is all bits "1". As a result, the data (
bit string), only those bit strings that are “1” in all the data in the high-speed buffer memory 19 are “1”.
In other words, it shows only the part where the output data of all the memory cells of the tested semiconductor memory device 1 were good.Then, strobe point 7 in the Schmumm plot This corresponds to the result of repeated tests by changing the value in fixed increments, and if the bit string "1" is replaced with an asterisk "*", it will be displayed in column 23 of Figure 4 (column parallel to the horizontal axis). This is the plot result.

Next, the data (bit string) finally remaining in the register 22 is sent to a large capacity memory 24 and stored therein. Then, the above operation is repeated while changing the parameters of the test conditions set on the vertical axis of the Schum plot, and the results are sequentially stored in the large-capacity memory 24.

Finally, if the data in the large capacity memory 24 are enumerated in order and the "1" bits are replaced with "*" and the "0" bits are replaced with blanks, a Schmoe plot similar to the conventional one is obtained. The Shumu plot is displayed on a CRT or output to a printer.

In the above embodiment, the parameter on the vertical axis of the Schmumm plot is the power supply voltage, but other parameters such as
For example, it may be an operation timing. In addition, although the above embodiments have explained the characteristic tests, especially the Schmumm plot, it is also possible to perform a high-speed EWS (engineering work station) function that graphically displays output data of a semiconductor integrated circuit device on a display device. It is also possible to use an apparatus capable of processing the above-mentioned conditions, and the same effects as those of the above-mentioned embodiments can be obtained.

[0026]

As described above, according to the present invention, there is provided a signal conversion means for sampling a signal output from a semiconductor integrated circuit device at high speed and converting it into a digital signal, and a digital signal output from the signal conversion means. a comparison means for comparing the values, a first storage means for temporarily storing the comparison result of the comparison means, and an arithmetic means for performing a logical product between the data in the first storage means; Since the second storage means stores the calculation results of the calculation means, it is possible to evaluate the output data of the semiconductor integrated circuit device without changing the strobe point. There is no need to perform device characteristic tests, especially repeated tests by changing the parameters of the test conditions on one axis of the Schmumm plot, but only by changing the parameters of the other test conditions. Therefore, an effect can be obtained in that the time required to collect a Schmoe plot can be shortened from several tenths to several hundredths of the conventional time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram including the main part configuration of a semiconductor integrated circuit testing apparatus according to an embodiment of the present invention.

FIG. 2 is a configuration diagram for explaining the operation of this embodiment.

FIG. 3 is a diagram for explaining the operation of the digital comparator in this embodiment.

FIG. 4 is a model diagram of a Schmoe plot for explaining the effects of this embodiment.

FIG. 5 is a Schmoe plot diagram for explaining the effects of this embodiment.

FIG. 6 is a block diagram including the main part configuration of a conventional semiconductor integrated circuit testing device.

FIG. 7 is a diagram for explaining the operation of the comparator in FIG. 6;

FIG. 8 is a configuration diagram of the digital comparator in FIG. 6;

FIG. 9 is a diagram illustrating the results of a characteristic test of a semiconductor memory device.

FIG. 10 is a diagram for explaining the time required for the above characteristic test.

FIG. 11 is a diagram for explaining the time required for the above characteristic test.

[Explanation of symbols]

1 Semiconductor memory device (semiconductor integrated circuit device) 5
Semiconductor integrated circuit testing equipment 15 High-speed A/D converter (signal conversion means) 17
Digital comparator (comparison means) 19 High-speed buffer memory (first storage means) 20 Arithmetic unit

Claims (1)

[Claims] 1. A semiconductor integrated circuit testing device that determines the quality of a semiconductor integrated circuit device by comparing a signal output from the semiconductor integrated circuit device with an expected value, comprising:
Comparison of a signal conversion means for sampling the signal output from the semiconductor integrated circuit device at high speed and converting it into a digital signal, a comparison means for comparing the digital signal from the signal conversion means with an expected value, and this comparison means. A first storage means for temporarily storing results, and data in this first storage means.
The semiconductor integrated circuit device is provided with an arithmetic means for performing a logical product with the data, and a second memory means for storing the arithmetic result of the arithmetic means, and by checking the data in the second memory means. A semiconductor integrated circuit testing device characterized by determining the quality of a semiconductor integrated circuit.