JPH04204066A - Ic tester and command data storing method in pin command register of ic tester - Google Patents

Abstract

PURPOSE:To efficiently store command data in a pin command register by simultaneously storing the same command data in the same pins of respective ICs. CONSTITUTION:The (N) taking mode signal inputted through a test address bus TAD is stored in an (N) taking mode register 1. Next, the pin address signal PAD indicating the pin command register corresponding to the specific pin among a plurality of the pins provided to a plurality of ICs to be measured is inputted to an address coder 2 through the bits b1-bm of the tester address bus TAD. The address coder 2 indicates the pin command register storing command data as follows: That is, output O11 enables the first pin command register of the first IC to be measured and, in the same way, the output O11 enables the pin command register.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an IC testing device, and more specifically, when testing a plurality of ICs, a pin command register provided for each bin of each IC is used. The present invention relates to an IC testing device suitable for efficiently storing instruction data.

[Conventional technology]

In recent years, IC test equipment has increased the amount of time required for each test as ICs have become more highly integrated, and as a result, the number of ICs that can be measured simultaneously has been increased to perform IC tests more efficiently. There is.

Here, in order for the IC testing apparatus to test the IC, it is necessary to store command data in a pin command register provided corresponding to each pin of each IC.

Storing instruction data in this pin instruction register has conventionally been performed as follows. In other words, Figure 4 is 4
In order to store instruction data in the four pin instruction registers corresponding to the four pins, the input pin address signal b
1 shows an example of an address decoder that forms address signals for each instruction register based on l, b l+1. Although not shown in FIG. 4, the data stored in the bin instruction registers is output to each bin instruction register via the tester data bus.

As is clear from FIG. 4, the conventional address decoder is configured to form an enable signal for each pin command register using the bin address signals bl and bl+1.

[Problem to be solved by the invention]

In the above-mentioned conventional technology, the instruction data is stored individually in the pin instruction register provided for each bin, so as the number of simultaneous measurement ICs increases, it becomes difficult to store the instruction data. There is a problem that requires a lot of time. That is, if it takes a long time to store instruction data in the pin instruction register, it will take a long time to execute a device test program, making it impossible to perform an IC test efficiently.

The present invention has been made in view of the problems of the prior art described above, and provides an IC testing device suitable for efficiently storing instruction data in a bin instruction register provided corresponding to each bin of each IC. The purpose is to

[Means to solve the problem]

The IC testing device and the method of storing instruction data in the bin instruction register of the IC testing device of the present invention simultaneously enable the pin instruction registers corresponding to the same pin among the pin instruction registers provided for each bin of each IC. This is to efficiently store instruction data in each bin instruction register.

[Effect]

In the present invention, the instruction register corresponding to the same pin of each IC has
This was done in consideration of the fact that normally the same instruction data is stored, and by storing the same instruction data to the bin instruction register of the same pin of each IC by one instruction data storage operation, it is possible to improve efficiency. The instruction data is stored in the .

〔Example〕

Hereinafter, the present invention will be explained in more detail with reference to embodiments shown in the accompanying drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, 1 is an N-capture mode register 1, 2 is an address decoder, TDB is a tester data bus, and TAB is a tester address bus.

Further, FIG. 2 is an explanatory diagram showing an example of a tester address signal transmitted via the tester address bus TAB, and the pitch hb+t-b of the tester address bus TDA constitutes the bin address signal PAD. .

First, N input via the tester address bus TDA.
The individual picking mode signal is stored in the N piece picking mode register 1. Next, bit b of the tester address bus TDA, ~
A pin address signal PAD that instructs a bit instruction register corresponding to a specific pin among a plurality of pins included in a plurality of ICs under test is sent to the address decoder 2 via the address decoder 2.
is input. The address decoder 2 receives the N-piece mode signals 00 to 00 stored in the N-piece mode register 1.
Upon receiving CJ and the pin address signal PAD, a pin instruction register for storing instruction data is specified as follows.

That is, the output ○□1 of the address decoder 2 enables the pin instruction register provided corresponding to the first bin of the first IC under test, and the output 012 enables the pin command register provided for the first bin of the first IC under test.
This is to enable the pin command register provided corresponding to the first pin of the 1st IC under test. The output OLM enables the pin command register provided corresponding to the M-th bin of the first IC under test.

Here, the address decoder 2 selects the first IC to be measured from the first IC to be measured according to the N-bit mode signals C0 to CJ stored in the N-bit mode register 1.
Regarding C, in order to store the same instruction data in each pin instruction register corresponding to the same pin of each IC, the output 011
．． ...OIK+ ...Controls OLM.

Next, the function of the address decoder 2 will be specifically explained using FIG. FIG. 3 is a circuit diagram showing a specific example of the address decoder 2 shown in FIG. 2, which corresponds to four pins (the same pin in different ICs, for example, the first bin of the first to fourth ICs). In order to store instruction data in the four pin instruction registers, input pin address signals P A D (b +, b 1 + x) are input.
An address signal for each instruction register is formed based on the 2-bit 4-bit mode signal Cs and Cs.

Here, the data stored in the pin instruction register is
It is assumed that the command is input to each pin command register via the tester data bus TDB shown in the figure.

In FIG. 3, when both C3 and C2 are O, one piece is taken. That is, in this case, outputs 011. 02++ 0311 04. One of them becomes "1" and the corresponding one pin instruction register is enabled.

In FIG. 3, C1 is 1. If C2 is 0, only two pieces are taken. That is, in this case, two of the outputs Olit 0211031+Oa become "1" according to the input pin address signal PAD (b,,b,ya,), and the two corresponding pin instruction registers are enabled. and the same instruction data is stored.

In FIG. 3, when C1 is O and C2 is 1, four pieces are taken. That is, in this case, according to the input pin address signal PAD (b, , b, +1), the outputs 0 + 1 + O, , , O, , 04, all become "1", and the corresponding Four pin instruction registers are enabled and store the same instruction data.

As is clear from the above description, according to this embodiment, the same instruction data can be stored in the pin instruction registers corresponding to the same pins in each IC under test.

(Effects of the Invention) According to the present invention, it is possible to efficiently store instruction data in the pin instruction register provided corresponding to each bin of each IC. Device test programs can be executed in a short time without requiring a large amount of time.
This makes it possible to conduct tests efficiently.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram showing an example of a tester address signal transmitted via the tester address bus shown in FIG. 1, and FIG. FIG. 4 is a circuit diagram showing a specific example of an address decoder shown in FIG. 4, and FIG. 4 is a circuit diagram showing an example of a conventional address decoder. 1...N mode register, 2...Address recorder, TDB...Tester data bus, TAB...
Tester address bus.

Claims (1)

[Claims] 1. A plurality of pin instruction registers are provided corresponding to respective pins of a plurality of ICs, and instruction data is stored in each pin instruction register, and based on the stored instruction data, In IC testing equipment that tests ICs, when storing instruction data in each of the above instruction registers, each I
1. A method for storing instruction data in a pin instruction register of an IC testing device, characterized in that the same instruction data is simultaneously stored for the same pin of an IC tester. 2. An IC that includes a plurality of pin instruction registers provided corresponding to each pin of a plurality of ICs, stores instruction data in each pin instruction register, and tests the IC based on the stored instruction data. In the test equipment, when storing instruction data in each of the instruction registers, the same instruction data is simultaneously stored to the same pins of a group of ICs selected from the plurality of ICs. A method 3 for storing instruction data in a pin instruction register of an IC testing device, characterized by comprising a plurality of pin instruction registers corresponding to each pin of a plurality of ICs, storing instruction data in each pin instruction register, and storing the instruction data in the pin instruction register. An IC testing device for testing an IC based on instruction data, characterized by comprising means for simultaneously enabling a plurality of instruction registers storing the same data. 4. The means receives a pin address signal for instructing a pin command register and a take-N mode signal for enabling a plurality of pin command registers, and is selected based on the pin address signal and the take-N mode signal. 4. The IC testing device according to claim 3, further comprising a logic circuit that simultaneously outputs an enable signal to each pin command register corresponding to the same pin of each IC.