JPH08110371A - Control method of test pattern memory of testing device of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To execute the flexible measurement when simultaneously measuring a plurality of products in parallel by constituting a test pattern memory from a plurality of memories. CONSTITUTION: A test pattern memory section 2 is constituted of a plurality of memories comprising at least a first memory and a second memory. When executing the testing, a test pattern stored in the first memory is copied to a memory region of the second memory by corresponding to the pin arrangement of a semiconductor integrated circuit (DUT) 3 to be measured so that the second memory is set to an execution memory. A pin number memory 23 that stores pin numbers of a copying target is provided. The test pattern is copied to the execution memory by referring the pin number data on the memory 23. Thereby, it is possible to execute the parallel measurement without providing an additional circuit on a hardware. When simultaneously testing the plurality of DUTs 3, arbitrary pin connection can be carried out without being limited by the physical arrangement of a pin electronics card 10 in a test head 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device (hereinafter referred to as "LSI"), and more particularly to an inspection device for testing electrical characteristics and functions of a logic LSI.
The present invention relates to a test pattern memory control system for an inspection apparatus having a parallel measurement function that enables simultaneous measurement of a plurality of LSIs.

[0002]

2. Description of the Related Art A conventional logic LSI tester will be described below with reference to the drawings.

FIG. 6 is a block diagram showing an example of the configuration of a conventional logic LSI tester. FIG. 7 is a diagram showing details of the circuit configuration of the pin electronics card 10 of FIG.

Referring to FIGS. 6 and 7, a conventional logic LSI tester includes a timing generator 1 for generating timings of signals for testing an LSI, and a test pattern memory unit (hereinafter referred to as a test pattern memory unit for storing an LSI inspection pattern). “Pattern memory” 2 and the LSI under test (Device Under
Test; hereinafter referred to as “DUT”) 3, and a test signal is converted into a predetermined voltage level according to the contents of the pattern memory 2, and the DU is generated at the timing generated by the timing generation unit 1.
The output signal from the driver circuit 4 applied to T3 and the DUT 3 is compared with a predetermined voltage level at the timing generated by the timing generation unit 1, a test signal is generated, and expected value data stored in the pattern memory 2 is compared. Power is supplied to the comparator circuit 5 (see FIG. 7) for comparison and determination, the fail memory unit 6 for storing the comparison and determination result according to the test pattern address, the data level control unit 7 for controlling the predetermined voltage level, and the DUT 3. A sample power supply unit 8 to
It is composed of a DC measuring unit 9.

Referring to FIG. 7, driver circuit 4 and comparator circuit 5 are formed on pin electronics card 10, and a plurality of pin electronics cards 10 are housed in test head 11. The load circuit (dynamic load) of the pin electronics card 10 applies a predetermined load to the output pin of the DUT 3 during a functional test or the like.

Incidentally, in the test head 11 shown in FIG. 6, G1 to G16 are generic names of pin electronics card groups arranged at the positions for the convenience of drawing, and G1 to G16 are respectively shown. For example, 16 pin electronics cards are accommodated, and the total pin count is 256 pins.

The pin electronics card 10 is connected to the pattern memory 2 via the parallel control circuit 12, and also has a timing generator 1, a data level controller 7,
And the fail memory unit 6.

The timing generator 1, the pattern memory 2,
The fail memory unit 6, the data level control unit 7, the sample power supply unit 8, the DC measurement unit 9, and the parallel control circuit 12 are controlled according to a test program running on a test processor unit (referred to as “processor”) 13. .

The control program and the test program executed by the processor 13 are stored in the program memory 14.
The external storage device 20 stores and stores a control program, a test program, a test pattern file, and the like.

FIG. 8 is a block diagram showing a detailed structure of the pattern memory 2. Referring to FIG. 8, the pattern memory 2 includes a low-speed large-capacity memory 15 and a high-speed execution memory 1.
6 and a memory control unit 17, and register 1
8 and 19 designate the pin numbers of the memories 16 and 17, respectively.

FIG. 9 is a block diagram showing a detailed configuration of the parallel control circuit 12. Referring to FIG. 9, the parallel control circuit 12 is formed of a matrix circuit, and the pattern memory 2 and the pin electronics card 10 are connected to each other. , And at the time of simultaneous measurement of four, it is connected to four pin electronics cards.
The parallel control signals 21 and 22 are active when two and four parallel control signals are measured, respectively.

Referring to FIG. 9, in the case of the two-piece parallel measurement, when the total number of pins is 256, the output of 1 from the pattern memory 2 is, for example, 1 and 129, and is output to two pin electronics cards every 128 pins. In the case of four parallel measurements, one output from the pattern memory 2 is distributed to four pin electronics cards every 64 pins, eg 1, 65, 129 and 193.

Further, referring to FIG. 9, when two or four parallel measurements are not performed, both parallel control signals 21 and 22 are made inactive, and NOR gates to which parallel control signals 21 and 22 are input. The output of the pattern memory 2 and the pin electronics card 10 correspond one-to-one via the.

The operation flow will be described below with reference to the flow chart shown in FIG.

First, the processor 13 reads a test program and a test pattern from the external storage device 20, and respectively reads the program memory 14 and the large capacity memory 1.
5 is written (S401).

Next, the processor 13 executes the test program according to an instruction from the outside (S402).

That is, the processor 13 first sets the timing generator 1 and the data level controller 7 in order to set the timing and voltage to predetermined values according to the contents of the test program.
The sample power supply unit 8 and the DC measurement unit 9 are controlled (S403), and the test pattern is executed (S404).

When the test pattern is executed, the test pattern on the large capacity memory 15 is copied to the execution memory 16 (S405).

In this copying operation, the processor 13
First, the pin number of the pattern data to be copied is written in the register 18 via the memory control unit 17, and the same pin number is written in the register 19 (S406).

Next, the test pattern data of the pin number indicated by the register 18 is read from the large capacity memory 15, and the execution memory 16 of the pin number indicated by the register 19 is read.
(S407).

Then, the test pattern data for the required number of pins is written while sequentially incrementing the pin number (S409 and the repeating processing of S406 to S407).

At the stage of executing the test pattern, the contents of this pattern are sent from the pattern memory 2 to the pin electronics card (PE) 10 via the parallel control circuit 12 (S410).

An electric signal is applied from the driver circuit 4 to the DUT 3 at the voltage and timing preset in the timing generator 1 and the data level controller 7 (S41).
1). The DUT 3 operates in response to the applied electric signal and responds with an output signal. The comparator circuit 5 compares this output signal with the voltage set by the data level control unit 7, and compares the result with the contents of the pattern memory 2 (S411).

Then, if the comparison determination contents do not match, it is determined to be defective, defect information is written to the fail memory 6 (S412), and a series of test operations is completed.

Then, in order to perform the test operation under the new test condition, the processor 13 reads the subsequent instruction of the test program, decodes it (S414), and sets a new timing and voltage to the timing generator 1 and data. Setting the level control unit 7, the sample power supply unit 8 and the DC measurement unit 9,
Execute the test pattern.

In this case, when the test pattern is already copied on the execution memory 16, the large capacity memory 15
The test pattern from is not copied, but only executed.

Only when the test pattern does not exist in the execution memory 16, the test pattern is copied from the large capacity memory 15.

As long as the program continues, the processor 13
Repeat a series of operations.

Next, the case of the two-piece parallel measurement operation will be described.

Here, the first LSI to be measured is set to DUT3.
The second LSI to be measured is DUT 3b.

In this case, referring to FIG. 9, the parallel control signal 21 becomes active at the time of parallel measurement of two pieces, and the pattern memory 2 has two pin electronics cards 1
Connected to 0, for example, in case of 256 pin system, connected to pin 129 together with pin 1 and pin 2 to 1 at the same time.
It is connected to the 20th pin, corresponds to the 3rd pin → the 121st pin, and is connected to the 128th pin → the 256th pin.

As a result, the DUT 3a is connected to pins 1-128 and the DUT 3b is connected to pins 129-256.

Then, as in the case of measuring one piece, signals are supplied to both DUT 3a and DUT 3b in accordance with the contents of the pattern memory 2, and the respective output results are also compared with the contents of the pattern memory 2 to make a judgment result. Is written in the fail memory 6.

Similarly, in the case of parallel measurement of four pieces, the parallel control signal 22 becomes active and is connected to the pins 65, 129 and 193 together with the pin 1, and is connected to the pattern memory 2 respectively. The same measurement as in the case of four measurements is possible.

[0035]

As described above, in the conventional tester, the pattern memory and the pin electronics card are connected to each other by hardware through the parallel control circuit 12 composed of a matrix circuit. Since parallel measurement is realized, pin number assignment during parallel measurement is fixed.

That is, in the above-mentioned 256-pin system, when two pieces are measured, the tester pins 1 and 129 form a pair, and 2 → 130, ..., 128 in sequence.
→ Corresponds to 256.

As a result, even if the wiring from the driver circuit 4 and the comparator circuit 5 to the socket in which the DUT 3 is mounted is optimum (for example, the minimum distance) at the time of measuring one piece, it is not always optimum at the time of measuring a plurality of pieces. In some cases, the wiring intersects, so it is necessary to increase the number of wiring layers of the test board, or it is necessary to perform wiring with a cable or the like.

Measurement in wafer state (wafer test)
Then, the restriction is further increased due to the restriction of the needle (probe needle) on the probe card.

In addition, since the conventional tester is realized by hardware, it is difficult to flexibly change the number of parallel measurements according to the number of pins to be mounted.

For example, in the 128-pin system, it is necessary to change the unit in 64-pin units in the case of two parallels and in the 32-pin unit in the case of four parallels. The hardware connection is changed from the 256-pin system described above. There is a constraint that you must do it.

Further, in the case of further increasing the number of parallel measurements as in the memory tester, there is a disadvantage that the number of connections in the parallel control circuit increases and the cost becomes high.

Therefore, the present invention has been made in view of such a problem, and an object of the present invention is to provide a flexible measurement when a plurality of products are simultaneously measured in parallel in a logic LSI inspection device. It is to provide a control method of a test pattern memory capable of performing the above.

[0043]

In order to achieve the above-mentioned object, the present invention has a test pattern memory for storing a test pattern for testing a semiconductor integrated circuit, and according to the contents of the test pattern memory. An inspection apparatus having a pin electronics card including a driver circuit for supplying an electric signal to a semiconductor integrated circuit under test and a comparator circuit for comparing and judging the output signal from the semiconductor integrated circuit under test and the contents of the test pattern memory. In the test pattern memory, the test pattern memory is composed of a plurality of memories including at least a first memory and a second memory, and when the test is executed, the test pattern stored in the first memory is used as a pin of the semiconductor integrated circuit to be measured. Copy to the memory area of the second memory according to the arrangement and execute the second memory Characterized by a memory, which provides a control method of the test pattern memory of the inspection apparatus for a semiconductor integrated circuit.

In the test pattern memory control method of the present invention, preferably, when simultaneously testing a plurality of semiconductor integrated circuits, the test pattern stored in the first memory is applied to the pins of the plurality of semiconductor integrated circuits. The second memory is copied into a plurality of memory areas of the second memory in correspondence with the above, and the second memory is used as an execution memory.

The present invention has a test pattern memory for storing a test pattern for testing a semiconductor integrated circuit, and a driver circuit for supplying an electric signal to the semiconductor integrated circuit under test according to the contents of the test pattern memory. ,
In a test apparatus including a pin electronics card configured by a comparator circuit for comparing and judging an output signal from the semiconductor integrated circuit under test and the contents of the test pattern memory, the test pattern memory includes at least a first memory and a second memory. And a pin information storage unit that stores information indicating the correspondence between the pins of the semiconductor integrated circuit under test and the memory area of the test pattern memory, and simultaneously tests a plurality of semiconductor integrated circuits. At this time, the test pattern stored in the first memory is copied to the plurality of memory areas of the second memory corresponding to the pins of the plurality of semiconductor integrated circuits based on the information of the pin information storage unit. A test of a semiconductor integrated circuit inspection device, characterized in that the second memory is an execution memory To provide a control method of turn memory.

Further, the test pattern memory control system of the present invention preferably comprises a register for designating a copy area (copy destination pin number) of the second memory,
Further, a third memory for storing the pin number and the copy destination pin number of the semiconductor integrated circuit under test is provided, and the third memory is stored when the contents of the first memory are copied to the second memory. The feature is that copying is performed with reference.

Further, in the test pattern memory control method of the present invention, preferably, when a plurality of semiconductor integrated circuits are tested at the same time, a plurality of copy destination pin numbers are stored in the third memory, and When the contents of the first memory are copied to the second memory, the third memory is referred to.

The test pattern memory control system of the present invention comprises a fourth memory which stores the pin numbers of the semiconductor integrated circuit to be measured and a plurality of pin numbers of the first memory. When a test pattern is read from an external storage device connected to the inspection device into the inspection device, the fourth memory is referred to, copied to a plurality of areas of the first memory, and a plurality of semiconductor integrated circuits are simultaneously tested. However, the above-mentioned object can be achieved.

[0049]

According to the present invention, when the test pattern is copied from the large capacity memory (first memory) to the execution memory (second memory), the test patterns corresponding to a plurality of LSIs to be measured are also copied. By doing so, it is not necessary to distribute the contents of the pattern memory to the plurality of pin electronics cards by the parallel control circuit during the parallel simultaneous measurement.

Further, a memory for storing the pin number of the copy destination execution memory is provided, and the test pattern is copied to the execution memory while referring to the pin number data on the memory.

Further, a new memory for storing the pin number of the LSI to be measured and a plurality of pin numbers of the large capacity memory is provided,
Depending on the contents of the memory, even if the test pattern stored in the external storage device is read into the tester and stored in the large-capacity memory, it is possible to perform parallel measurement by measuring multiple LSIs at the same time by copying to multiple areas. It will be realized.

As described above, the conventional tester is provided with the parallel control circuit composed of the matrix circuit and interconnects the pattern memory and the pin electronics card by hardware, and in the case of measuring two pieces, in two places and in the case of measuring four pieces, Parallel connection is realized by connecting 4 points.

On the other hand, according to the present invention, test pattern data corresponding to a plurality of LSIs to be tested are generated in advance on the execution memory by software without providing a matrix circuit. The above is different in operation.

Further, in the conventional tester, the pin number and the parallel measurement number corresponding to the parallel measurement are fixed, whereas in the present invention, the parallel measurement number can be increased and the corresponding pin number can be freely set. Therefore, they are also different in terms of their actions and effects.

[0055]

Embodiments of the present invention will be described below with reference to the drawings.

[0056]

[Embodiment 1] FIG. 1 is a block diagram showing an embodiment of the present invention.

The tester is similar to the conventional example shown in FIG.
A timing generation unit 1, a test pattern memory unit (referred to as “pattern memory”) 2, a DUT 3, a test head 11 containing a plurality of pin electronics cards 10 including a driver circuit 4 and a comparator circuit 5, and a fail memory unit 6. It is composed of a data level control unit 7, a sample power supply unit 8 and a CD measuring unit 9. FIG.
In the test head 11 shown in FIG. 1, G1 to G16 are generic names of the pin electronics card group arranged at the positions for the convenience of drawing.
Each of them accommodates, for example, 16 pin electronics cards, and has a total pin count of 256 pins.

The pin electronics card 10 is shown in FIG.
The configuration is the same as that of the above conventional example. Further, the pin electronics card 10 is directly connected to the pattern memory 2, and also connected to the timing generation unit 1, the data level control unit 7, and the fail memory unit 6.

The timing generator 1, the pattern memory 2,
The fail memory unit 6, the data level control unit 7, the sample power supply unit 8, and the DC measurement unit 9 are controlled by a test processor unit (referred to as “processor”) 13 according to a test program.

The program memory 14 has a processor 13
The external storage device 20 stores a test program and a test pattern.

Referring to FIG. 8, the pattern memory 2 is composed of a low-speed large-capacity memory 15, a high-speed execution memory 16 and a memory control unit 17, as in the conventional example, and registers 18 and 19 are memory respectively. Specify pin numbers 15 and 16.

Referring to FIG. 1, the pin number memory 23 is
A plurality of copy destination pin numbers in the execution memory 16 are stored.

As shown in FIG. 1, the tester according to this embodiment is not provided with the parallel control circuit 12 having the matrix configuration of the conventional example.

Next, FIG. 2 shows the flow of control in this embodiment.
This will be described with reference to the flowchart shown in FIG.

In the present embodiment, in the case of measuring one,
Since there is no difference with the conventional control flow, it is omitted, and in the following,
The case of parallel measurement will be described. Further, the description is omitted because it is the same as the conventional one except the test pattern control part.

In the present embodiment, it will be described below that, in the state where the pin number memory 23 is not used, the two-device parallel measurement operation can be performed as in the conventional example.

In this case, the same test fixture as that of the conventional example can be used as it is, and only a slight software change is required.

The first LSI to be measured is DUT 3a and the second LSI to be measured is DUT 3b.

Referring to FIG. 2, first, the processor 13
Reads the test program and the test pattern from the external storage device 20 and writes them into the program memory 13 and the large capacity memory 15 (S101).

At the time of executing the test pattern (S104), the test pattern is copied from the large capacity memory 15 to a plurality of areas of the execution memory 16 (S105).

In the copying process (S105), first, the processor 13 determines the DUT3 in the same manner as the one-piece measurement.
The test pattern data for a is read from the large capacity memory 15 and written in the execution memory 16.

That is, the pin number of the copy source is written in the register 18 (S106), the same pin number of the copy destination is written in the register 19, and the pin numbers are sequentially incremented (S110), and the required number of pins are tested. Write the pattern data.

Next, in copying the test pattern data for the DUT 3b, the most significant bit of the register 19 (here, the register 19 is composed of 7 bits 0 to 6) is set to "1", and the DUT 3a is set. Similarly, the test pattern data read from the large capacity memory 15 is written in the execution memory 16 (S108), and the test pattern data for the required number of pins is similarly written while incrementing the pin number sequentially (S110).

Most significant bit (b6) of this register 19
As a realization method for setting "1" to "1", in the case of software processing, it can be realized by writing the result added to the content of the register 18 to the register 19 as shown in the flowchart of FIG. 2 (see S107). .

That is, the contents of the register 18 and "10000
This can be realized by setting (writing) the sum of "00" in the register 19. Of course, a circuit can be added by hardware, but it will be described later when the pin number is arbitrarily set. It is not preferable because it becomes a limitation.

As a result, for example, the data of the first pin on the large capacity memory 15 is the most significant bit (b) of the register 19.
Since 6) is "1", 1 in the execution memory 16
It will be written to the 29th pin, and the execution memory 16
Data is written to the 129th pin as well as the above 1st.

Since the No. 129 pin is connected to the No. 1 pin of the DUT 3b, the signal is applied similarly to the DUT 3a, and the output signal of the DUT 3b is also compared and judged and written in the fail memory unit 6.
From the above, it is possible to simultaneously test each of the DUT 3a and DUT 3b.

Similarly, in the case of four parallel operation, the test pattern data of the 1st to 64th pins of the large capacity memory 15 are set by setting the b5 and b6 bits of the register 19 to "1". 1 to 64 of the execution memory 16
No. of pin area, (b5, b6) = (1,
0), pins 65 to 128, (b5, b6) = (0,
In 1), pins 129 to 192, (b5, b6) =
In (1, 1), it is also written in pins 193 to 256,
Each DUT is connected to each DUT, and measurement can be performed in the same manner as in the case of two parallel measurements.

Next, in the present embodiment, a case will be described in which the pin number memory 23 is used to arbitrarily set the pin number.

A flowchart of the operation in this case is shown in FIG. In the flowchart of FIG. 3, description of the same processing steps as in FIG. 1 will be omitted.

The pin number memory 23 has the following table 1 in advance.
As shown in, it is assumed that the copy source pin number and the copy destination pin number are written. Here, the copy source pin number is the pin number of the large capacity memory 15, and the copy destination pin number is
It is a pin number of the execution memory 16.

[0082]

[Table 1]

First, the test pattern execution stage (S20
In 4), the contents of the large capacity memory 15 are copied to the execution memory 16. In this case, the processor 13 first reads the copy source pin number from the pin number memory 23 (S20).
6) First, the copy source pin number is written in the register 18 (S207), the first copy destination pin number is read from the pin number memory 23 (S208), and the copy destination pin number is written in the register 19 (S209). That is, each pin 1 is written.

Then, the contents of the large capacity memory 15 designated by the register 18 are read and copied to the execution memory 16 designated by the register 19 (S210).

Next, with the contents of the register 18 storing the copy source pin number unchanged, the second copy destination pin number is read from the pin number memory 23 and the second copy destination pin number is written in the register 19 ( S212, S20
9).

Large-capacity memory 1 designated by register 18
The contents of 5 are read and copied to the execution memory 16 designated by the register 19 (S210).

As a result, the contents of the 1st pin of the large capacity memory 15 are written in the 16th pin of the execution memory 16.

Similarly, the test pattern is written in the execution memory 16 for all the copy destination pin numbers corresponding to one copy source pin number.

The contents of the 1st pin of the large capacity memory 15 are written to the 1st, 16th, 128th and 140th pins of the execution memory 16 (see the first row of Table 1).

Next, a new copy source pin number (second number in Table 1)
By writing the copy source pin number 2) of the line in the register 18 (S207) and the copy destination pin number in the register 19 (S209), the content of the pin 2 of the large-capacity memory 15 is the number 3 of the execution memory 16. Copied to a pin, 1
The pins 8, 130, and 152 are also sequentially copied (see the second row in Table 1).

In the same manner, the test patterns of all the copy source pin numbers are repeated until they are copied to the execution memory indicated by the copy destination pin number.

In this way, the test pattern data for the required number of pins is transferred from the large capacity memory 15 to the execution memory 16.
Copied to. This series of operations is controlled by software, and operations after the data is copied to the execution memory 16,
For example, the application of a signal from the driver circuit 4 to the DUT 3 and the comparison of the response output signal of the DUT 3 with the expected value pattern in the comparator circuit 5 and the fail processing are the same as those in the conventional example.

As described above, by referring to the pin number memory 23 and copying the test pattern from the large capacity memory 15 to the execution memory 16, the physical pin arrangement in the test head is not restricted. , It is possible to easily measure any pin number in parallel.

Note that the pin number memory 23 can be provided as an independent memory, but it is versatile to provide it in an area on the program memory 14 for storing the control program and the test program executed by the processor 13. It is preferable in terms.

In this case, the test program,
It is necessary to simultaneously read the data indicating the corresponding pin number together with the test pattern. For example, the data shown in Table 1 is previously created as a file and stored in the external storage device 20. It is read and generated as a pin number memory 23 on the program memory 14.

[0096]

Second Embodiment Next, a second embodiment of the present invention will be described. FIG. 4 is a block diagram showing the configuration of this embodiment. Further, FIG. 5 shows a flowchart of the operation of this embodiment.

Referring to FIG. 4, this embodiment is different from the structure of the first embodiment in that a pin corresponding memory 24 is provided instead of the pin number memory 23 of FIG. . Only the differences from the first embodiment will be described below.

In this embodiment, the pin number of the test pattern read from the external storage device 20 and the large capacity memory 1 are used.
A pin-corresponding memory 24 showing the correspondence with the pin number 5 (see FIG. 8) is provided, and when the test pattern is read from the external storage device 20, the pin-corresponding memory 24 is referred to and written in the large capacity memory 15.

Table 2 shows an example of the contents of the pin corresponding memory 24.

By writing in a plurality of areas of the large-capacity memory 15 at the pin number destination, it is copied to the execution memory 16 and executed at the time of execution.

That is, the copy destination pin number in Table 2 is set in the register 18 for designating the pin number of the large capacity memory 15 (see S307 in FIG. 5), and a test pattern read from the outside is written in the pin number. (See S308 of FIG. 5).

The operation after the test pattern is written in the execution memory 16 is not different from the operation of the conventional inspection apparatus, and in this embodiment as well, as in the first embodiment, the physical operation inside the test head is performed. It enables parallel measurement of arbitrary pin numbers without being restricted by various pin arrangements.

The pin-corresponding memory 24 can also be used as the pin number memory 23 described above. It can also be formed on the program memory 14 or can be generated in an independent memory area and used properly. Is also possible.

[0104]

[Table 2]

Although the present invention has been described with reference to each of the above embodiments, the present invention is not limited to the above embodiments, but includes various embodiments according to the principle of the present invention. For example, the present invention is not limited to logic LSI testers.

[0106]

As described above, according to the present invention (Claim 1), it is possible to perform parallel measurement without providing an additional circuit on the hardware, and to simultaneously test a plurality of DUTs. Any pin connection is possible without being limited to the physical arrangement of the pin electronics card in the test head, and the degree of freedom of pin connection during parallel measurement is increased.

Therefore, according to the present invention (Claims 1 and 2), there is an effect of facilitating the production of the test board and the probe card in the parallel measurement, and the test cost is reduced.

Further, according to the present invention, the degree of freedom of pin connection is remarkably increased, so that it is possible to realize the optimization of the test circuit such as connecting the LSI to be measured and the pin electronics card in the shortest distance. And enables measurements in the field of high speed testing.

Further, according to the present invention (claim 3), there is provided a pin information storage section for storing information indicating the correspondence between the pin of the semiconductor integrated circuit under test and the memory area of the test pattern memory, and the information storage section. With reference to, the test pattern stored in the first memory is copied to the plurality of memory areas of the second memory in association with the pins of the plurality of semiconductor integrated circuits to add to the hardware. Parallel measurement is possible without providing a circuit, and any pin connection is possible without being restricted by the physical arrangement of the pin electronics card in the test head. It is increasing.

According to the present invention, the fourth to sixth aspects are provided.
According to the preferred embodiment of the present invention as well, since special hardware for parallel measurement is not provided, parallel measurement can be performed with a pin number at an arbitrary position without being limited to a physical pin number in the test head. Therefore, the above effect can be achieved in the same manner.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a flowchart showing an operation of the first exemplary embodiment of the present invention.

FIG. 3 is a flowchart showing the operation of the first exemplary embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 5 is a flowchart showing the operation of the first exemplary embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a conventional LSI tester.

FIG. 7 is a block diagram showing a configuration of a pin electronics card of a conventional LSI tester.

FIG. 8 is a diagram showing details of the configuration of a pattern memory.

FIG. 9 is a diagram showing details of a parallel control circuit.

FIG. 10 is a flowchart showing an operation of a conventional example.

[Explanation of symbols]

1 Timing Generation Section 2 Test Pattern Memory Section 3 LSI Under Test 4 Driver Circuit 5 Comparator Circuit 6 Fail Memory Section 7 Data Level Control Section 8 Sample Power Supply Section 9 DC Measuring Section 10 Pin Electronics Card 11 Test Head 12 Parallel Control Circuit 13 Test Processor Section 14 program memory 15 large capacity memory 16 execution memory 17 memory control section 18 register 19 register 20 external storage device for storing test programs and test patterns 21 parallel control signal 22 parallel control signal 23 pin number memory 24 pin compatible memory

Claims (6)

[Claims] 1. A driver circuit having a test pattern memory for storing a test pattern for testing a semiconductor integrated circuit, the driver circuit supplying an electric signal to a semiconductor integrated circuit under test according to the contents of the test pattern memory, In a test apparatus including a pin electronics card configured by a comparator circuit for comparing and judging an output signal from a semiconductor integrated circuit under test and the contents of the test pattern memory, the test pattern memory includes at least a first memory and a second memory. And a plurality of memories including a memory, and when a test is executed, the test pattern stored in the first memory is copied to the memory area of the second memory in correspondence with the pin arrangement of the semiconductor integrated circuit under test. A semiconductor integrated circuit, wherein the second memory is an execution memory Control method of the test pattern memory of the location. 2. When simultaneously testing a plurality of semiconductor integrated circuits, the test pattern stored in the first memory is made to correspond to the pins of the plurality of semiconductor integrated circuits and the second pattern is stored.
2. The control system for a test pattern memory of a semiconductor integrated circuit inspection apparatus according to claim 1, wherein the second memory is copied into a plurality of memory areas of the memory of FIG. 3. A driver circuit having a test pattern memory for storing a test pattern for testing a semiconductor integrated circuit, the driver circuit supplying an electric signal to the semiconductor integrated circuit under test according to the content of the test pattern memory, In a test apparatus including a pin electronics card configured by a comparator circuit for comparing and judging an output signal from a semiconductor integrated circuit under test and the contents of the test pattern memory, the test pattern memory includes at least a first memory and a second memory. When a plurality of semiconductor integrated circuits are tested at the same time, including a plurality of memories including a memory, and having a pin information storage unit that stores information indicating the correspondence between the pins of the semiconductor integrated circuit under test and the memory area of the test pattern memory, And stores in the first memory based on the information in the pin information storage unit. The semiconductor integrated circuit is characterized in that the generated test pattern is copied to a plurality of memory areas of the second memory in association with pins of the plurality of semiconductor integrated circuits, and the second memory is used as an execution memory. Control method of test pattern memory of the inspection equipment of. 4. A register for designating a copy area (copy destination pin number) of the second memory, further comprising a third pin for storing a pin number and a copy destination pin number of the semiconductor integrated circuit under test.
2. The semiconductor integrated circuit according to claim 1, further comprising: a memory, wherein when copying the contents of the first memory to the second memory, the copying is performed with reference to the third memory. Control system for test pattern memory of inspection equipment. 5. When testing a plurality of semiconductor integrated circuits at the same time, a plurality of copy destination pin numbers are stored in the third memory, and the contents of the first memory are copied to the second memory. The control method of a test pattern memory of a semiconductor integrated circuit inspection apparatus according to claim 4, wherein the third memory is referred to at this time. 6. A test pattern is inspected from an external storage device connected to an inspection device, comprising a fourth memory storing and storing a pin number of the semiconductor integrated circuit to be measured and a plurality of pin numbers of the first memory. 2. The semiconductor integrated circuit according to claim 1, wherein when read into a device, the fourth memory is referred to, copied to a plurality of regions of the first memory, and a plurality of semiconductor integrated circuits are tested at the same time. Pattern memory control method for the inspection equipment of.