JPS63191080A - Electronic circuit measuring apparatus - Google Patents

Electronic circuit measuring apparatus

Info

Publication number
JPS63191080A
JPS63191080A JP62023172A JP2317287A JPS63191080A JP S63191080 A JPS63191080 A JP S63191080A JP 62023172 A JP62023172 A JP 62023172A JP 2317287 A JP2317287 A JP 2317287A JP S63191080 A JPS63191080 A JP S63191080A
Authority
JP
Japan
Prior art keywords
pattern
electronic circuit
circuits
measured
judge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62023172A
Other languages
Japanese (ja)
Inventor
Teruaki Ogata
尾方 照明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62023172A priority Critical patent/JPS63191080A/en
Publication of JPS63191080A publication Critical patent/JPS63191080A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To simultaneously measure a plurality of electronic circuits each having a small number of pins without adding hardware, by respectively providing a plurality of comparators and a plurality of memory parts and arbitrarily combining them by software. CONSTITUTION:The pattern from a pattern generating part 1 is supplied to an electronic circuit through a pattern driver 3 and inputted to a level comparator 7 through a buffer circuit 6. This output pattern is compared with the expectation value pattern from the pattern generating part 1 by a pattern comparator 8 and the result thereof is transmitted to a judge result recording part 9. At this time, when 10 judge circuits are used with respect to one electronic circuit to be measured, the remaining 38 judge circuits are allotted to the other electronic circuit to be measured. The result at every judge circuit is collected at every circuit to be measured to perform the judgement of quality in a controller 10A and a judge result is displayed on a display part 11A corresponding at each electronic circuit to be measured.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は例えば論理回路機能など入カッ(ターンに対
して、出力)くターンが一義的に規定できる電子回路の
測定装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a measuring device for electronic circuits, such as logic circuit functions, which can uniquely define input (output versus turn) turns.

〔従来の技術〕[Conventional technology]

第2図は従来のこの種の電子回路測定装置を示す全般的
構成図で、(1)は論理テストのための入カバターンを
発生するパターン発生部、(2]はその発生パター78
制御するパターン制御部、(3)はパターン発生部[1
1からの人カバターンをスイッチ(4a)を介して被測
定電子回路(図示せず)へ供給するパターンドライバ、
(5)はパターンドライバ(3)及び後述のレベルコン
パレータの7ベル設定に用いる基準電圧発生部、(6)
は被測定電子回路からスイッチ(4b)を経て得られる
出力を取り込むバッファ回路、(7)はバッファ回路(
6)の出カッベルを基準電圧発生部[5)からの基準ノ
ベルと比較するレベルコンパレータ、(8)は出力パタ
ーンを期待パターンと比較スルパターンコンパソータ、
(9)はそれら比較による判定結果を記憶する判定結果
記録部、αqは上記この装置全体をコントロールするコ
ントローラ。
FIG. 2 is a general configuration diagram showing a conventional electronic circuit measuring device of this type, in which (1) is a pattern generation section that generates an input pattern for logic testing, and (2) is the generated pattern 78.
The pattern control section (3) is the pattern generation section [1
a pattern driver that supplies the human cover turn from 1 to an electronic circuit under test (not shown) via a switch (4a);
(5) is a reference voltage generator used for setting 7 bells of the pattern driver (3) and the level comparator (described later); (6)
is a buffer circuit that takes in the output obtained from the electronic circuit under test via the switch (4b), and (7) is a buffer circuit (
(6) is a level comparator that compares the output pattern with the reference level from the reference voltage generator [5); (8) is a pattern comparator that compares the output pattern with the expected pattern;
(9) is a judgment result recording unit that stores the judgment results obtained by these comparisons, and αq is a controller that controls the entire device.

(ロ)は測定結果を表示する表示部である。(b) is a display section that displays measurement results.

次に動作について説明する。被測定回路の入力として必
要なパターン及び出力の期待値パターンはパターン発生
部(1)に記憶させておいて、ノ<ターン制@ m (
21によって、所定の連続パターンとして。
Next, the operation will be explained. The pattern required as the input of the circuit under test and the expected value pattern of the output are stored in the pattern generation unit (1), and then
21 as a predetermined continuous pattern.

パターン・ドライバ(3)に供給される。一方で基準電
圧発生部15)から人力レベルの設定に必要な基準レベ
ルがパターンドライバ(3)に供給され、パターンドラ
イバ(3)から被測定電子回路(こ必要なパターンとレ
ベルを満足する信号出力が、供給される。
Supplied to pattern driver (3). On the other hand, the reference voltage generation section 15) supplies the reference level necessary for setting the human power level to the pattern driver (3), and the pattern driver (3) outputs a signal that satisfies the required pattern and level of the electronic circuit under test. is supplied.

次に被測定電子回路からの出力はバッファ回路(6)箒
を経由した後に、ノベルコ/パV−タ(7)に接続サレ
る。レベルコンパレータ(1)は、規定の出力レベルで
ある力Sどう乃Sを基準電圧発生部(5)からの比較判
定レベルと比較し、出力パターンをノーマライズする。
Next, the output from the electronic circuit under test passes through a buffer circuit (6) and is then connected to a novel computer/computer (7). The level comparator (1) compares the force S which is a prescribed output level with the comparative determination level from the reference voltage generator (5), and normalizes the output pattern.

次(こ、このパターンをパターン発生部(11fこ記憶
させである期待値パターンと、バター7コンパレータ(
8)で比較し、その結果を判定結果記録部(9)1こ転
送し、被測定電子回路の良否判定を行ない1表示部0η
に表示する。
Next (this pattern is stored in the pattern generation section (11f) and the expected value pattern is stored in the butter 7 comparator (
8) and transfers the results to the judgment result recording section (9), which judges whether the electronic circuit under test is good or not.
to be displayed.

第3図は従来の測定装置を用いて複数個の被測定回路の
評価を行なう場合の判定結果の記録及び表示動作に必要
な構成を示すブロック図で、従来装置では1例えば48
個の同種の被測定回路の評価を行なうには48個の判定
回路を必要とし、これに伴なって48個の判定結果記録
部(9a)〜(9n)が設けられ、これらの出力結果を
ハードウェア的に合成して、コントローラαQ1こ伝達
し1表示部qので測定結果として表示していた。
FIG. 3 is a block diagram showing the configuration necessary for recording and displaying judgment results when evaluating multiple circuits under test using a conventional measuring device.
In order to evaluate the same type of circuit under test, 48 judgment circuits are required, and accordingly, 48 judgment result recording sections (9a) to (9n) are provided to record these output results. The results were synthesized by hardware, transmitted to the controller αQ1, and displayed as measurement results on the display unit q.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来のこの種の電子回路測定装置は以上のように構成さ
れているので1例んば、複数個の同種の被測定電子回路
を同時に並列Eこ測定する場合ζこは。
Since this type of conventional electronic circuit measuring device is constructed as described above, for example, when a plurality of electronic circuits of the same type are to be simultaneously measured in parallel.

個々の被測定回路に対応した。出力判定部すなわち、コ
ンパレータ部と記録部とをハード的に準備する必要があ
り、測定装置の−・−ドウエアの制作時に並列測定の個
数を決定すべきであり、冗長性に欠ける。ハードウェア
が複雑となるなどの問題点があった。
Compatible with individual circuits under test. It is necessary to prepare an output determination section, that is, a comparator section and a recording section as hardware, and the number of parallel measurements must be determined at the time of manufacturing the measuring device, resulting in a lack of redundancy. There were problems such as complicated hardware.

この発明は、上記のような問題点を解消するためになさ
れたもので、ソフト・ウェア的に複数個同時測定できる
と共に多数の入出力ビンを有する電子回路測定装置を、
ハード・ウェアを付加せrに、ソフト・ウェアで制御す
ることによって少数ビンの電子回路の複数個同時測定を
容易に実現しハード・ウェアの有効利用、即チコスト・
パフォーマンスの改善可能な装置を得ることを目的とす
る。
This invention was made to solve the above-mentioned problems, and it is an electronic circuit measuring device that can simultaneously measure multiple items using software and has a large number of input/output bins.
By adding hardware and controlling with software, simultaneous measurement of multiple electronic circuits with a small number of bins can be easily realized, making effective use of hardware and reducing costs.
The purpose is to obtain a device whose performance can be improved.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る電子回路測定装置は、複数個同時測定の
場合lこは、出力判定部をソフト・ウェア的に分割し、
各被測定回路に割り付け、その結果を各被測定回路ごと
にまとめて記録し、最終結果を記録部力)ら各被測定回
路ごとに、識別表示することを可能としたものである。
In the case of simultaneous measurement of a plurality of electronic circuits, the electronic circuit measuring device according to the present invention divides the output determination section using software,
It is possible to allocate it to each circuit under test, record the results for each circuit under test, and display the final result for each circuit under test from the recording section.

〔作用〕[Effect]

予 この発明に3ける電子回路測定装置は、〉ストプログラ
ムの記述により、出力a足回路が6被測定電子回路に割
り付けられ、その割り付けられた出力判定部ごとに良否
判定を実施し、測定結果としての良否判定を各被測定電
子回路毎に識別表示する。
In the electronic circuit measuring device according to the third aspect of the present invention, the output a-leg circuit is assigned to six electronic circuits to be measured according to the description of the strike program, the pass/fail determination is performed for each of the assigned output determination sections, and the measurement result is determined. The pass/fail judgment is identified and displayed for each electronic circuit under test.

〔実施例〕〔Example〕

以下この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.

まずこの発明を適用する電子回路測定装置の基本形は第
2図に示した従来装置と全く同一であるので1重複説明
は省略する。
First, since the basic form of the electronic circuit measuring device to which the present invention is applied is exactly the same as the conventional device shown in FIG. 2, repeated explanation will be omitted.

第1図はこの発明の一実施例の要部のみの構成を概念的
に示すブロック図で、従来装置の@3図に対応して示し
たものである。この実施例では。
FIG. 1 is a block diagram conceptually showing the configuration of only the main parts of an embodiment of the present invention, and is shown corresponding to FIG. 3 of the conventional device. In this example.

判定結果記録部(気)〜(9n)の出方は48個独立し
てコントローラ(IOA)に伝達される。コントローラ
(IOA)では測定プログラムの記述に従って測定結果
を合成する。すなわち、48個の出方判定回路がすべて
1個の被測定電子回路の判定に使用される場合には判定
結果を1個分にまとめる。
The results of 48 determination result recording sections (Ki) to (9n) are independently transmitted to the controller (IOA). The controller (IOA) synthesizes the measurement results according to the description of the measurement program. That is, when all 48 output determination circuits are used to determine one electronic circuit under test, the determination results are combined into one circuit.

ところが、1個の被測定電子回路に対して、10個の判
定回路を使用する場合は残りは38個を、他の被測定電
子回路用に割り当てる。そしてこの割り当てた判定回路
ごとの結果を各被測定電子回路ごと昏こまとめて、良否
判定の判断をコントローラ’ (IOA)で行ない、各
被測定電子回路ごとGζ対応して、良否判定の表示を!
表示部(ILA)で実施する。勿論1表示部(IIA)
はテストプログラムによって記述された被測定電子回路
数に対応した表示機能を有している。
However, when 10 judgment circuits are used for one electronic circuit under test, the remaining 38 judgment circuits are allocated to other electronic circuits under test. Then, the results for each assigned judgment circuit are summarized for each electronic circuit under test, and a pass/fail judgment is made by the controller' (IOA), and the pass/fail judgment is displayed for each electronic circuit under test. !
This is carried out on the display unit (ILA). Of course 1 display section (IIA)
has a display function corresponding to the number of electronic circuits to be measured written by the test program.

前記の実施例では、ハード・フェア上で決定される判定
回路の数を分割して、複数の被測定成子回路に使用する
場合について述べたが、逆に、このような機能を有する
測定装置を1例えば48個出力判定回路を有する装置を
、被数台並列に用いて48X2.48X3.48X4な
ど多数個の出力判定回路を有する装置としても使用でき
る。
In the above embodiment, a case was described in which the number of judgment circuits determined on the hardware fair is divided and used for multiple child circuits to be measured. 1. For example, a device having 48 output determination circuits can be used as a device having a large number of output determination circuits such as 48×2.48×3.48×4 by using several devices in parallel.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば1判定回路をノット・
ウェアで組み合わせる事を可能としたので、多数の入出
力端子を有する被測定電子回路用の測定装置を少数の入
出力端子を有する被測定電子回路用として用いる際に容
易に並列測定の実現を可能とし、コスト・パフォーマン
スの高い電子回路測定装置を得られる効果がある。
As described above, according to the present invention, the 1 determination circuit can be knotted.
Since it is possible to combine them using hardware, it is possible to easily realize parallel measurements when using a measurement device for an electronic circuit under test that has a large number of input/output terminals as an electronic circuit under test that has a small number of input/output terminals. This has the effect of providing an electronic circuit measuring device with high cost performance.

【図面の簡単な説明】[Brief explanation of the drawing]

@1図はこの発明の一実施例の要部のみの構成を概念的
に示すブaノ゛り図、第2図は従来の電子回路測定装置
を示す全般的構成図、第3図は従来の測定装置を用いて
複数個の被測定成子回路の評価を行なう場合の要部のみ
の構成を示すブロック図である。 図(こ3いて、C1)はパターン発生部、(7)はノベ
ルコンパレータ、 (8)はパターンコンパレータ、(
9)。 (9a) 〜(9n)は判定結果記録部、M 、 Cl
0A)はコントローラ、 01)、  (IIA)は表
示部である。 な21図中同一符号は同一、または相当部分を示す。
@ Figure 1 is a box diagram conceptually showing the configuration of only the main parts of an embodiment of the present invention, Figure 2 is a general configuration diagram showing a conventional electronic circuit measuring device, and Figure 3 is a diagram of a conventional electronic circuit measuring device. FIG. 2 is a block diagram showing the configuration of only the main parts when evaluating a plurality of component circuits to be measured using the measuring device of FIG. Figure (C1) shows the pattern generation section, (7) shows the novel comparator, (8) shows the pattern comparator, (
9). (9a) to (9n) are determination result recording units, M, Cl
0A) is a controller, 01) and (IIA) are display units. The same reference numerals in Figure 21 indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] (1)論理機能を有する被測定電子回路に所定の入力パ
ターンを入力したときの当該被測定電子回路の出力パタ
ーンを期待パターンと比較するコンパレータと、 その比較結果を記憶して良否判定を行なう記録部を有す
るものにおいて、 上記コンパレータ及び上記記録部をそれぞれ複数個設け
、ソフトウェアで任意に組み合わせて複数個の上記被測
定電子回路を同時並列に測定できるようにしたことを特
徴とする電子回路測定装置。
(1) A comparator that compares the output pattern of the electronic circuit under test with an expected pattern when a predetermined input pattern is input to the electronic circuit under test having a logic function, and a record that stores the comparison results and makes a pass/fail judgment. An electronic circuit measuring device having a plurality of comparators and a plurality of recording sections, each of which can be arbitrarily combined using software to simultaneously measure a plurality of the electronic circuits to be measured in parallel. .
JP62023172A 1987-02-03 1987-02-03 Electronic circuit measuring apparatus Pending JPS63191080A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62023172A JPS63191080A (en) 1987-02-03 1987-02-03 Electronic circuit measuring apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62023172A JPS63191080A (en) 1987-02-03 1987-02-03 Electronic circuit measuring apparatus

Publications (1)

Publication Number Publication Date
JPS63191080A true JPS63191080A (en) 1988-08-08

Family

ID=12103207

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62023172A Pending JPS63191080A (en) 1987-02-03 1987-02-03 Electronic circuit measuring apparatus

Country Status (1)

Country Link
JP (1) JPS63191080A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08110371A (en) * 1994-10-07 1996-04-30 Nec Corp Control method of test pattern memory of testing device of semiconductor integrated circuit
US6546511B1 (en) 1999-06-15 2003-04-08 Samsung Electronics Co., Ltd. Apparatus and method for parallel testing of multiple functional blocks of an integrated circuit
US7207738B2 (en) 2005-07-14 2007-04-24 Micro Co., Ltd. Writing instrument

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08110371A (en) * 1994-10-07 1996-04-30 Nec Corp Control method of test pattern memory of testing device of semiconductor integrated circuit
US6546511B1 (en) 1999-06-15 2003-04-08 Samsung Electronics Co., Ltd. Apparatus and method for parallel testing of multiple functional blocks of an integrated circuit
US7207738B2 (en) 2005-07-14 2007-04-24 Micro Co., Ltd. Writing instrument

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