JP2962552B2 - IC test equipment - Google Patents

Description

The present invention relates to an IC test apparatus for testing a large-scale integrated circuit device such as an LSI.

[Prior art] In an IC test apparatus, a predetermined pattern signal is given to each input terminal of an IC under test, and a response output corresponding to the pattern signal is compared with an expected value pattern signal. Is determined.

The rising and falling timing edges of the pattern signal given to each terminal of the IC under test and the timing edge for reading the response output of the IC under test must be set for each terminal.

Classification of how to handle timing edges in IC test equipment is broadly classified into resource distribution type (shared resource type) and per-pin type.

In the case of a resource distribution type IC test apparatus, a method is used in which a predetermined number of timing edges are prepared and each timing edge is assigned to each terminal of the IC under test.

If the total number of required timing edges exceeds the predetermined number, it is necessary to divide the test into several times or to round the test edges using relatively close timing edges. .

Combination of timing edges (timing set)
In order to realize the on-the-fly function of changing the real time during the test of a large-scale integrated circuit, a large number of additional circuits are required, which leads to an increase in mounting space and cost.

On the other hand, in the case of a per-pin type IC test apparatus, since a timing generation circuit is provided for each terminal of the IC under test, a timing edge given to each terminal can be freely selected.

Therefore, there is no need to round the timing edge or divide the test into several times.

However, since a timing generation circuit is provided for every pin, the scale of hardware is larger than that of a resource-distribution-type testing machine without considering the on-the-fly function. Therefore, on-the-
When the fly function is realized, the scale of the hardware is further increased, which leads to an increase in mounting space and cost.

[Problems to be solved by the invention] To realize the on-the-fly function in the conventional per-pin type IC test equipment, it is necessary to prepare multiple timing edges for each terminal that requires on-the-fly There is.

If a plurality of timing edges are prepared for each terminal by a conventional method, there is a disadvantage that the scale of hardware increases almost in proportion to the number of timing edges.

SUMMARY OF THE INVENTION An object of the present invention is to provide a per-pin type IC test apparatus in which the timing set per terminal can be made plural by adding a small amount of hardware, thereby providing an on-the-fly function. It is intended to provide a test device.

In the present invention, the pattern data memory and the timing generation circuit, and the pattern data read from the pattern data memory and the timing signal output from the timing generation circuit are supplied to the IC under test. Tested with a waveform generator that generates the actual waveform signal applied to the pins
In an IC test apparatus having a per-pin structure provided for each terminal of an IC, a signal switching circuit is provided between a timing generation circuit and a waveform generation circuit, and the signal switching circuit is provided for other terminals. And a timing signal output from its own timing generation circuit, and the timing signal output from its own timing generation circuit can be selected and taken into the waveform generation circuit. The switching data is stored in a pattern data memory, and the switching circuit is switched and controlled by the switching data as required.

According to the configuration of the present invention, a signal is switched between a waveform generating circuit that supplies a pattern signal to a terminal of an IC under test that requires an on-the-fly function and a timing generating circuit that supplies a timing signal to the waveform generating circuit. A signal switching circuit for selectively receiving a timing signal output from a timing generation circuit provided for another terminal and a timing signal output from its own timing signal generation circuit by the signal switching circuit. The timing can be switched on-the-fly by switching the signal switching circuit in real time during the test. Therefore, simply providing a signal switching circuit
The fly function can be added.

Needless to say, the switching data for switching the signal switching circuit is shared by using the pattern data memory paired with the timing generation circuit for the other terminals, so that an increase in hardware can be suppressed also in this respect.

Embodiment FIG. 1 shows an outline of an IC test apparatus according to the present invention. In the figure, 100 is a reference rate generator, 200 is a tester controller,
Reference numeral 300 denotes a group of waveform generators.

Each unit 300A, 300 constituting this waveform generator group 300
B, 300C,..., 300N show a case where a waveform generator for two terminals is configured to be combined as one unit in this example.

That is, the waveform generator for the odd-numbered terminal and the timing generator for the even-numbered terminal are incorporated in each of the units 300A to 300N.

The reference rate generator 100 outputs a reference rate signal 400 to each of the units 300A to 300N.

The tester controller 200 and each of the units 300A to 300N are connected by a data bus line 500 and a control bus line 600, and test pattern data and expected value pattern data, timing data for determining a timing edge, and control signals through these bus lines 500 and 600. Is distributed to each of the units 300A to 300N.

FIG. 2 shows the internal structure of each of the units 300A to 300N. Each unit 300A to 300N is a unit 30 for odd-numbered terminals of the IC under test.
1 and an even terminal unit 302. These units 301 and 302 are hereinafter referred to as single units.

The single units 301 and 302 are the pattern data memories 301A and 30
2A, timing generation circuits 301B and 302B, fail memories 301C and 302C, waveform generation circuits 301D and 302D, and a driving circuit 30
1E, 302E and logical comparison circuits 301F, 302F.

The feature of the present invention is that a signal switching circuit 301G is provided in one of the paired single units, 301 in this example. The signal switching circuit 301G is provided between the timing generation circuit 301B and the waveform generation circuit 301D of the single unit 301, and outputs a single timing signal to the waveform generation circuit 301D.
The configuration is such that the timing signal output by the timing generation circuit 301B of the unit 301 and the timing signal output by the timing generation circuit 302B of the other single unit 302 forming the pair can be selectively captured.

Note that a case is shown in which a strobe switching circuit 301H is provided on a supply path of a strobe pulse supplied to the logical comparator 301F, and the strobe pulse is also switched by the strobe switching circuit 301H.

The figure shows a case where the switching circuits 301G and 301H are configured by contact switches, but since the switching circuits 301G and 301H operate at high speed, semiconductor switches are actually used. The switching signal is a parallel signal composed of a plurality of bits.

These signal switching circuit 301G and strobe switching circuit 30
Switching of 1H is controlled by switching data stored in a pattern memory provided in the other single unit 302.

The normal operation will be described. Terminals P ₁ and P _{2 of the} IC under test
Is a single unit 301, 302
, The switches S ₁ and S ₂ are controlled to be turned on, and the drive circuits 301E and 302E and the logic comparison circuits 301F and 302F are connected to the terminals P ₁ and P ₂ of the IC under test. When the terminals P ₁ and P ₂ are input-only terminals, the switch S ₂ is turned off, and only the drive circuits 301 E and 302 E are connected to the terminals P ₁ and P ₂ . When the terminals P ₁ and P ₂ are output-only terminals, only the switch S ₂ is turned on and the logic comparison circuit
301F and 302F are connected to terminals P ₁ and P ₂ .

The following description is based on the assumption that the terminals P ₁ and P ₂ are input / output terminals. In the normal test state, the signal switching circuit 301G and the strobe switching circuit 301H select the contact A side, and the single unit
Waveform generating circuit 301 301D generates a pattern signal with the pattern data and the timing signal output from the pattern data memory 301A and the timing generator circuit 301B, and inputs the pattern signal to the terminal P _1.

Logical comparison circuits at a timing which the terminal P ₁ is the output terminal 30
Give strobe pulse from the timing generator circuit 301B to 1F, read the logic state of the pin P _1. This logic state is compared with the logic of the corresponding bit in the expected value pattern,
A mismatch is determined. When a mismatch is detected, data indicating a failure is written to the fail memory 301C at the address where the mismatch occurred. At this time also works like a single 1 unit 302 side to judge whether the logical correct output to the terminal P _2.

Next, the operation of the on-the-fly function will be described with reference to FIGS.

In the mode for operating the on-the-fly function, the switches S ₁ and S ₂ of the single unit 302 are turned off, and the single unit 30 is switched off.
2 is disconnected from the IC under test.

In the on-the-fly mode, the switching data is sent from the tester controller 200 to the pattern data memory 302A of the single unit 302 and stored. The switching data is sequentially read out, and the signal switching circuit 301G and the strobe switching circuit 301H
Are switched.

Different timing data is set in the timing generation circuits 301B and 302B, and timing signals having different timings are generated using the set timing data.

This timing signal is selected in accordance with the switching data stored in the pattern data memory 302A, and the waveform generation circuit 301D
To generate a pattern signal.

By controlling the switching of the signal switching circuit 301G as necessary in this manner, the timing of the pattern signal and the timing of the strobe pulse can be switched at any time during the test, and the operation in the on-the-fly mode is performed. Can be done.

[Effects of the Invention] As described above, according to the present invention, the signal switching circuit 301G and the strobe switching circuit are provided in one of the paired single units.
It can be operated in on-the-fly mode only by providing 301H.

Therefore, it is possible to operate in the on-the-fly mode by adding only a few components to the configuration of the single unit 301. Therefore, it can be turned on without significantly increasing costs.
The effect of being able to provide an IC test apparatus having the fly function is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram for explaining a main part of the present invention, and FIG. 3 is an embodiment of the present invention in an on-the-fly mode. FIG. 4 is a block diagram for explaining a main part in the on-the-fly mode of the present invention. 301A, 302A: pattern data memory, 301B, 302B: timing generation circuit, 301D, 302D: waveform generation circuit, 301G: signal switching circuit, 301H: strobe switching circuit.

Claims (1)

(57) [Claims] 1. A pattern data memory and a timing generation circuit, and a pattern signal read from the pattern data memory and a timing signal output from the timing generation circuit are applied to apply a pattern signal to be applied to a terminal of an IC under test. An IC test apparatus having a per-pin structure in which a waveform generating circuit to be generated is provided for each terminal of an IC under test, a signal switching circuit is provided between the timing generating circuit and the waveform generating circuit, The switching circuit is configured to be able to select a timing signal of a timing generation circuit provided for another terminal and a timing signal output from its own timing generation circuit to be taken into a waveform generation circuit. The switching data is stored in the pattern data memory paired with the IC test equipment comprising configured to switch controlling the switching circuit by the switching data according to.