JP2002189058A - Semiconductor device testing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device testing apparatus, capable of simultaneously testing a plurality of semiconductor devices, when the timing of a test pattern signal applied on a specied pin by each semiconductor device to be tested must be selected to timing which is suitable for each device. SOLUTION: A changeover means 16 is provided on the partial channel of the supply system path of the test pattern signal applied on each semiconductor device, and the test pattern signal of the other channel is selected by the changeover means to be applied on the specied pin of the semiconductor device to be tested.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device test apparatus for testing a semiconductor device constituted by a logic circuit such as an arithmetic processing unit (CPU), and more particularly to a test pattern having a different timing for each semiconductor device under test. It is an object of the present invention to provide a semiconductor device test apparatus having a configuration capable of simultaneously testing a plurality of semiconductor devices under test even when a signal must be applied.

[0002]

2. Description of the Related Art FIG. 3 shows an outline of a generally used semiconductor device test apparatus. Generally, a semiconductor device test apparatus includes a timing generator 11 and a pattern generator 12.
, A waveform shaper 13 and a logic comparator 14 for testing whether the semiconductor device under test DUT operates normally. That is, the pattern generator 12 generates a test pattern signal including an address signal, test pattern data, and a control signal for the semiconductor device under test DUT according to the reference clock generated by the timing generator 11. These test pattern signals are applied to the waveform shaper 13, shaped into a waveform required for the test, and applied to the semiconductor device under test DUT.

The semiconductor device under test DUT controls writing and reading of a test pattern signal by a control signal. The test pattern signal read from the device under test DUT is supplied to a logical comparator 14, where the expected value data output from the pattern generator 12 and the read data are compared with each other. As a result, the quality of the semiconductor device under test DUT is determined.
The waveform shaper 13 includes, for example, a 1024-channel test pattern signal supply path, sorts the 1024-channel test pattern signal supply path, for example, for every 32 channels, and has 32 memories to be tested having 32 pins (32 pins). 32
× 32 = 1024) at the same time, or in the case of a logic device, the number of pins is 200 to 50
Since there are as many as 0 pins, for example, in the case of a 512-pin semiconductor device, the number of semiconductor devices that can be tested at one time is two.

As described above, since the number of channels of a test pattern signal supply system provided in a semiconductor device test apparatus is limited, the number of semiconductor devices that can be tested simultaneously depends on the number of pins. Limited. Providing a plurality of test stations has been practically used as one method of solving this. FIG. 4 shows this state. In FIG. 4, reference numeral 10 denotes a semiconductor device test apparatus,
Reference numeral 13 denotes the waveform shaper shown in FIG. In the example shown in FIG. 4, when only one test station 15A can test only two semiconductor devices, a test station 15B is added, and a total of four semiconductor devices are used by these two test stations 15A and 15B. This shows a case where DUT1 to DUT4 can be tested.

[0005]

However, it is necessary to operate some semiconductor devices by setting the timing of a signal applied to each device to an optimum timing. For example, in a semiconductor device generally called a CPU, the phase of a clock applied to a clock input terminal has an optimum phase for each device. Therefore, when testing this kind of semiconductor device, at the beginning of the test, for example, an optimal phase of a clock to be applied is measured in advance, and a waveform having the measured phase is generated. The test is performed by setting the clock generation channel of the shaper 13.

[0006] To the semiconductor devices DUT3 and DUT4 to be mounted on the expanded test station 15B, only clocks having the same phase as the clock supplied to the semiconductor devices DUT1 and DUT2 mounted on the test station 15A originally existing are applied. Can not do.
The semiconductor devices under test DUT3 and DUT4 mounted on the added test station 15B are the semiconductor devices under test DUT1 mounted on the other test station 15A.
DUT1 and DUT3 and DUT2 and DUT4 are connected in parallel between DUT2 and DUT2.
Only test pattern signals having the same timing can be supplied to UT1 and DUT3 and DUT2 and DUT4.

For this purpose, DUT1, DUT3 and DU
Both T2 and DUT4 can be tested at the same time only if they are semiconductor devices that operate at the same timing.
In the case of devices operating at different timings, there is a disadvantage that the devices cannot be tested simultaneously. Therefore, even if two test stations 15A and 15B are conventionally provided, after the semiconductor devices under test DUT1 and DUT2 are tested, the setting of the waveform shaper 13 (see FIG. 3) is changed to change the clock timing (see FIG. 3). The test is performed using the test stations 15A and 15B alternately by changing the phase) and testing the semiconductor devices DUT3 and DUT4 under test. As described above, when the test is performed by alternately using the two test stations 15A and 15B, one of the semiconductor devices DUT1 to be tested has an advantage.
Test of the semiconductor devices under test DUT3 and DUT4 can be started immediately after the test of the DUT2 and the test of the DUT2 are completed, and the other test station 15A can perform the device replacement work during the test of the devices under test DUT3 and DUT4. Therefore, it can contribute to speeding up a little.

However, the original purpose of "testing a large number of semiconductor devices under test at the same time and improving the test efficiency" by providing a plurality of test stations has not been achieved. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device test apparatus capable of simultaneously performing a test on a semiconductor device in which a test must be performed by setting different timings for each device.

[0009]

According to a first aspect of the present invention, the same test pattern signal is applied from a pattern generator to a plurality of semiconductor devices under test, and a response signal from the semiconductor device under test is compared with an expected value. In a semiconductor device test apparatus for determining the quality of a semiconductor device under test, switching means is provided in some channels of a supply path of a test pattern signal composed of a plurality of channels to be applied to each semiconductor device. Proposes a semiconductor device test apparatus in which a test pattern signal of another channel is selected and applied to some pins of the semiconductor device under test.

According to a second aspect of the present invention, in the semiconductor device test apparatus according to the first aspect, the plurality of semiconductor devices under test are mounted on different test stations, respectively, and are arranged in parallel with the semiconductor devices under test mounted on each test station. While applying the same test pattern signal,
Switching means is provided in some channels of the supply path of the test pattern signal, and the test pattern signal obtained through a supply path of another test pattern signal to a specific pin of the semiconductor device under test specified in advance by the switching means. A semiconductor device test apparatus to which a configuration for applying a voltage is applied is proposed.

[0011] acting from supply line of the other test pattern signals to a specific pin of the semiconductor device attached to a different test stations according to the construction according to the invention, which is set to supply line of the test pattern signal timing ( Phase). As a result, for example, even if the semiconductor devices have different optimal phases of the clock, the test can be performed by making the phase of the clock applied to one semiconductor device different from the phase of the clock applied to the other semiconductor device. it can.

Therefore, according to the present invention, the purpose of providing a plurality of test stations and simultaneously testing a large number of semiconductor devices can be realized for a semiconductor device which must be operated at different timings as described above. The effect that can be obtained is obtained.

[0013]

FIG. 1 shows an embodiment of a main part of the present invention. Parts corresponding to those in FIG. 4 are denoted by the same reference numerals.
FIG. 1 shows a state in which one DUT 1 and a DUT 2 are mounted on each of the test stations 15A and 15B with one semiconductor device in order to simplify the description. The feature of the present invention is that a plurality of test stations 15
A, semiconductor device under test DUT1 mounted on 15B
And DUT 2 in that a switching means 16 is provided on a supply path of a test pattern signal to be applied to one of the pins specified in advance.

In the example shown in FIG.
A case is shown in which a switching means 16 is provided in a test pattern signal supply path wired to a clock pin CLK of a semiconductor device under test DUT2 mounted on B. Switching means 16 may be constituted by, for example, reed relays, clocks in the test pattern signal to the terminal A of the switching means 16 constituted generated by the waveform shaper 13 from the channel CH _m of the waveform shaper 13 by reed relays Apply CP1.
The timing of the clock CP1 is applied to the clock terminal CLK of the device under test DUT1 mounted on the test station 15A and has a phase that allows the semiconductor device under test DUT1 to operate in an optimal state.

A clock CP2 having a phase different from that of the clock CP1 is applied to the other terminal B of the switching means 16 from another channel CH _n-1 of the waveform shaper 13. This clock CP2 is a clock having the optimum phase of the semiconductor device under test DUT2. By applying the clock CP2 to the contact B of the switching means 16, the switching means 16 is switched to the contact B, whereby the semiconductor device under test DU is switched.
A clock CP2 having an optimum phase for the semiconductor device under test DUT2 can be applied to T2.

As a result, the two test stations 15
A and two semiconductor devices under test DU mounted on 15B
T1 and DUT2 can be tested simultaneously. FIG. 2 shows a case where two or more test stations are provided. In this case, the reference test station 1
The switching means 16 provided on the test pattern supply line that is wired to the clock pin CLK of the test station 15B ... 15N other than 5A, it selects the clock CP2, CP3 ... CP _n, each output separately in this switching means 16 It is configured as follows.

If the configuration shown in FIG. 2 is used to test M semiconductor devices per test station by N test stations, M × n semiconductor devices can be tested simultaneously. You can do it.

[0018]

As described above, according to the present invention, even if the semiconductor device has a property that the phase of the test pattern signal applied to a specific pin of the semiconductor device must be different for each semiconductor device, Since a large number of devices can be tested at the same time, there is an advantage that the efficiency of the test can be improved. In the above description, a clock is exemplified as the pattern signal under test for making the timing different for each semiconductor device. However, the present invention is not necessarily limited to the clock, and it can be easily understood that the present invention can be applied to other various control signals. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram for explaining a modified embodiment of the present invention.

FIG. 3 is a block diagram illustrating an outline of a semiconductor device test apparatus.

FIG. 4 is a block diagram for explaining a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Semiconductor device test apparatus 11 Timing generator 12 Pattern generator 13 Waveform shaper 14 Logic comparator 15A, 15B Test station 16 Switching means

Claims (2)

[Claims] 1. A semiconductor for applying the same test pattern signal from a pattern generator to a plurality of semiconductor devices under test and comparing a response signal from the semiconductor device under test with an expected value to judge pass / fail of the semiconductor device under test. In the device test apparatus, switching means is provided in some channels of a supply path of a test pattern signal composed of a plurality of channels applied to each of the semiconductor devices, and the switching means selects a test pattern signal of another channel. A device for applying a voltage to some pins of a semiconductor device under test. 2. The semiconductor device test apparatus according to claim 1, wherein the plurality of semiconductor devices under test are mounted on different test stations, respectively, and the same test pattern signal is supplied in parallel to the semiconductor devices under test mounted on each test station. In addition to applying the test pattern signal, a switching means is provided in some of the channels of the supply path of the test pattern signal, and the switching means supplies a predetermined pin of the semiconductor device under test through a supply path of another test pattern signal. A device for applying a test pattern signal to the semiconductor device.