JP4263810B2 - Semiconductor memory test apparatus and test method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory test apparatus and test method for testing a semiconductor memory constituted by a semiconductor integrated circuit (referred to as an IC memory in this technical field), and in particular, a plurality of memories capable of high-speed operation. The present invention relates to a semiconductor memory test apparatus and a test method that are suitable for use in testing simultaneously.
[0002]
[Prior art]
FIG. 3 shows an example of a conventional semiconductor memory test apparatus that can test a plurality of semiconductor memories simultaneously. Roughly speaking, this semiconductor memory test apparatus includes a pattern generator PG, a timing generator TG, a waveform generator WF, a drive circuit group DR, a level comparator group LVC, and a plurality of logic comparators LC. It is constituted by. Since the illustrated semiconductor memory test apparatus exemplifies a case where three semiconductor memories MUT1, MUT2, and MUT3 are tested simultaneously, the drive circuit group DR is composed of three driver groups. Similarly, the level comparator The group LVC is also composed of three comparator groups, and three logical comparators LC are provided.
[0003]
The pattern generator PG and the timing generator TG are controlled by a main controller (not shown) generally constituted by a computer system. That is, a test program created by a user (user) is preset in the main controller, and the main controller mainly controls the pattern generator PG and the timing generator TG according to the test program. Although not shown, the timing generator TG is generally composed of a period generator, a clock generator, and a clock control circuit.
[0004]
First, before starting the test of the semiconductor memory, various data are set from the main controller for predetermined components of the test apparatus. After the data is set, the semiconductor memory test is started. When the test start command is given from the main controller to the pattern generator PG, the pattern generator PG becomes operable, and pattern data is generated according to the test program given from the main controller.
[0005]
The pattern data PTN generated from the pattern generator PG is supplied to the waveform generator WF. The waveform generator WF uses the pattern data and the timing signal TS supplied from the timing generator TG to provide three semiconductor memory devices to be tested. Test pattern signals, address signals, and control signals having actual waveforms to be given to MUT1, MUT2, and MUT3 (hereinafter referred to as memory under test) are generated. In a test pattern write cycle for writing a test pattern signal to the memory under test, this control signal controls the operation of the memory under test to an operation for writing the test pattern signal into the memory under test. The address signal specifies the memory cell of the memory under test to which the test pattern signal is written.
[0006]
On the other hand, in the test pattern read cycle for reading the test pattern signal written in the memory under test, the control signal controls the operation of the memory under test to the operation of reading the test pattern signal written in the memory under test. . The address signal specifies the memory cell of the memory under test from which the written test pattern signal is read.
[0007]
In the test pattern write cycle, the test pattern signal output from the waveform generator WF is applied to each of the memories under test MUT1, MUT2, and MUT3 through the related driver group of the drive circuit group DR, and has the address specified by the address signal. It is written in the memory cell. On the other hand, in the test pattern read cycle, an expected value pattern is generated from the pattern generator PG and supplied to the logic comparator LC, and at the same time, a comparison timing signal ST is generated from the timing generator TG to the logic comparator LC. Applied. On the other hand, a read signal and an address signal are applied to the memories under test MUT1, MUT2, and MUT3 through the drive circuit group DR from the waveform generator WF, and test pattern signals written in the memory cells at the specified addresses of these memories under test. Is read out.
[0008]
Test pattern signals (response signals) read from the memories under test MUT1, MUT2, and MUT3, respectively, are compared with reference voltages from a comparison reference voltage source (not shown) in an associated comparator group of the level comparator group LVC. It is determined whether or not it has a predetermined logic level (H logic (high logic) voltage or L logic (low logic) voltage). The response signal determined to have a predetermined logic level is sent to the associated logic comparator LC, where the response signal is the timing of the comparison timing signal ST supplied from the timing generator TG. Then, it is compared with the expected value pattern (data) EXP supplied from the pattern generator PG.
[0009]
If each of the logical comparators LC does not match the expected value pattern EXP from the pattern generator PG and the response signals read from the memories under test MUT1, MUT2, and MUT3, the logic comparator LC reads the response signal from which the response signal has been read. The memory cell of the test memory is determined to be defective, and a fail (FAIL) signal indicating that is generated. Normally, this fail signal is represented by a logic “1” signal and stored in a failure analysis memory (not shown).
[0010]
On the other hand, when the expected value pattern EXP matches the response signal, the logical comparator LC determines that the memory cell of the memory under test from which the response signal is read is normal, and indicates a path ( PASS) signal (usually represented by a logic "0" signal). This pass signal is usually not stored in the failure analysis memory.
When the test is completed, the fail signal stored in the failure analysis memory is read out, and the quality of the tested memory is determined.
[0011]
By the way, in recent years, semiconductor memories are increasingly required to operate at high speed. In order to meet this demand, a semiconductor memory of a type called a synchronous memory having a clock synchronous interface has been proposed. Here, when a clock and a high-order address signal are input from the outside, a synchronous memory generates a low-order address signal in the memory in synchronization with this clock, and each address in the memory is generated by this low-order address signal. As a result of high-speed access, this indicates a type of memory that enables high-speed writing and high-speed reading.
[0012]
In this type of synchronous memory, a function of outputting a clock for synchronizing data read from the memory in a data read cycle is added to the output side of the memory (integrated). When this type of memory is actually incorporated into a product, the timing of the data read from the memory is retimed using the clock output from the added clock output function, and the waveform is shaped and used. The method to do is adopted.
[0013]
The reason will be explained. When high-speed operation is realized, the time during which the waveform of the data read from the memory is fixed becomes extremely short, and the response speed varies depending on manufacturing variations among memory elements. Even if the memory is driven by this, the phase of the data to be read varies for each memory. Therefore, it is difficult to retime data read from each memory simply by using an externally generated clock. For this reason, in this type of memory, a driving clock is taken into the memory and passed through the memory, and in synchronization with the clock, data is read from the memory and output at the same time. That is, read data is output at the same timing as the clock. Then, the timing of data read from each memory is retimed by using a clock output from the clock output function of the memory externally.
[0014]
When testing a plurality of such synchronous memories at the same time, as described above, the output timing (phase) of the test pattern signal (data) read from the memory under test due to variations in the manufacturing process, etc. Variation occurs. Naturally, the clocks output from the clock output function of each memory also vary in their phases.
[0015]
FIG. 4 shows that when the memories under test MUT1, MUT2, and MUT3 shown in FIG. 3 are the above-mentioned synchronous type memories and have manufacturing variations and the like, they were simultaneously tested with the memory test apparatus shown in FIG. It is a timing chart for explaining the operation at the time.
4A shows the input clock CLK0 applied to each of the memories under test MUT1, MUT2, and MUT3, and FIG. 4B shows the internal clocks CLK1, CLK2, and CLK3 that are output through the inside of the memories under test MUT1, MUT2, and MUT3. Respectively. In the example of FIG. 4B, the internal clock CLK2 output from the memory under test MUT2 is slightly delayed from the input clock CLK0, whereas the internal clocks CLK1 and CLK3 output from the memories under test MUT1 and MUT3, respectively. Indicates a state of being delayed from the input clock CLK0 (in the figure, the internal clock CLK1 is delayed by φ1 from the internal clock CLK2, and the internal clock CLK3 is further delayed by φ2 from the internal clock CLK1).
[0016]
The phases of the data D1, D2, and D3 read from the memory under test MUT1, MUT2, and MUT3 also vary greatly due to manufacturing variations and the like. Therefore, as shown in FIG. 4D, the read data D1 output from the memory under test MUT1 is delayed by φ1 from the read data D2 output from the memory under test MUT2, and the read data output from the memory under test MUT3. The data D3 is further delayed by φ2 from the read data D2. Therefore, the phase lag of the read data D1, D2, and D3 and the phase lag of the internal clocks CLK1, CLK2, and CLK3 are the same.
[0017]
In other words, the read data D2 output from the memory under test MUT2 is slightly delayed from the input clock CLK0, whereas the read data D1 and D3 output from the memories under test MUT1 and MUT3 are input. Each of the clocks CLK0 is greatly delayed. 4C shows a command (instruction) for switching between a test pattern write cycle and a test pattern read cycle, and the illustrated example shows a state where a read command for executing the test pattern read cycle is given.
[0018]
Thus, the data (test pattern signals) stored in the memories under test MUT1 and MUT3 are read with a large phase lag due to manufacturing variations, etc., and the internal clocks CLK1 and CLK3 output simultaneously also have a large phase lag. have. On the other hand, since the comparison timing signal ST shown in FIG. 4E supplied from the timing generator TG to each logical comparator LC is generated with reference to the input clock CLK0, the comparison timing signal ST is read from the memory under test. Does not take into account phase lag of data. As a result, the comparison timing signal ST is an appropriate timing signal for the read data D2 having almost no phase delay, but is not an appropriate timing signal for at least the read data D3 having the largest phase delay. Therefore, when semiconductor memories having large delay time variations are mixed, a conventional semiconductor memory test apparatus has a serious drawback that a plurality of memories cannot be tested simultaneously.
[0019]
One object of the present invention is to provide a semiconductor memory test apparatus capable of executing a logical comparison operation at an appropriate timing even when the phases of internal clocks output from a plurality of semiconductor memories to be tested simultaneously vary. Is to provide.
Another object of the present invention is to appropriately correct the logical comparison by correcting the phase of the comparison timing signal correspondingly when there is a variation in the phase of the internal clock output from a plurality of semiconductor memories to be tested simultaneously. A semiconductor memory test method for performing an operation is provided.
[0020]
[Means for Solving the Problems]
To achieve the above object, according to the first aspect of the present invention, at least a pattern for outputting pattern data for generating a test pattern signal, an address signal, and a control signal applied to the semiconductor memory under test is output. A generator, a waveform generator for converting pattern data output from the pattern generator into a test pattern signal having an actual waveform, an address signal, and a control signal, read data read from the semiconductor memory under test, and the pattern A clock for retiming the output timing of read data in a semiconductor memory test apparatus including a logic comparator that compares an expected value pattern output from a generator and determines the quality of the semiconductor memory under test. For testing multiple semiconductor memories under test, which are semiconductor memories that output Before starting, there are a phase measuring means for measuring the phase of the clock output from each of these memories, and a plurality of variable delay circuits in which delay times corresponding to the phases measured by the phase measuring means are respectively set. There is provided a semiconductor memory testing device comprising a plurality of variable delay circuits that delay the comparison timing signals supplied to the respective variable delay circuits by the set delay time and apply them to the corresponding logical comparators.
[0021]
In a preferred embodiment, the phase measuring means measures the phase of the clock output from each of the semiconductor memories under test by inputting the same clock into the plurality of semiconductor memories under test before the start of the test. The delay time corresponding to the measured phase is set in the variable delay circuit associated with each semiconductor memory under test, and the phase of the comparison timing signal output from these variable delay circuits is read out from the associated semiconductor memory under test. Match the data phase. The same number of logical comparators as the variable delay circuits are provided, and each logical comparator is read from the corresponding semiconductor memory under test at the timing of the comparison timing signal provided from the corresponding variable delay circuit. The read data is logically compared with the expected value pattern output from the pattern generator.
[0022]
According to the configuration of the present invention described above, the phase of the data read from each memory under test before starting the test even if the phase of the data read from each of the plurality of memories under test tested at the same time varies. Is measured, and the delay time corresponding to the measured phase is set in the related delay circuit provided in the comparison timing signal path, so that the comparison timing signal having an appropriate phase is related to each memory under test. To the logical comparison means. Therefore, even in a memory such as a high-speed memory, the determination time of read data is very short, and there is a considerable phase difference in the timing of output data, and these can be tested simultaneously. For example, even a synchronous semiconductor memory having a clock synchronous interface can be tested simultaneously.
[0023]
According to the fifth aspect of the present invention, the pattern data output from the pattern generating means is converted into a test pattern signal having an actual waveform, an address signal, and a control signal, and each of them retimes the output timing of read data. A test pattern signal having an actual waveform, an address signal, and a control signal are given to each of a plurality of semiconductor memories to be tested, which are semiconductor memories of the type that output the clock of the above, and the test pattern signals are supplied to these semiconductor memories. Write, read the written test pattern signal from each of the plurality of semiconductor memories under test, logically compare with the expected value pattern at the timing of the comparison timing signal provided from the timing generation means, and determine whether the semiconductor memory under test is good or bad In the semiconductor memory test method for determining Before starting the test of the semiconductor memory under test, inputting the same clock to the semiconductor memory under test, measuring the phase of the clock output from each of the semiconductor memory under test, A step of setting a delay time corresponding to the measured value of the phase of the clock to be output in each comparison timing delay means associated with each semiconductor memory under test, the read data read from each semiconductor memory under test, and the expected value There is provided a semiconductor memory test method including a step of logically comparing a pattern with a timing of a delayed comparison timing signal provided from the comparison timing delay means.
[0024]
According to the above-described method of the present invention, the phase of the comparison timing signal is corrected according to the amount of phase variation even if the phase of the internal clock output from each of the plurality of semiconductor memories to be tested simultaneously varies. Thus, an appropriate logical comparison operation can be executed.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to FIGS. 1, parts and elements corresponding to those in FIG. 3 are denoted by the same reference numerals, and the description thereof is omitted unless necessary.
FIG. 1 is a block diagram showing an embodiment of a semiconductor memory test apparatus according to the present invention. Similarly to the conventional semiconductor memory test apparatus shown in FIG. 3, this semiconductor memory test apparatus also has a pattern generator PG, a timing generator TG, a waveform generator WF, a drive circuit group DR, a level comparator group LVC, and A plurality of logical comparators LC are provided.
[0026]
In the present invention, in the test pattern read cycle, the same number of variable delays as the memories under test MUT1, MUT2, and MUT3 are provided in the supply path of the comparison timing signal ST supplied from the timing generator TG to each of the plurality of logical comparators LC. Circuits DY1, DY2, and DY3 are provided so as to match the phase of the comparison timing signal ST with the phase of data read from the memory under test. In the example shown in FIG. 1, like the conventional memory test apparatus shown in FIG. 3, since the number of memories under test simultaneously tested is 3, the drive circuit group DR is composed of three driver groups. The level comparator group LVC is also composed of three comparator groups, and three logic comparators LC are provided. Further, although three variable delay circuits are provided, it goes without saying that the number of these elements is changed according to the number of memories to be tested simultaneously. The number of memories under test to be tested simultaneously is arbitrary, and there may be a large number such as 32 or 64, for example.
[0027]
Further, in this embodiment, before starting the test of the memories under test MUT1, MUT2, and MUT3, the phase of the clock output from these memories under test is measured, and the associated variable delay circuit is based on the measurement result. A phase measuring device CP for setting delay times of DY1, DY2, and DY3 is provided.
That is, before starting the test, clocks are input to the memories under test MUT1, MUT2, and MUT3, and the phase delay of the clocks output from these memories under test is measured by the phase measuring device CP. The phase measuring device CP sets the delay times of the corresponding variable delay circuits DY1, DY2, and DY3 according to the magnitude of the measured phase delay. The delay time setting of the variable delay circuits DY1, DY2, and DY3 by the phase measuring device CP is executed once before the test is started every time the memory under test is exchanged, and after the test is started, those tests are finished. Until then, the set values of the variable delay circuits DY1, DY2, and DY3 are maintained as they are.
[0028]
Thus, after the test starts, the comparison data supplied from the timing generator TG to the variable delay circuits DY1, DY2, DY3 when the data written from the memories under test MUT1, MUT2, MUT3 is read in the test pattern read cycle. The timing signal ST is delayed by the delay time set in these variable delay circuits and supplied to the corresponding logical comparator LC. Therefore, since these comparison timing signals ST are delayed by a time corresponding to the phase delay of the data read from the corresponding memory under test and applied to the corresponding logical comparator LC, the data read from the memory under test and the pattern generator It is possible to logically compare the expected value pattern EXP given from PG at an appropriate timing.
[0029]
The operation of the memory test apparatus having the above configuration will be described in detail with reference to the timing chart of FIG.
FIG. 2A shows the input clock CLK0 applied to each of the memories under test MUT1, MUT2, and MUT3, and FIG. 2B shows the internal clocks CLK1, CLK2, CLK output through the inside of the memories under test MUT1, MUT2, and MUT3. Each of CLK3 is shown. In the example of FIG. 2B, the internal clock CLK2 output from the memory under test MUT2 is slightly delayed from the input clock CLK0, whereas the internal clock CLK1 output from the memory under test MUT1 is less than the internal clock CLK2. The internal clock CLK3 output from the memory under test MUT3 is delayed by φ2 further than the internal clock CLK1.
[0030]
In other words, even if the same input clock CLK0 is input to the memories under test MUT1, MUT2, and MUT3, each of the devices under test is caused by manufacturing variations when the clock passes through the memories under test and is output. Since there is a difference in the delay time inside the memory, the internal clocks CLK1, CLK2, and CLK3 output from the memories under test MUT1, MUT2, and MUT3 have a phase delay corresponding to the delay time variation of each memory under test. appear.
[0031]
FIG. 2D shows read data D1, D2, and D3 read from the memories under test MUT1, MUT2, and MUT3, respectively, in the test pattern read cycle. There is a phase difference between the read data D1, D2, and D3 because there is a difference in delay time in each memory under test due to manufacturing variations. In addition, since the read data D1, D2, and D3 are output in synchronization with the internal clocks CLK1, CLK2, and CLK3, the read data D1 output from the memory under test MUT1 is read data D2 output from the memory under test MUT2. The read data D3 output from the memory under test MUT3 is further delayed by φ2 from the read data D1 output from the memory under test MUT1. That is, the read data D1 and the internal clock CLK1, the read data D2 and the internal clock CLK2, and the read data D3 and the internal clock CLK3 are output in exactly the same phase.
[0032]
FIG. 2E shows a comparison timing signal ST output from the timing generator TG and supplied to the variable delay circuits DY1, DY2, and DY3. If this comparison timing signal ST is input to each logical comparator LC with the phase as it is, it is easy that at least the logical comparison of the read data D3 is not normally performed in the case of the read data shown in FIG. 2D. I understand.
[0033]
FIG. 2F shows waveforms of clocks CLK1-1, CLK2-2, and CLK3-3 output from the memory under test when the same clock is input to the memories under test MUT1, MUT2, and MUT3 before the start of the test. Indicates. In this embodiment, these output clocks CLK1-1, CLK2-2, and CLK3-3 are taken into the phase measuring device CP, and the clocks CLK1-1, CLK2-2, and CLK3-3 are compared with each other by the phase measuring device CP. Measure the phase difference. In this embodiment, since there are three memories under test, of the three clocks CLK1-1, CLK2-2, and CLK3-3 output from each of the memories under test, the clock with the intermediate phase delay value is selected. The phase is adopted as the reference phase. As described above, when the phase of the clock having an intermediate phase delay is adopted as the reference phase, there is an advantage that the time width of the delay time set in the variable delay circuits DY1, DY2, and DY3 can be narrowed.
[0034]
In the example shown in FIG. 2F, since the clock CLK1-1 output from the memory under test MUT1 is located between the remaining two clocks, the phase of the clock CLK1-1 is determined as the reference phase. As a result, it is assumed that the clock CLK2-2 output from the memory under test MUT2 is a phase advanced by, for example, φ1 from the reference phase, and the clock CLK3-3 output from the memory under test MUT3 is, for example, φ2 from the reference phase. Only a delayed phase can be detected.
[0035]
Based on the detected phase difference, the phase measuring device CP sets a delay amount τ0 (a certain delay amount, for example, 10 ns is defined as τ0) in the variable delay circuit DY1 related to the clock CLK1-1, and the clock CLK2- 2 is set to the delay amount −τ1 (which is smaller than 10 ns) corresponding to the lead phase φ1, and the variable delay circuit DY3 related to the clock CLK3-3 corresponds to the delay phase φ2. Set the delay amount + τ2 (which is larger than 10 ns).
[0036]
By setting the delay times of the variable delay circuits DY1, DY2, and DY3 in this way, as shown in FIG. 2G, the comparison timing signal S1 that has passed through the variable delay circuit DY1 is delayed by a delay time corresponding to the delay amount τ0. The comparison timing signal S2 passed through the variable delay circuit DY2 and supplied to the corresponding logical comparator LC is delayed by a delay time corresponding to the delay amount -τ1 and supplied to the corresponding logical comparator LC. The comparison timing signal S3 that has passed through the delay circuit DY3 is delayed by a delay time corresponding to the delay amount + τ2 and supplied to the corresponding logical comparator LC. That is, the comparison timing signal S2 is given a phase difference of −τ1 with respect to the comparison timing signal S1, and the comparison timing signal S3 is given a phase difference of + τ2 with respect to the comparison timing signal S1.
[0037]
As a result, as can be easily understood by referring to the read data D1, D2, D3 in FIG. 2D and the comparison timing signals S1, S2, S3 in FIG. Thus, the timing of the comparison timing signal S2 coincides with the read data D2, and the timing of the comparison timing signal S3 coincides with the read data D3. Thus, in each logical comparator LC, even if there are mixed semiconductor memories with large variations in delay time, they are read from the corresponding memories under test MUT1, MUT2, and MUT3 by these comparison timing signals S1, S2, and S3. The read data D1, D2, D3 and the expected value pattern EXP supplied from the pattern generator PG can be logically compared at an appropriate timing.
[0038]
FIG. 5 is a waveform diagram for explaining an example of a method for measuring the phase of the clock output from each memory under test before the test. FIG. 5A shows the waveform of the clock CLK output from the memory under test. In this example, in the vicinity of the boundary between the H logic area (pass area) and the L logic area (fail area) of the clock CLK, FIGS. As shown in the figure, the comparison timing pulse is moved in the order of H logic area → L logic area → H logic area → L logic area... To find the boundary point between the H logic area and the L logic area. . The time from the time when the clock CLK is input to this boundary point is used as the measured value of the phase φM of this clock. Of course, the phase of the clock output from the memory under test may be measured using other measurement methods.
[0039]
In the above embodiment, the phase of the clock output from the memory under test is measured before the start of the test. However, since the read data has L logic time, it is difficult to measure the phase of the read data. If the delay time of the variable delay circuit is set by measuring the phase of the read data, the comparison timing signal cannot be corrected in time because the data is read at high speed. Therefore, before the test is started, the same clock is input to each memory under test, and the phase of the clock output with almost the same phase as the read data is measured.
[0040]
Although the invention has been described with reference to the preferred embodiments shown in the drawings, it will be understood by those skilled in the art that various modifications, changes and improvements may be made to the above-described embodiments without departing from the spirit and scope of the invention. It will be obvious. Accordingly, the invention is not limited to the illustrated embodiments, but encompasses all such variations, modifications, and improvements that fall within the scope of the invention as defined by the claims.
[0041]
【The invention's effect】
As apparent from the above description, according to the present invention, since the waveform of the read data changes at a high speed as in the case of a synchronous memory having a clock synchronous interface, the time during which the waveform is fixed is extremely high. Even if the semiconductor memory is a short semiconductor memory and a difference occurs in the timing at which read data is output, a great advantage is obtained that a plurality of semiconductor memories can be normally tested simultaneously.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a semiconductor memory test apparatus according to the present invention.
2 is a timing chart for explaining the operation of the semiconductor memory test apparatus shown in FIG. 1; FIG.
FIG. 3 is a block diagram showing an example of a conventional semiconductor memory test apparatus.
4 is a timing chart for explaining the operation of the semiconductor memory test apparatus shown in FIG. 3;
FIG. 5 is a waveform diagram for explaining an example of a method for measuring a phase of a clock output from a memory under test.
[Explanation of symbols]
PG: Pattern generator
TG: Timing generator
WF: Waveform generator
LC: Logic comparator
CP: Phase measuring device
DY1, DY2, DY3: Variable delay circuit

Claims (6)

A pattern generator for outputting at least pattern data for generating a test pattern signal, an address signal, and a control signal applied to the semiconductor memory under test;
A waveform generator that converts pattern data output from the pattern generator into a test pattern signal having an actual waveform, an address signal, and a control signal;
In a semiconductor memory test apparatus including a logical comparator that compares read data read from the semiconductor memory under test with an expected value pattern output from the pattern generator and determines whether the semiconductor memory under test is good or bad.
Before starting the test of a plurality of semiconductor memories under test, each of which is a type of semiconductor memory that outputs a clock for retiming the output timing of read data, measure the phase of the clock output from each memory. Phase measuring means for
A plurality of variable delay circuits each having a delay time corresponding to the phase measured by the phase measuring means, wherein the comparison timing signal supplied to each variable delay circuit is delayed by the set delay time. And a plurality of variable delay circuits applied to the corresponding logical comparators. The phase measuring means measures the phase of the clock output from each of the semiconductor memories under test by inputting the same clock to the plurality of semiconductor memories under test before starting the test, and corresponds to the measured phase. The delay time to be set in the variable delay circuit associated with each semiconductor memory under test, the phase of the comparison timing signal output from these variable delay circuits is matched with the phase of the read data read from the associated semiconductor memory under test,
The logical comparators are provided in the same number as the variable delay circuits, and each logical comparator is read data read from the corresponding semiconductor memory under test at the timing of the comparison timing signal given from the corresponding variable delay circuit. 2. The semiconductor memory test apparatus according to claim 1, wherein a logical comparison is made between the expected value pattern output from the pattern generator and the expected value pattern. 2. The semiconductor memory test apparatus according to claim 1, wherein each of the plurality of semiconductor memories to be tested is a synchronous semiconductor memory having a clock synchronous interface. 3. The semiconductor memory test apparatus according to claim 2, wherein each of the plurality of semiconductor memories to be tested is a synchronous semiconductor memory having a clock synchronous interface. This is a type of semiconductor memory that converts the pattern data output from the pattern generating means into a test pattern signal having an actual waveform, an address signal, and a control signal, and each outputs a clock for retiming the output timing of read data. A test pattern signal having an actual waveform, an address signal, and a control signal are given to each of the plurality of semiconductor memories to be tested, and the test pattern signals are written to the semiconductor memories to be tested. In the semiconductor memory test method for reading out from each of the semiconductor memories under test, logically comparing with the expected value pattern at the timing of the comparison timing signal given from the timing generation means, and determining the quality of the semiconductor memory under test,
Before starting the test of the plurality of semiconductor memories under test, inputting the same clock to the semiconductor memories under test and measuring the phases of the clocks respectively output from the semiconductor memories under test;
Setting a delay time corresponding to the measured value of the phase of the clock output from each semiconductor memory under test in the comparison timing delay means associated with each semiconductor memory under test;
Logically comparing the read data read from each semiconductor memory under test and the expected value pattern at the timing of the delayed comparison timing signal provided from the comparison timing delay means. Semiconductor memory test method. 6. The semiconductor memory testing method according to claim 5, wherein each of the plurality of semiconductor memories to be tested is a synchronous semiconductor memory having a clock synchronous interface.

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