JP2952131B2 - Test equipment for semiconductor integrated circuits - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit (AC).
The present invention relates to a test apparatus for a semiconductor integrated circuit that performs a test including a characteristic test.

[0002]

2. Description of the Related Art Various tests including an AC (AC) characteristic test of a semiconductor integrated circuit are performed during a development stage or a mass production of the semiconductor integrated circuit. This AC characteristic test measures a signal propagation delay time (hereinafter, referred to as “delay time”) between an input terminal and an output terminal of a semiconductor integrated circuit, and a rise time and a fall time of an output waveform.

FIG. 1 is a block diagram showing an electrical configuration of a test apparatus for a semiconductor integrated circuit which is a premise of the present invention. This semiconductor integrated circuit test apparatus is a semiconductor integrated circuit AC
Perform tests including characteristic tests. The timing signal is output from the timing generator 51 to the pattern generation circuit 50, the waveform format circuit 52, and the comparison circuit 57 according to the test start signal from the pattern generator 50. The waveform format circuit 52 shapes the waveform of the test pattern signal from the pattern generator 50 using the timing signal, and outputs the waveform to the drive circuit 53 as a test signal. The test signal input to the drive circuit 53 is adjusted in level and output to a semiconductor integrated circuit (hereinafter, referred to as a “circuit under test”) 55 to be tested. Next, the comparator 57 compares the output signal from the circuit under test 55 with the expected value included in the corresponding pattern signal from the pattern generator 50, and outputs a coincidence signal if the values match. If not, a mismatch signal is output.

In this semiconductor integrated circuit test apparatus,
When measuring the delay time of the circuit under test 55 in the AC characteristics, for example, a timing signal is generated at a fixed time interval from the time when the test signal is input from the timing generator 51 to the circuit under test 55, and the timing is synchronized with the timing. Then, the time when the expected value data and the output data in the comparator 57 match is measured. Therefore, the delay time of the output signal of the circuit under test 55 can be measured from that time.

FIG. 2 is a block diagram showing a more detailed electrical configuration of comparison circuit 57 shown in FIG. The comparison circuit 57 includes a plurality of n outputs CH1 from the circuit under test 55.
To CHn at the same time, the storage circuit 61,
Each of the signals input to and output from the comparison determination circuit 62 and the comparator 63 is n. In the following description, n
When the input / output signals are collectively referred to, the suffixes 1 to n are omitted. For example, the expected value signals EV1 to EVn are collectively referred to as the expected value signal EV.

The pattern generation circuit 50 outputs an address signal ADR to the storage circuit 61 and specifies the value of the expected value signal EV of the circuit under test 55 stored in the storage circuit 61 and the value of the mask signal MASK. . Mask signal MAS
K is a signal for controlling whether or not to compare and determine the output value of the circuit under test 55 with the value of the expected value signal EV. The timing generation circuit 51 receives the strobe signal ST from the test start signal START from the pattern generation circuit 50.
B is generated at regular intervals and output to the comparison and determination circuit 62.

The comparator 63 determines whether the value of the output signal CH from the circuit under test 55 is at a high level or a low level. Comparator 63
At a, a comparison is made between the high-level threshold VOH and the value of the output signal CH, and the value of the output signal CH is
If not less than H, the output signal CM
PH is output. The comparator 63b compares the low-level threshold VOL with the value of the output signal CH. If the value of the output signal is equal to or smaller than the threshold VOL, the comparator 63b determines that the output signal is low and outputs the output signal CMPL. Is done.

[0008] The comparison determination circuit 62 outputs a strobe signal ST
B, the value of the expected value signal EV from the storage circuit 61 and the output signal CMP (signal CMPH) from the comparator 63.
And a value of the mismatch signal FAIL is output to the pattern generation circuit 50 as "1" if the values do not match. Therefore, by measuring the output time of the strobe signal STB when the value of the mismatch signal FAIL changes from “1” to “0” (or “0” to “1”), the input time of the output signal of the circuit under test is measured. The delay time for the signal is calculated, and the AC characteristics can be measured.

FIG. 6 is an electric circuit diagram of the conventional comparison and judgment circuit 62 shown in FIG. The expected value signal EV is input to the input terminal S of the selection circuit 1, and an output signal CMP to be compared with the expected value signal EV is selected. When the value of the expected value signal EV is "1", the output signal CMPH from the comparator is selected and output from the output terminal Y of the selection circuit 1. When the value of the expected value signal EV is "0", the signal from the comparator is output. The output signal CMPL is selected and output from the output terminal Y of the selection circuit 1.

EX. The OR gate 2 detects a mismatch between the value of the expected value signal EV and the output signal CMP for comparing the value of the expected value signal EV with the value of the expected value signal. That is, when the value of the expected value signal EV is “1” and the value of the output signal CMPH is “0”, and when the value of the expected value signal EV is “0” and the value of the output signal CMPL is “1”, EX . The value of the output terminal of the OR gate 2 is “1”. The EX. The output from the OR gate 2 and the mask signal inverted MASK are given, and only when the value of the mask signal inverted MASK is “1”,
EX. The output of the OR gate 2 is supplied to the input terminal D of the D flip-flop 4 via the AND gate 3.
The D flip-flop 4 is connected to the AN input to the input terminal D.
The output from the D gate 3 is latched in synchronization with the strobe signal STB input to the input terminal CP. That is,
The result of comparison between the value of the expected value signal EV and the value of the output signal CMP of the circuit under test is latched in synchronization with the strobe signal STB. The strobe signal STB is applied to the input terminal CP
When the value of the expected value signal EV and the output value of the circuit under test do not match, the value of the mismatch signal FAIL output from the output terminal Q becomes "1". The value of FAIL becomes “0”. The value of the mismatch signal FAIL is held until the reset signal RESET is input. When the reset signal RESET is input to the input terminal R of the D flip-flop 4, the value of the mismatch signal FAIL is reset to “0”.

FIG. 7 is a graph showing the result of measuring the AC characteristics of the circuit under test 55 using the above-described test apparatus for a semiconductor integrated circuit. This graph is called a shmoo plot, in which the vertical axis is assigned the power supply voltage, and the horizontal axis is assigned the delay time of the output of the circuit under test 55. For example, power supply voltage 6.0
When creating a shmoo plot of the AC characteristics at V, first, the power supply voltage of the circuit under test 55 is set to 6.0 V, and the strobe signal STB for measuring the AC characteristics (the above-described expected value and the output of the circuit under test 55). The generation timing of a synchronization signal for comparing with a signal value is changed from 20 ns to 100 ns every 2 ns. As a result of comparing the expected value and the output signal value in synchronization with the timing of generation of the strobe signal STB, in response to the above-described mismatch signal FAIL indicating whether or not the values match, in the case of mismatch, ". Is printed, and if they match, "*" is printed. Similarly, the test is repeated while changing the power supply voltage from 5.8 V to 4.0 V in steps of 0.2 V, and the Shmoo plot shown in FIG. 7 can be created. Thus, the characteristics of the delay time corresponding to each power supply voltage of the circuit under test 55, that is, the AC characteristics can be measured.

[0012]

As described above, in a conventional test apparatus for a semiconductor integrated circuit, the AC characteristics of a circuit under test are measured, and a Shmoo plot or the like is created and evaluated. For example, when a shmoo plot as shown in FIG. 7 is created, a test for comparing an expected value and an output value in synchronization with the strobe signal STB 41 times for each power supply voltage (hereinafter referred to as a “test cycle”). (Abbreviated). Also, the power supply voltage to be measured (4.0 V to 6.0 V)
Is a total of 11 parameters, so it is necessary to repeat the above test cycle 41 × 11 = 451 times to create a Shmoo plot.

Conventionally, when such a shmoo plot is created, a dedicated program for outputting a strobe signal for testing is generally developed, or a utility program of a test apparatus for a semiconductor integrated circuit is used. . There is also a test apparatus that automatically changes the output timing of a strobe signal only with hardware in order to reduce the load on software. However, the number of test cycles is the same regardless of whether the test strobe signal is output by hardware or software.

Further, since the actual evaluation of the AC characteristics is performed for a plurality of pins and a plurality of items of the circuit under test, it takes a long time to evaluate the AC characteristics.

An object of the present invention is to provide a test apparatus for a semiconductor integrated circuit capable of performing an AC characteristic test of a circuit under test in a short time.

[0016]

According to the present invention, an input signal is supplied to an input terminal of a semiconductor integrated circuit, an output signal from an output terminal of the semiconductor integrated circuit is detected, and a delay time of the output signal with respect to the input signal is set. AC to measure and obtain AC characteristics
In a test apparatus for a semiconductor integrated circuit for performing a characteristic test, a waveform generating means for applying a predetermined input signal to an input terminal of the semiconductor integrated circuit for each predetermined test cycle, and an output signal from an output terminal of the semiconductor integrated circuit. Comparing means for comparing a predetermined expected value with a predetermined timing for each test cycle at a predetermined timing; and in a first test cycle, at a time after a predetermined minimum delay time elapses from the start of the measurement of the AC characteristics for each test cycle, In a subsequent test cycle, a first strobe generating means for supplying a first strobe signal defining the predetermined timing to the comparing means at a time later by a predetermined unit time, and in the first test cycle, the AC in each test cycle. At the time after the elapse of the predetermined maximum delay time from the start of characteristic measurement, A second strobe generating means for providing a second strobe signal defining the predetermined timing to the comparing means at an earlier time by a predetermined unit time; and for each test cycle, the input signal, the expected value, and the maximum value. Pattern signal generation means for providing a pattern signal defining a delay time, the minimum delay time, and the unit time to a waveform generation means, a comparison means, a first strobe generation means, and a second strobe generation means. This is a test device for a semiconductor integrated circuit.

[0017]

According to the present invention, the pattern signal generating means generates a pattern signal representing a test pattern, and according to the pattern signal, provides an input signal to the waveform generating means for each test cycle and provides an expected value to the comparing means. , The minimum delay time and the unit time to the first strobe generating means, and the maximum delay time and the unit time to the second strobe generating means.

In the first test cycle, the first strobe generating means generates the first strobe at a time after a predetermined minimum delay time has elapsed from the input time of the input signal, and at a time later by a predetermined unit time in subsequent test cycles. A signal is generated and provided to the comparison means. The second strobe generating means generates a second strobe signal at a time after a predetermined maximum delay time has elapsed from the input time of the input signal in the first test cycle, and at a time earlier by a predetermined unit time in subsequent test cycles. And give it to the comparison means.

The comparing means compares the output signal from the semiconductor integrated circuit with the expected value in synchronization with the first strobe signal and the second strobe signal in each test cycle.

Therefore, the expected value and the output signal of the semiconductor integrated circuit can be sequentially compared with each other by the two strobe signals in each test cycle as described above. The delay time can be measured in a short time, and the AC characteristics can be obtained.

[0021]

FIG. 1 is a block diagram showing a schematic electrical configuration of a semiconductor integrated circuit test apparatus according to one embodiment of the present invention. This semiconductor integrated circuit test apparatus performs tests including an AC characteristic test of a semiconductor integrated circuit. The timing signal is output from the timing generator 51 to the pattern generation circuit 50, the waveform format circuit 52, and the comparison circuit 57 according to the test start signal from the pattern generator 50. The waveform format 52 shapes the waveform of the test pattern signal from the pattern generator 50 using a timing signal, and outputs the waveform to the drive circuit 53 as a test signal. The level of the test signal input to the drive circuit 53 is adjusted and output to a semiconductor integrated circuit to be tested (hereinafter, referred to as “circuit under test”). Next, the comparator 57 compares the output signal from the circuit under test 55 with the expected value included in the pattern signal from the pattern generator 50, and outputs a coincidence signal if the values match, and must match. Output a mismatch signal.

In this semiconductor integrated circuit test apparatus,
When measuring the delay time (signal propagation delay time between the input terminal and the output terminal) of the circuit under test 55 in the AC characteristics, a strobe signal is sequentially generated from the timing generator 51 at a predetermined timing described later. The comparator 57 compares the expected value with the output value of the circuit under test 55 in synchronization with the timing. Therefore, the delay time of the output signal of the circuit under test 55 can be measured from the comparison result.

FIG. 2 is a block diagram showing a more detailed electrical configuration of comparison circuit 57 shown in FIG. The comparison circuit 57 includes a plurality of n outputs CH1 from the circuit under test 55.
To CHn at the same time, the storage circuit 61,
Each of the signals input to and output from the comparison determination circuit 62 and the comparator 63 is n. In the following description, n
When the input / output signals are collectively referred to, the suffixes 1 to n are omitted. For example, the expected value signals EV1 to EVn are collectively referred to as the expected value signal EV.

The pattern generation circuit 50 outputs the address signal ADR to the storage circuit 61, and specifies the value of the expected value signal EV of the circuit to be measured and the value of the mask signal MASK stored in the storage circuit 61. Mask signal MASK
Is a signal for controlling whether or not to compare and determine the output value of the circuit under test 55 with the value of the expected value signal EV. The timing generation circuit 51 receives the strobe signal STB from the test start signal START from the pattern generation circuit 50.
Is generated at regular intervals and output to the comparison and judgment circuit 62.

The value of the output signal CH from the circuit under test 55 is determined by the comparator 63 as to whether it is at a high level or a low level. Comparator 63
a, the threshold value VOH and the output signal C are at the high level.
The value of the output signal is compared with the threshold value VO.
If not less than H, the output signal CM
PH is output. The comparator 63b compares the low-level threshold value VOL with the value of the output signal CH. If the output signal value is equal to or less than the threshold value VOL, it is determined that the output signal CH is low, and the output signal CMPL is output. Is done.

The comparison / determination circuit 62 outputs a strobe signal ST
B, the value of the expected value signal EV from the storage circuit 61 and the output signal CMP (signal CMPH) from the comparator 63.
And the value of the signal CMPL).

FIG. 3 is an electric circuit diagram of the comparison and judgment circuit 62 of the present invention shown in FIG. The expected value signal EV is input to the input terminal S of the selection circuit 70, and when the value of the expected value signal EV is “1”, the output signal CMPH from the comparator is output.
Is selected and output from the output terminal Y of the selection circuit 70,
When the value of the expected value signal EV is “0”, the output signal CMPL from the comparator is selected and output from the output terminal Y of the selection circuit 70.

EX. The OR gate 71 outputs the expected value signal EV
Is not coincident with the output signal CMP to be compared with the expected value. That is, when the value of the expected value signal EV is “1” and the value of the output signal CMPH is “0”, and when the value of the expected value signal EV is “0” and the value of the output signal CMPL is “1”, EX . The value of the output signal of the OR gate 71 is “1”. The EX. The output from the OR gate 71 and the mask signal inverted MASK are provided. Only when the value of the mask signal inverted MASK is “1”, EX. O
The output of the R gate 71 is supplied to the D gate via the AND gate 72.
It is provided to each input terminal D of flip-flops 73 and 74.

D flip-flop 73 latches the output signal from AND gate 72 input to input terminal D in synchronization with strobe signal STBE input to input terminal CP. The strobe signal STBE is generated by a predetermined time Δt for each test cycle sequentially from the timing delayed by the maximum delay time te from the measurement start time of the AC characteristics in the above-described test cycle, which is predetermined at the time of the AC characteristics test of the circuit under test 55. Output faster. Before the timing delayed by the maximum delay time te, the expected value of the circuit under test 55 always coincides with the output value, and this time te is known in advance from the specifications of the circuit under test.

That is, the result of comparing and determining the value of the expected value signal EV with the value of the output signal CMP of the circuit under test 55 is
The latch is performed in synchronization with the strobe signal STBE. When the strobe signal STBE is input to the terminal CP and the value of the expected value signal EV does not match the output value of the circuit under test 55, a failure signal FAILE is output from the output terminal Q.
When the reset signal RESET is input to the input terminal R of the D flip-flop 73, the value of the failure signal FAILE is initialized to “0”.

D flip-flop 74 latches an output signal from AND gate 72 input to input terminal D in synchronization with strobe signal STBS input to input terminal CP.

The strobe signal STBS is constant in each test cycle from the timing delayed by the minimum delay time ts from the start time of measuring the AC characteristics in the above-described test cycle, which is predetermined at the time of the AC characteristics test of the circuit under test 55. The output is delayed by the time Δt. Before the timing delayed by the minimum delay time ts, the circuit under test 5 is always
5 does not match the output value, and the time ts
Is known in advance from the specifications of the circuit under test 55 and the like.

Therefore, two strobe signals, ie, strobe signal STBS and strobe signal STBE, are output for each test cycle. Next, the result of comparing and determining the value of the expected value signal EV and the value of the output signal CMP of the circuit under test 55 is latched in synchronization with the strobe signal STBS. When the strobe signal STBS is input to the terminal CP and the value of the expected value signal EV and the output value of the circuit under test 55 do not match, the output terminal inverting Q outputs the defective signal F
AIL is not output. The D flip-flop 74
When the set signal SET is input to the input terminal S, the value of the failure signal FAIL is initialized to “0”.

The OR gate 75 outputs a mismatch signal FAILE.
Alternatively, when the value of the mismatch signal FAILS becomes “1”, the mismatch signal FAIL is output with a value of “1”.

FIG. 4 is a more detailed electric block diagram of the timing generation circuit 51 shown in FIG. A portion 80 surrounded by a broken line is added in the embodiment of the present invention. When the test start signal START is given from the pattern generation circuit 50, the rate timing generation circuit 81
A rate timing signal MCL serving as a reference timing signal for measuring the AC characteristics in the test cycle of the above-described AC characteristic test is generated and output to the strobe S output circuit 86 and the strobe E output circuit 89. At the same time, it outputs the clock signal CLK to the strobe S output circuit 86 and the strobe E output circuit 89. The strobe S storage circuit 82 and the strobe E output circuit 83 previously store a plurality of output timing values of the strobe signal STB,
Address signal RT output from pattern generation circuit 50
Selected by TC.

The pattern generation circuit 50 determines the minimum delay time t of the aforementioned strobe signal STBS in the test cycle.
When s and the maximum delay time te of the strobe signal STBE are determined, an address signal RTTC corresponding to those time values is output to the strobe S storage circuit 82 and the strobe E storage circuit 83. Next, the strobe S storage circuit 82 outputs a value corresponding to the selected minimum delay time ts to the strobe S output circuit 86 via the adder 85,
Strobe E storage circuit 83 outputs the selected value to strobe E output circuit 89 via subtractor 88.

Next, the strobe S output circuit 86 counts down a value representing a value corresponding to the input minimum delay time ts in synchronization with the clock signal CLK with reference to the timing at which the rate timing signal MCL is input. I do. When the count value becomes 0, the output from the strobe S output circuit 86 via the strobe variable delay circuit 91
A strobe signal STBS is output. Therefore, strobe signal STBS is applied to rate timing signal MCL.
Is output at a timing delayed by the minimum delay time ts with reference to Similarly, the strobe signal STBE has a maximum delay time te based on the rate timing signal MCL.
Output at delayed timing.

Although the strobe signal STBS and the strobe signal STBE are output in synchronization with the clock CLK, if it is desired to change the output timing between the cycles of the clock CLK, the strobe variable delay circuit 91,
The adjustment is performed by 92.

The A register 100 accumulates and adds the values of the B register 101 via the adder 102. Therefore, every time the A register 100 adds to the B register 101, the value of the A register 100 increases by the value of the B register 101. The adder 102 outputs the added value of the A register 100 and the B register to the adder 85 and the subtractor 88. The value of the A register 100 is set to 0 in an initial state.

The adder 85 includes a strobe S storage circuit 82
And the output value of the adder 102 are added and output to the strobe S output circuit 86. The subtracter 88 subtracts the output value of the adder 102 from the output value of the strobe E storage circuit 83 and outputs the result to the strobe E output circuit 89.

Therefore, by adding the A register 100 and the B register 101 in synchronization with the rate timing MCL, the value output from the strobe S circuit 82 in synchronization with the rate timing MCL is stored in the B register 1
The value of 01 is added. Thereby, the strobe S
The strobe signal STBS output from the output circuit is output for each test cycle later by the time Δt corresponding to the value of the B register 101 from the timing delayed by the aforementioned minimum delay time ts. Similarly, the strobe signal STBE output from the strobe E output circuit is output earlier by the time Δt from the timing delayed by the maximum delay time te in each test cycle.

The controller 105 controls the adder 85, the subtractor 88, the adder 102, the A register 100, the B register 101 and the like. That is, the controller 105
Determines the test conditions of the AC characteristic test such as the test cycle, the output timing of the strobe signal STBS and the output timing of the strobe signal STBE, based on the address signal ADR from the pattern generation circuit 50, and based on the determination, determines the above-described adder, register, etc. Control.

FIG. 5 is a timing chart when an AC characteristic test for obtaining a delay time of a circuit under test is performed using the semiconductor integrated circuit test apparatus of the present invention shown in FIGS. In this test, the value of the output signal CH is
The rise delay time from when the threshold value VOH changes from “0” to “1” is obtained. In a test cycle for obtaining the delay time of the circuit under test, the time for actually performing measurement is represented by T
AC (hereinafter referred to as “rate TAC”). In each test cycle, first, the internal state of the test apparatus is set based on the pattern signal, and then the AC characteristics are actually measured at the rate TAC. Therefore, this rate TAC
Is set to "1" and the mask signal M
Set the value of ASK to "1".

The aforementioned minimum delay time ts of the strobe signal STBS and the maximum delay time te of the strobe signal STBE
Is the start time tm of the rate TAC as shown in FIG.
1 is set as a reference. Although the start time tm1 does not always coincide with the test signal input to the circuit under test,
The input test signal and the start time tm1 are output in the same cycle, and their time intervals are known in advance.
By measuring the delay time of the circuit under measurement based on the time tm1, an accurate delay time can be obtained.

The output timing for each test cycle of the strobe signal STB, that is, for each rate TAC is, as shown in FIG. 5, the time Ts1 corresponding to the minimum delay time ts and the maximum delay time te at the first rate TAC. Is the time Te1 corresponding to. Here, since the delay time of the timing of the strobe signal for each rate TAC is Δt, the rate T in the next test cycle
The output timing of the strobe signal STBS in the AC becomes time Ts2, which is later than the time Ts1 by the time Δt, and the output timing of the strobe signal STBE becomes earlier by the time Δt than the time Te1, and becomes the time Te2. The above processing is repeated, and the rate T of each test cycle is sequentially determined.
A strobe signal STB is output for each AC.

When the AC characteristic test is performed, the power supply voltage of the circuit under test is set to a predetermined power supply voltage, and the strobe signal STBS is supplied at the first rate TAC to the time Ts1.
, And it is determined whether or not the value of the output signal CH at that time matches the expected value “1”. At this time, since the value does not match the value of the expected value signal EV as shown in FIG. 5, the value of the mismatch signal FAILS is set to “0” and output. Next, strobe signal STBE is output at time Te1, and it is determined whether or not the value of output signal CH at that time matches value "1" of expected value EV. At this time, since the value matches the value of the expected value signal EV, the value of the mismatch signal FAILE is set to “0” and output.

The above processing is performed by setting the strobe signal STBS for each rate TAC at times Ts2, Ts3, Ts
4,..., And the value of the output signal CH and the expected value signal E
Repeat until the value of V matches. Also, the strobe signal S
TBE is sequentially output at times Te2, Te3, Te4.
This is repeated until the value of the output signal CH does not match the value of the expected value signal EV. During this processing, the strobe signal ST
When BE is output at time Te7, the value of output signal CH changes from threshold VOH or more to threshold V for the first time.
OH or less, and does not match the value “1” of the expected value signal EV. At this time, the value of the mismatch signal FAILE becomes “1”, and the mismatch signal FAIL becomes “1”.

Therefore, the delay time TD of the circuit under test is determined from the output time Te7 of the strobe signal STB, the AC characteristic at the power supply voltage set for the circuit under test is determined, and this test ends. By setting the next value of the power supply voltage of the circuit under test and repeating the above processing, the AC characteristics using the power supply voltage as a parameter can be obtained.

As described above, the two strobe signals STBS and STBE are changed by the time Δt from the minimum delay time ts and the maximum delay time te for each rate TAC.
The AC characteristics can be measured in a very short time by outputting. Even in the worst case, the AC characteristics can be measured in half the time required in the past. At this time, the strobe signal STBS and the strobe signal STBE
Are given by the following equation so that they coincide at the last output timing.

Maximum delay time te = minimum delay time ts + Δt × n (1) Δt: change time for each rate n: positive integer Further, strobe signal STBS or strobe signal S
When any of the signals of TBE is output, and when the fail signal FAIL is detected, the transition point of the output signal CH (the value of the output signal becomes equal to the threshold value VOH or (Changes to threshold VOL)
There are advantages that can be sought. But the rate TA
If there are two or more transitions of the output signal within the C time, an incorrect result may be obtained. In such a case, the measurement may be performed until the output timing of the strobe signal STBS matches the output timing of the strobe signal STBE. Therefore, even in such a case, the test time is reduced to a half of the conventional test time.

[0051]

As described above, according to the present invention, the first strobe generating means and the second strobe generating means set the maximum delay time, the minimum delay time, and the unit time based on the pattern signal. Each time, a strobe signal is generated once every test cycle at a time earlier than the maximum delay time by a unit time and later at a time later than the minimum delay time by a unit time. Therefore, by comparing the output signal of the semiconductor integrated circuit and the expected value measured by the comparing means twice in each test cycle in synchronization with the strobe signal, the delay time of the semiconductor integrated circuit can be shortened in a short time. Can be detected and its AC characteristics can be determined.

Thus, it is possible to obtain a semiconductor integrated circuit test apparatus capable of performing an AC characteristic test of the semiconductor integrated circuit in a short time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an electrical configuration of a test apparatus for a semiconductor integrated circuit according to one embodiment of the present invention.

FIG. 2 is a block diagram showing a more detailed electrical configuration of a comparison circuit 57 shown in FIG.

FIG. 3 is an electric circuit diagram of the comparison and judgment circuit 62 of the present invention shown in FIG.

FIG. 4 is a more detailed electric block diagram of the timing generation circuit 51 shown in FIG. 2;

FIG. 5 is a diagram showing an example of a method for determining a delay time of a circuit under test using the semiconductor integrated circuit test apparatus of the present invention shown in FIGS.
It is a time chart at the time of performing a C characteristic test.

FIG. 6 is an electric circuit diagram of a conventional comparison and judgment circuit 62.

FIG. 7 is a graph showing a result of measuring an AC characteristic of a circuit under test using the above-described semiconductor integrated circuit test apparatus.

[Explanation of symbols]

 Reference Signs List 50 pattern generator 51 timing generator 52 waveform format circuit 53 drive circuit 55 circuit under test 57 comparison circuit 61 storage circuit 62 comparison determination circuit 63 comparator 81 rate timing generation circuit 82 strobe S storage circuit 83 strobe E storage circuit 85, 102 addition 86 Strobe S output circuit 88 Subtractor 89 Strobe E output circuit 91, 92 Strobe variable delay circuit 100 A register 101 B register 105 Controller

Claims (1)

(57) [Claims] An input signal is supplied to an input terminal of a semiconductor integrated circuit, an output signal from an output terminal of the semiconductor integrated circuit is detected, and a delay time of the output signal with respect to the input signal is measured to obtain an AC characteristic. In a semiconductor integrated circuit test apparatus for performing a characteristic test, a waveform generating means for applying a predetermined input signal to an input terminal of the semiconductor integrated circuit for each predetermined test cycle; and an output signal from an output terminal of the semiconductor integrated circuit. Comparing means for comparing a predetermined expected value with a predetermined timing for each test cycle at a predetermined timing; and in a first test cycle, at a time after a predetermined minimum delay time elapses from the start of measurement of the AC characteristics for each test cycle, In a subsequent test cycle, a first strobe signal defining the predetermined timing is set at a time later by a predetermined unit time. A first strobe generating means for applying a signal to the comparing means, at a time after a predetermined maximum delay time elapses from the start of the measurement of the AC characteristics in each test cycle in a first test cycle, and in a subsequent test cycle. Second strobe generating means for providing a second strobe signal defining the predetermined timing to the comparing means at an earlier time by a unit time; and for each test cycle, the input signal, the expected value, the maximum delay time, A pattern signal that defines the minimum delay time and the unit time, a waveform generation unit, a comparison unit,
An apparatus for testing a semiconductor integrated circuit, comprising: a first strobe generating means; and a pattern signal generating means provided to a second strobe generating means.