JP2546066Y2 - Waveform generator - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform generator for, for example, an LSI tester, and more specifically, outputs a digital pulse waveform to a DUT (device under test) with high timing accuracy even when a format is switched. The present invention relates to a waveform generator capable of performing the above.

[0002]

2. Description of the Related Art An LSI tester gives a measurement signal to an LSI according to a pattern address, and compares a response signal output from the LSI based on the measurement signal with an expected value in real time to judge the quality of the LSI. I have. Conventionally, there are two methods for obtaining the measurement signal: a pinned type and a shared source type. In the share-dos-source method, since a signal of a timing generator shared by the entirety is switched and output to a formatter circuit provided for each pin, a delay error occurs in a measurement signal when the timing generator is switched. However, in the per-pin system, since a timing generator and a formatter circuit are provided for each pin of the LSI, a more accurate timing signal can be obtained as compared with the shared-source system.

[0003]

[Problems to be solved by the present invention]
In the pin-type LSI tester waveform generator, although the timing generator is provided separately for each pin, the timing generator and the formatter circuit are provided separately. Therefore, it was necessary to provide a delay line for correction.

The present invention has been made in view of such a point, and is to integrate the operation of the timing generator and the formatter, so that the rising / falling of the format can be accurately performed even when the format is changed. It is an object of the present invention to provide a waveform generator capable of setting timing.

[0005]

In order to achieve the above object, the present invention provides a waveform generator for arbitrarily generating a digital pulse waveform based on pattern data and format data. A timing set memory storing delay time data for each of the format data; and a start / stop based on the pattern data and the format data; First and second delay circuits for delaying the rising / falling timing of the output waveform specified by the format data by the data loaded from the timing set memory; and the first delay And a flip-flop that is set by the output of the pulse signal of the circuit and reset by the output of the pulse signal of the second delay circuit. It is characterized by obtaining a digital pulse waveform.

[0006]

The components of the present invention operate as follows. The timing set memory stores delay time data for each formatter data. The first and second delay circuits are started / stopped by the format data and the test rate signal, and output a pulse signal to the flip-flop based on the delay time data loaded from the timing set memory. I do. The flip-flop is set by the output of the first delay circuit and reset by the output of the second delay circuit.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a waveform generator according to an embodiment of the present invention. In the figure, reference numeral 1 denotes a pattern memory which outputs pattern data D1 and format data D2 to a controller 2 based on a pattern address AD1. The controller 2 activates / deactivates the first delay circuit 3 and the second delay circuit 4 according to the data of the pattern memory 2 latched by the test rate signal S1.
The first delay circuit 3 outputs the delayed pulse signal to the set terminal S of the RS flip-flop 5, and the second delay circuit 4 outputs the delayed pulse signal to the set terminal S of the RS flip-flop 5.

The first and second delay circuits 3 and 4 are composed of clock generators 31 and 41 and delay lines 32 and 42, respectively.
The delay time is set by the time using K as the resolution, and the delay lines 32 and 42 further set the resolution below the resolution of the clock generators 31 and 32. The delay time can be set over a cycle by providing a double clock generator.

Reference numeral 6 denotes a timing set memory, NRZ
(Non Retrun to Zero), RZ (Retrun to Zero), R
Delay time data such as O (Retrun to one) is stored, and the data is switched for each format data D2 input to the first and second delay circuits 3 and 4. Output (see FIG. 4).

FIG. 2 is a block diagram showing the configuration of the controller 2 extracted from FIG. The pattern data D1 input to the controller 2 is input in 1 bit.
The formatter data D2 is input in two bits. 41
Is an OR circuit. The pattern data D1 is input to one input terminal, and the upper bit D2M of the format data D2 is input to the other input terminal. Reference numeral 42 denotes a first D-type flip-flop. The output signal S2 of the OR circuit 41 is input to the D terminal, and the Q output is output to the first delay circuit in response to the test rate signal S1 input to the clock terminal. I do.

Reference numeral 43 denotes an AND circuit. One input terminal receives the upper bit D2M of the inverted format data D2, and the other input terminal receives the lower bit D2L of the format data D2. Have been. An OR circuit 44 has one input terminal to which an output signal of the AND circuit 44 is input.
The pattern data D1 inverted by the inverter 45 is input to the other input terminal. Reference numeral 46 denotes a second D-type flip-flop in which the output signal S3 of the OR circuit 44 is input to the D terminal and the test signal input to the clock terminal.
The Q output is output to the second delay circuit in response to the trigger signal S1. The controller may use a hardware sequencer to control the load, count, and stop of the clock generator.

FIG. 3 is a truth table showing a state where the first and second delay circuits are started / stopped by the output of the controller, and FIG. 4 is a waveform chart at that time. In the figure, ○ indicates an operable state, ★ indicates an inoperable state, and-indicates an undefined state. Also, ta indicates the set value of the faster delay time, and tb indicates the set value of the slower delay time.

FIG. 5 is a time chart for explaining the operation of the waveform generator according to the present invention, in which the format data is N.
This is a description of a case where the values are given in the order of RZ to RO to RZ. In the figure, (a) is a test rate signal S1 having a period T, (b) is format data D2, (c) is pattern data D1, and (d) is an output signal from the first delay circuit. S4, (e) is the output signal S5 from the second delay circuit,
(F) is a waveform S6 output from the RS flip-flop.
It is. Incidentally, t1 to t5 are data of delay times loaded from the timing memory to the delay circuits 3 and 4.

(1) The controller 2 decodes the input NRZ format data D2 and the pattern data D1 of "1" at the rise of the test rate signal S1. (2) As a result, the first delay circuit 3 is activated. (3) The first delay circuit 3 uses the pattern captured at the time of startup.
Based on "1" of the data D1 and the data of the delay time loaded from the timing set memory 6, a pulse signal S4 is output to the S terminal of the RS flip-flop 5 after a delay time t1.

(4) Subsequently, the format data D2 of the RO and the pattern data D1 of "0" are input to the controller 2. (5) The controller 2 activates the first and second delay circuits 3 and 4 in response to the next input test rate signal S1. (6) The second delay circuit 4 uses the pattern captured at the time of activation.
Based on "0" of the data D1 and the data of the delay time t loaded from the timing set memory 6, the pulse signal S5 is supplied to the RS flip-flop 5 after the delay time t2.
To the R terminal.

(7) On the other hand, the first delay circuit 3 is based on "0" of the pattern data taken together with the start-up and the delay time data loaded from the timing set memory 6. Then, after a delay time t3, the pulse signal S4 is output to the S terminal of the RS flip-flop 5. (8) Thereafter, the same operation is repeated for the RZ format data D2. The test rate signal S1
Is synchronous with the reference clock signal CK, and has a relationship of an integral multiple, for example, 20 to a reference clock signal period of 1 nsec.
The cycle is nsec.

[0017]

As described in detail above, the waveform generator of the present invention integrates the operation of the timing generator and the formatter. Fall timing can be set accurately. Further, since the delay circuit is controlled by the reference clock signal, the calibration of the delay time is easy.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a waveform generator according to an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a controller 2 extracted from FIG. 1;

FIG. 3 is a truth table showing a state in which first and second delay circuits are started / stopped by an output of a controller.

FIG. 4 is a waveform diagram for each format.

FIG. 5 is a time chart for explaining the operation of the waveform generator of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Pattern memory 2 Controller 3 First delay circuit 4 Second delay circuit 5 RS flip-flop 6 Timing set memory

Claims (1)

(57) [Scope of request for utility model registration] 1. A waveform generator for arbitrarily generating a digital pulse waveform based on pattern data and format data, wherein data of delay time is provided for each format data. It is started / stopped based on the stored timing set memory, the pattern data and the format data, and is loaded from the timing set memory.
First and second delay circuits for delaying rising / falling timings of output waveforms specified by the format data according to the input data, and output of a pulse signal of the first delay circuit. And a flip-flop that is set by the second delay circuit and reset by the output of the pulse signal of the second delay circuit, and obtains a target digital pulse waveform from the flip-flop.